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- add IDM_DEFSIZE to resource.h (luigi__ will have merge issues). 

- add code to use bios if the bios files exist. this code is preliminary. it seems to freeze games right now. to use this, make sure BiosNds7.ROM and BiosNds9.ROM exist in the application startup working directory. this is probably not a good way to do it, but it is a start.
- fix recently created spu issues with adpcm and psg.
- change execute = FALSE; to emu_pause(); so that other things can be done or disabled in one place.
- analyze performance of MatrixIdentity for speedup.
- accept crazymax's correction to my matrix caching. that was boneheaded, sorry!
This commit is contained in:
zeromus 2008-12-28 02:27:13 +00:00
parent 70a8af9942
commit 5a940dc2be
14 changed files with 2059 additions and 1999 deletions
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38
desmume/src/MMU.cpp
View File

@ -2040,7 +2040,7 @@ static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
} }
case REG_DISPB_DISPCNT+2 : case REG_DISPB_DISPCNT+2 :
{ {
//execute = FALSE; //emu_halt();
u32 v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000) & 0xFFFF) | ((u32) val << 16); u32 v = (T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000) & 0xFFFF) | ((u32) val << 16);
GPU_setVideoProp(SubScreen.gpu, v); GPU_setVideoProp(SubScreen.gpu, v);
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000, v); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x1000, v);
@ -2049,7 +2049,7 @@ static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
case REG_DMA0CNTH : case REG_DMA0CNTH :
{ {
u32 v; u32 v;
//if(val&0x8000) execute = FALSE; //if(val&0x8000) emu_halt();
//LOG("16 bit dma0 %04X\r\n", val); //LOG("16 bit dma0 %04X\r\n", val);
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xBA, val); T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xBA, val);
DMASrc[ARMCPU_ARM9][0] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xB0); DMASrc[ARMCPU_ARM9][0] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xB0);
@ -2070,7 +2070,7 @@ static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
case REG_DMA1CNTH : case REG_DMA1CNTH :
{ {
u32 v; u32 v;
//if(val&0x8000) execute = FALSE; //if(val&0x8000) emu_halt();
//LOG("16 bit dma1 %04X\r\n", val); //LOG("16 bit dma1 %04X\r\n", val);
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xC6, val); T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xC6, val);
DMASrc[ARMCPU_ARM9][1] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xBC); DMASrc[ARMCPU_ARM9][1] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xBC);
@ -2091,7 +2091,7 @@ static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
case REG_DMA2CNTH : case REG_DMA2CNTH :
{ {
u32 v; u32 v;
//if(val&0x8000) execute = FALSE; //if(val&0x8000) emu_halt();
//LOG("16 bit dma2 %04X\r\n", val); //LOG("16 bit dma2 %04X\r\n", val);
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xD2, val); T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xD2, val);
DMASrc[ARMCPU_ARM9][2] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xC8); DMASrc[ARMCPU_ARM9][2] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xC8);
@ -2112,7 +2112,7 @@ static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
case REG_DMA3CNTH : case REG_DMA3CNTH :
{ {
u32 v; u32 v;
//if(val&0x8000) execute = FALSE; //if(val&0x8000) emu_halt();
//LOG("16 bit dma3 %04X\r\n", val); //LOG("16 bit dma3 %04X\r\n", val);
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xDE, val); T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xDE, val);
DMASrc[ARMCPU_ARM9][3] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xD4); DMASrc[ARMCPU_ARM9][3] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0xD4);
@ -2131,7 +2131,7 @@ static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
#endif #endif
} }
return; return;
//case REG_AUXSPICNT : execute = FALSE; //case REG_AUXSPICNT : emu_halt();
} }
#ifdef _MMU_DEBUG #ifdef _MMU_DEBUG
mmu_log_debug_ARM9(adr, "(write16) %0x%X", val); mmu_log_debug_ARM9(adr, "(write16) %0x%X", val);
@ -2464,7 +2464,7 @@ static void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
LOG("ARMCPU_ARM9 %d, dma %d src %08X dst %08X start taille %d %d\r\n", ARMCPU_ARM9, 0, DMASrc[ARMCPU_ARM9][0], DMADst[ARMCPU_ARM9][0], 0, ((MMU.DMACrt[ARMCPU_ARM9][0]>>27)&7)); LOG("ARMCPU_ARM9 %d, dma %d src %08X dst %08X start taille %d %d\r\n", ARMCPU_ARM9, 0, DMASrc[ARMCPU_ARM9][0], DMADst[ARMCPU_ARM9][0], 0, ((MMU.DMACrt[ARMCPU_ARM9][0]>>27)&7));
} }
#endif #endif
//execute = FALSE; //emu_halt();
return; return;
case REG_DMA1CNTL: case REG_DMA1CNTL:
//LOG("32 bit dma1 %04X\r\n", val); //LOG("32 bit dma1 %04X\r\n", val);
@ -2579,7 +2579,7 @@ static void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
case REG_DISPA_BG0CNT : case REG_DISPA_BG0CNT :
GPU_setBGProp(MainScreen.gpu, 0, (val&0xFFFF)); GPU_setBGProp(MainScreen.gpu, 0, (val&0xFFFF));
GPU_setBGProp(MainScreen.gpu, 1, (val>>16)); GPU_setBGProp(MainScreen.gpu, 1, (val>>16));
//if((val>>16)==0x400) execute = FALSE; //if((val>>16)==0x400) emu_halt();
T1WriteLong(ARM9Mem.ARM9_REG, 8, val); T1WriteLong(ARM9Mem.ARM9_REG, 8, val);
return; return;
case REG_DISPA_BG2CNT : case REG_DISPA_BG2CNT :
@ -3006,14 +3006,14 @@ static void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
val = 0; val = 0;
break; break;
case 0x10 : case 0x10 :
//execute = FALSE; //emu_halt();
if(SPI_CNT&(1<<11)) if(SPI_CNT&(1<<11))
{ {
if(partie) if(partie)
{ {
val = ((nds.touchY<<3)&0x7FF); val = ((nds.touchY<<3)&0x7FF);
partie = 0; partie = 0;
//execute = FALSE; //emu_halt();
break; break;
} }
val = (nds.touchY>>5); val = (nds.touchY>>5);
@ -3102,7 +3102,7 @@ static void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
#endif #endif
return; return;
case REG_IE + 2 : case REG_IE + 2 :
//execute = FALSE; //emu_halt();
MMU.reg_IE[ARMCPU_ARM7] = (MMU.reg_IE[ARMCPU_ARM7]&0xFFFF) | (((u32)val)<<16); MMU.reg_IE[ARMCPU_ARM7] = (MMU.reg_IE[ARMCPU_ARM7]&0xFFFF) | (((u32)val)<<16);
#ifndef NEW_IRQ #ifndef NEW_IRQ
if ( MMU.reg_IME[ARMCPU_ARM7]) if ( MMU.reg_IME[ARMCPU_ARM7])
@ -3118,11 +3118,11 @@ static void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
return; return;
case REG_IF : case REG_IF :
//execute = FALSE; //emu_halt();
MMU.reg_IF[ARMCPU_ARM7] &= (~((u32)val)); MMU.reg_IF[ARMCPU_ARM7] &= (~((u32)val));
return; return;
case REG_IF + 2 : case REG_IF + 2 :
//execute = FALSE; //emu_halt();
MMU.reg_IF[ARMCPU_ARM7] &= (~(((u32)val)<<16)); MMU.reg_IF[ARMCPU_ARM7] &= (~(((u32)val)<<16));
return; return;
@ -3183,7 +3183,7 @@ static void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
{ {
u32 v; u32 v;
//if(val&0x8000) execute = FALSE; //if(val&0x8000) emu_halt();
//LOG("16 bit dma0 %04X\r\n", val); //LOG("16 bit dma0 %04X\r\n", val);
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xBA, val); T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xBA, val);
DMASrc[ARMCPU_ARM7][0] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xB0); DMASrc[ARMCPU_ARM7][0] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xB0);
@ -3204,7 +3204,7 @@ static void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
case REG_DMA1CNTH : case REG_DMA1CNTH :
{ {
u32 v; u32 v;
//if(val&0x8000) execute = FALSE; //if(val&0x8000) emu_halt();
//LOG("16 bit dma1 %04X\r\n", val); //LOG("16 bit dma1 %04X\r\n", val);
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xC6, val); T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xC6, val);
DMASrc[ARMCPU_ARM7][1] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xBC); DMASrc[ARMCPU_ARM7][1] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xBC);
@ -3225,7 +3225,7 @@ static void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
case REG_DMA2CNTH : case REG_DMA2CNTH :
{ {
u32 v; u32 v;
//if(val&0x8000) execute = FALSE; //if(val&0x8000) emu_halt();
//LOG("16 bit dma2 %04X\r\n", val); //LOG("16 bit dma2 %04X\r\n", val);
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xD2, val); T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xD2, val);
DMASrc[ARMCPU_ARM7][2] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xC8); DMASrc[ARMCPU_ARM7][2] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xC8);
@ -3246,7 +3246,7 @@ static void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
case REG_DMA3CNTH : case REG_DMA3CNTH :
{ {
u32 v; u32 v;
//if(val&0x8000) execute = FALSE; //if(val&0x8000) emu_halt();
//LOG("16 bit dma3 %04X\r\n", val); //LOG("16 bit dma3 %04X\r\n", val);
T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xDE, val); T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xDE, val);
DMASrc[ARMCPU_ARM7][3] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xD4); DMASrc[ARMCPU_ARM7][3] = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0xD4);
@ -3265,7 +3265,7 @@ static void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
#endif #endif
} }
return; return;
//case REG_AUXSPICNT : execute = FALSE; //case REG_AUXSPICNT : emu_halt();
} }
#ifdef _MMU_DEBUG #ifdef _MMU_DEBUG
mmu_log_debug_ARM7(adr, "(write16) %0x%X", val); mmu_log_debug_ARM7(adr, "(write16) %0x%X", val);
@ -3408,7 +3408,7 @@ static void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
LOG("ARMCPU_ARM7 %d, dma %d src %08X dst %08X start taille %d %d\r\n", ARMCPU_ARM7, 0, DMASrc[ARMCPU_ARM7][0], DMADst[ARMCPU_ARM7][0], 0, ((MMU.DMACrt[ARMCPU_ARM7][0]>>27)&7)); LOG("ARMCPU_ARM7 %d, dma %d src %08X dst %08X start taille %d %d\r\n", ARMCPU_ARM7, 0, DMASrc[ARMCPU_ARM7][0], DMADst[ARMCPU_ARM7][0], 0, ((MMU.DMACrt[ARMCPU_ARM7][0]>>27)&7));
} }
#endif #endif
//execute = FALSE; //emu_halt();
return; return;
case REG_DMA1CNTL: case REG_DMA1CNTL:
//LOG("32 bit dma1 %04X\r\n", val); //LOG("32 bit dma1 %04X\r\n", val);

62
desmume/src/NDSSystem.cpp
View File

@ -33,7 +33,7 @@
#include "ROMReader.h" #include "ROMReader.h"
#include "gfx3d.h" #include "gfx3d.h"
#include "utils/decrypt/decrypt.h" #include "utils/decrypt/decrypt.h"
#include "bios.h"
#include "debug.h" #include "debug.h"
#ifdef _WIN32 #ifdef _WIN32
@ -277,34 +277,34 @@ void NDS_releaseTouch(void)
void debug() void debug()
{ {
//if(NDS_ARM9.R[15]==0x020520DC) execute = FALSE; //if(NDS_ARM9.R[15]==0x020520DC) emu_halt();
//DSLinux //DSLinux
//if(NDS_ARM9.CPSR.bits.mode == 0) execute = FALSE; //if(NDS_ARM9.CPSR.bits.mode == 0) emu_halt();
//if((NDS_ARM9.R[15]&0xFFFFF000)==0) execute = FALSE; //if((NDS_ARM9.R[15]&0xFFFFF000)==0) emu_halt();
//if((NDS_ARM9.R[15]==0x0201B4F4)/*&&(NDS_ARM9.R[1]==0x0)*/) execute = FALSE; //if((NDS_ARM9.R[15]==0x0201B4F4)/*&&(NDS_ARM9.R[1]==0x0)*/) emu_halt();
//AOE //AOE
//if((NDS_ARM9.R[15]==0x01FFE194)&&(NDS_ARM9.R[0]==0)) execute = FALSE; //if((NDS_ARM9.R[15]==0x01FFE194)&&(NDS_ARM9.R[0]==0)) emu_halt();
//if((NDS_ARM9.R[15]==0x01FFE134)&&(NDS_ARM9.R[0]==0)) execute = FALSE; //if((NDS_ARM9.R[15]==0x01FFE134)&&(NDS_ARM9.R[0]==0)) emu_halt();
//BBMAN //BBMAN
//if(NDS_ARM9.R[15]==0x02098B4C) execute = FALSE; //if(NDS_ARM9.R[15]==0x02098B4C) emu_halt();
//if(NDS_ARM9.R[15]==0x02004924) execute = FALSE; //if(NDS_ARM9.R[15]==0x02004924) emu_halt();
//if(NDS_ARM9.R[15]==0x02004890) execute = FALSE; //if(NDS_ARM9.R[15]==0x02004890) emu_halt();
//if(NDS_ARM9.R[15]==0x0202B800) execute = FALSE; //if(NDS_ARM9.R[15]==0x0202B800) emu_halt();
//if(NDS_ARM9.R[15]==0x0202B3DC) execute = FALSE; //if(NDS_ARM9.R[15]==0x0202B3DC) emu_halt();
//if((NDS_ARM9.R[1]==0x9AC29AC1)&&(!fait)) {execute = FALSE;fait = TRUE;} //if((NDS_ARM9.R[1]==0x9AC29AC1)&&(!fait)) {emu_halt();fait = TRUE;}
//if(NDS_ARM9.R[1]==0x0400004A) {execute = FALSE;fait = TRUE;} //if(NDS_ARM9.R[1]==0x0400004A) {emu_halt();fait = TRUE;}
/*if(NDS_ARM9.R[4]==0x2E33373C) execute = FALSE; /*if(NDS_ARM9.R[4]==0x2E33373C) emu_halt();
if(NDS_ARM9.R[15]==0x02036668) //execute = FALSE; if(NDS_ARM9.R[15]==0x02036668) //emu_halt();
{ {
nds.logcount++; nds.logcount++;
sprintf(logbuf, "%d %08X", nds.logcount, NDS_ARM9.R[13]); sprintf(logbuf, "%d %08X", nds.logcount, NDS_ARM9.R[13]);
log::ajouter(logbuf); log::ajouter(logbuf);
if(nds.logcount==89) execute=FALSE; if(nds.logcount==89) execute=FALSE;
}*/ }*/
//if(NDS_ARM9.instruction==0) execute = FALSE; //if(NDS_ARM9.instruction==0) emu_halt();
//if((NDS_ARM9.R[15]>>28)) execute = FALSE; //if((NDS_ARM9.R[15]>>28)) emu_halt();
} }
#define DSGBA_EXTENSTION ".ds.gba" #define DSGBA_EXTENSTION ".ds.gba"
@ -546,7 +546,16 @@ void NDS_Reset( void)
//MMU_write32(0, 0x02007FFC, 0xE92D4030); //MMU_write32(0, 0x02007FFC, 0xE92D4030);
FILE* inf = 0;
//ARM7 BIOS IRQ HANDLER //ARM7 BIOS IRQ HANDLER
inf = fopen("BiosNds7.ROM","rb");
if(inf) {
fread(MMU.ARM7_BIOS,1,16384,inf);
fclose(inf);
NDS_ARM7.swi_tab = 0;
} else {
NDS_ARM7.swi_tab = ARM7_swi_tab;
MMU_write32(1, 0x00, 0xE25EF002); MMU_write32(1, 0x00, 0xE25EF002);
MMU_write32(1, 0x04, 0xEAFFFFFE); MMU_write32(1, 0x04, 0xEAFFFFFE);
MMU_write32(1, 0x18, 0xEA000000); MMU_write32(1, 0x18, 0xEA000000);
@ -556,8 +565,16 @@ void NDS_Reset( void)
MMU_write32(1, 0x2C, 0xE510F004); MMU_write32(1, 0x2C, 0xE510F004);
MMU_write32(1, 0x30, 0xE8BD500F); MMU_write32(1, 0x30, 0xE8BD500F);
MMU_write32(1, 0x34, 0xE25EF004); MMU_write32(1, 0x34, 0xE25EF004);
}
//ARM9 BIOS IRQ HANDLER //ARM9 BIOS IRQ HANDLER
inf = fopen("BiosNds9.ROM","rb");
if(inf) {
fread(ARM9Mem.ARM9_BIOS,1,4096,inf);
fclose(inf);
NDS_ARM9.swi_tab = 0;
} else {
NDS_ARM9.swi_tab = ARM9_swi_tab;
MMU_write32(0, 0xFFFF0018, 0xEA000000); MMU_write32(0, 0xFFFF0018, 0xEA000000);
MMU_write32(0, 0xFFFF0020, 0xE92D500F); MMU_write32(0, 0xFFFF0020, 0xE92D500F);
MMU_write32(0, 0xFFFF0024, 0xEE190F11); MMU_write32(0, 0xFFFF0024, 0xEE190F11);
@ -568,6 +585,10 @@ void NDS_Reset( void)
MMU_write32(0, 0xFFFF0038, 0xE510F004); MMU_write32(0, 0xFFFF0038, 0xE510F004);
MMU_write32(0, 0xFFFF003C, 0xE8BD500F); MMU_write32(0, 0xFFFF003C, 0xE8BD500F);
MMU_write32(0, 0xFFFF0040, 0xE25EF004); MMU_write32(0, 0xFFFF0040, 0xE25EF004);
}
MMU_write32(0, 0x0000004, 0xE3A0010E); MMU_write32(0, 0x0000004, 0xE3A0010E);
MMU_write32(0, 0x0000008, 0xE3A01020); MMU_write32(0, 0x0000008, 0xE3A01020);
@ -1803,6 +1824,11 @@ void NDS_setPad(bool R,bool L,bool D,bool U,bool T,bool S,bool B,bool A,bool Y,b
// TODO: low power IRQ // TODO: low power IRQ
} }
void emu_halt() {
execute = false;
}
//these templates needed to be instantiated manually //these templates needed to be instantiated manually
template u32 NDS_exec<FALSE>(s32 nb); template u32 NDS_exec<FALSE>(s32 nb);
template u32 NDS_exec<TRUE>(s32 nb); template u32 NDS_exec<TRUE>(s32 nb);

5
desmume/src/NDSSystem.h
View File

@ -102,6 +102,7 @@ typedef struct
} NDS_header; } NDS_header;
extern void debug(); extern void debug();
void emu_halt();
typedef struct typedef struct
{ {
@ -232,7 +233,7 @@ inline u32 NDS_exec(s32 nb) { return NDS_exec<false>(nb); }
{ {
MMU.reg_IF[0] |= 1;// & (MMU.reg_IME[0]);// (MMU.reg_IE[0] & 1); MMU.reg_IF[0] |= 1;// & (MMU.reg_IME[0]);// (MMU.reg_IE[0] & 1);
NDS_ARM9.wIRQ = TRUE; NDS_ARM9.wIRQ = TRUE;
//execute = FALSE; //emu_halt();
/*logcount++;*/ /*logcount++;*/
} }
} }
@ -242,7 +243,7 @@ inline u32 NDS_exec(s32 nb) { return NDS_exec<false>(nb); }
if(T1ReadWord(MMU.ARM7_REG, 4) & 0x8) if(T1ReadWord(MMU.ARM7_REG, 4) & 0x8)
MMU.reg_IF[1] |= 1;// & (MMU.reg_IME[1]);// (MMU.reg_IE[1] & 1); MMU.reg_IF[1] |= 1;// & (MMU.reg_IME[1]);// (MMU.reg_IE[1] & 1);
NDS_ARM7.wIRQ = TRUE; NDS_ARM7.wIRQ = TRUE;
//execute = FALSE; //emu_halt();
} }
static INLINE void NDS_swapScreen(void) static INLINE void NDS_swapScreen(void)

39
desmume/src/SPU.cpp
View File

@ -792,7 +792,7 @@ static void SPU_ChanUpdate8LR(SPU_struct* SPU, channel_struct *chan)
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
static void SPU_ChanUpdateNoMix(SPU_struct *SPU, channel_struct *chan) static void SPU_ChanUpdate8NoMix(SPU_struct *SPU, channel_struct *chan)
{ {
for (; SPU->bufpos < SPU->buflength; SPU->bufpos++) for (; SPU->bufpos < SPU->buflength; SPU->bufpos++)
{ {
@ -837,6 +837,16 @@ static void SPU_ChanUpdate8R(SPU_struct* SPU, channel_struct *chan)
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
static void SPU_ChanUpdate16NoMix(SPU_struct *SPU, channel_struct *chan)
{
for (; SPU->bufpos < SPU->buflength; SPU->bufpos++)
{
// check to see if we're passed the length and need to loop, etc.
TestForLoop(SPU, chan);
}
}
static void SPU_ChanUpdate16LR(SPU_struct* SPU, channel_struct *chan) static void SPU_ChanUpdate16LR(SPU_struct* SPU, channel_struct *chan)
{ {
for (; SPU->bufpos < SPU->buflength; SPU->bufpos++) for (; SPU->bufpos < SPU->buflength; SPU->bufpos++)
@ -891,6 +901,16 @@ static void SPU_ChanUpdate16R(SPU_struct* SPU, channel_struct *chan)
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
static void SPU_ChanUpdateADPCMNoMix(SPU_struct *SPU, channel_struct *chan)
{
for (; SPU->bufpos < SPU->buflength; SPU->bufpos++)
{
// check to see if we're passed the length and need to loop, etc.
TestForLoop2(SPU, chan);
}
}
static void SPU_ChanUpdateADPCMLR(SPU_struct* SPU, channel_struct *chan) static void SPU_ChanUpdateADPCMLR(SPU_struct* SPU, channel_struct *chan)
{ {
for (; SPU->bufpos < SPU->buflength; SPU->bufpos++) for (; SPU->bufpos < SPU->buflength; SPU->bufpos++)
@ -945,6 +965,15 @@ static void SPU_ChanUpdateADPCMR(SPU_struct* SPU, channel_struct *chan)
////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////
static void SPU_ChanUpdatePSGNoMix(SPU_struct* SPU, channel_struct *chan)
{
for (; SPU->bufpos < SPU->buflength; SPU->bufpos++)
{
chan->sampcnt += chan->sampinc;
}
}
static void SPU_ChanUpdatePSGLR(SPU_struct* SPU, channel_struct *chan) static void SPU_ChanUpdatePSGLR(SPU_struct* SPU, channel_struct *chan)
{ {
for (; SPU->bufpos < SPU->buflength; SPU->bufpos++) for (; SPU->bufpos < SPU->buflength; SPU->bufpos++)
@ -1001,25 +1030,25 @@ void (*SPU_ChanUpdate[4][4])(SPU_struct* SPU, channel_struct *chan) = {
SPU_ChanUpdate8L, SPU_ChanUpdate8L,
SPU_ChanUpdate8LR, SPU_ChanUpdate8LR,
SPU_ChanUpdate8R, SPU_ChanUpdate8R,
SPU_ChanUpdateNoMix SPU_ChanUpdate8NoMix
}, },
{ // 16-bit PCM { // 16-bit PCM
SPU_ChanUpdate16L, SPU_ChanUpdate16L,
SPU_ChanUpdate16LR, SPU_ChanUpdate16LR,
SPU_ChanUpdate16R, SPU_ChanUpdate16R,
SPU_ChanUpdateNoMix, SPU_ChanUpdate16NoMix,
}, },
{ // IMA-ADPCM { // IMA-ADPCM
SPU_ChanUpdateADPCML, SPU_ChanUpdateADPCML,
SPU_ChanUpdateADPCMLR, SPU_ChanUpdateADPCMLR,
SPU_ChanUpdateADPCMR, SPU_ChanUpdateADPCMR,
SPU_ChanUpdateNoMix SPU_ChanUpdateADPCMNoMix
}, },
{ // PSG/White Noise { // PSG/White Noise
SPU_ChanUpdatePSGL, SPU_ChanUpdatePSGL,
SPU_ChanUpdatePSGLR, SPU_ChanUpdatePSGLR,
SPU_ChanUpdatePSGR, SPU_ChanUpdatePSGR,
SPU_ChanUpdateNoMix SPU_ChanUpdatePSGNoMix
} }
}; };

68
desmume/src/arm_instructions.cpp
View File

@ -31,6 +31,7 @@
#include "debug.h" #include "debug.h"
#include "MMU.h" #include "MMU.h"
#include "armcpu.h" #include "armcpu.h"
#include "NDSSystem.h"
#define cpu (&ARMPROC) #define cpu (&ARMPROC)
#define TEMPLATE template<int PROCNUM> #define TEMPLATE template<int PROCNUM>
@ -248,7 +249,7 @@ extern volatile BOOL execute;
TEMPLATE static u32 FASTCALL OP_UND() TEMPLATE static u32 FASTCALL OP_UND()
{ {
LOG("Undefined instruction: %08X\n", cpu->instruction); LOG("Undefined instruction: %08X\n", cpu->instruction);
execute = FALSE; emu_halt();
LOG("Stopped (OP_UND)\n"); LOG("Stopped (OP_UND)\n");
return 1; return 1;
} }
@ -269,7 +270,7 @@ TEMPLATE static u32 FASTCALL OP_UND()
} \ } \
else \ else \
{ \ { \
execute = FALSE; \ emu_halt(); \
return 4; \ return 4; \
} \ } \
@ -5033,7 +5034,7 @@ TEMPLATE static u32 FASTCALL OP_STR_P_IMM_OFF()
u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12; u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]); WRITE32(cpu->mem_if->data, adr, cpu->R[REG_POS(i,12)]);
// execute = false; // emu_halt();
return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF]; return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF];
} }
@ -5791,7 +5792,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_M_IMM_OFF_POSTIND()
return 2; return 2;
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDRBT_M_IMM_OFF_POSTIND\n"); LOG("Untested opcode: OP_LDRBT_M_IMM_OFF_POSTIND\n");
@ -5817,7 +5818,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_P_REG_OFF_POSTIND()
return 2; return 2;
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDRBT_P_REG_OFF_POSTIND\n"); LOG("Untested opcode: OP_LDRBT_P_REG_OFF_POSTIND\n");
@ -5843,7 +5844,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSL_IMM_OFF_POSTIND()
if(cpu->CPSR.bits.mode==USR) if(cpu->CPSR.bits.mode==USR)
return 2; return 2;
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDRBT_P_LSL_IMM_OFF_POSTIND\n"); LOG("Untested opcode: OP_LDRBT_P_LSL_IMM_OFF_POSTIND\n");
@ -5871,7 +5872,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSL_IMM_OFF_POSTIND()
return 2; return 2;
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDRBT_M_LSL_IMM_OFF_POSTIND\n"); LOG("Untested opcode: OP_LDRBT_M_LSL_IMM_OFF_POSTIND\n");
@ -5899,7 +5900,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_P_LSR_IMM_OFF_POSTIND()
return 2; return 2;
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDRBT_P_LSR_IMM_OFF_POSTIND\n"); LOG("Untested opcode: OP_LDRBT_P_LSR_IMM_OFF_POSTIND\n");
@ -5927,7 +5928,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_M_LSR_IMM_OFF_POSTIND()
return 2; return 2;
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDRBT_M_LSR_IMM_OFF_POSTIND\n"); LOG("Untested opcode: OP_LDRBT_M_LSR_IMM_OFF_POSTIND\n");
@ -5955,7 +5956,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_P_ASR_IMM_OFF_POSTIND()
return 2; return 2;
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDRBT_P_ASR_IMM_OFF_POSTIND\n"); LOG("Untested opcode: OP_LDRBT_P_ASR_IMM_OFF_POSTIND\n");
@ -5983,7 +5984,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_M_ASR_IMM_OFF_POSTIND()
return 2; return 2;
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDRBT_M_ASR_IMM_OFF_POSTIND\n"); LOG("Untested opcode: OP_LDRBT_M_ASR_IMM_OFF_POSTIND\n");
@ -6011,7 +6012,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_P_ROR_IMM_OFF_POSTIND()
return 2; return 2;
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDRBT_P_ROR_IMM_OFF_POSTIND\n"); LOG("Untested opcode: OP_LDRBT_P_ROR_IMM_OFF_POSTIND\n");
@ -6039,7 +6040,7 @@ TEMPLATE static u32 FASTCALL OP_LDRBT_M_ROR_IMM_OFF_POSTIND()
return 2; return 2;
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDRBT_M_ROR_IMM_OFF_POSTIND\n"); LOG("Untested opcode: OP_LDRBT_M_ROR_IMM_OFF_POSTIND\n");
@ -6774,7 +6775,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2()
u32 start = cpu->R[REG_POS(i,16)]; u32 start = cpu->R[REG_POS(i,16)];
u32 * registres; u32 * registres;
TWaitState* waitState; TWaitState* waitState;
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDMIB2\n"); LOG("Untested opcode: OP_LDMIB2\n");
if(BIT15(i)==0) if(BIT15(i)==0)
@ -6833,7 +6834,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2()
TWaitState* waitState; TWaitState* waitState;
u32 start = cpu->R[REG_POS(i,16)]; u32 start = cpu->R[REG_POS(i,16)];
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_LDMDA2\n"); LOG("Untested opcode: OP_LDMDA2\n");
if(BIT15(i)==0) if(BIT15(i)==0)
@ -6958,7 +6959,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2_W()
TWaitState* waitState; TWaitState* waitState;
u32 tmp; u32 tmp;
Status_Reg SPSR; Status_Reg SPSR;
// execute = FALSE; // emu_halt();
if(BIT15(i)==0) if(BIT15(i)==0)
{ {
if(cpu->CPSR.bits.mode==USR) if(cpu->CPSR.bits.mode==USR)
@ -7073,7 +7074,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDA2_W()
u32 * registres; u32 * registres;
TWaitState * waitState; TWaitState * waitState;
Status_Reg SPSR; Status_Reg SPSR;
// execute = FALSE; // emu_halt();
if(BIT15(i)==0) if(BIT15(i)==0)
{ {
if(cpu->CPSR.bits.mode==USR) if(cpu->CPSR.bits.mode==USR)
@ -7133,7 +7134,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB2_W()
u32 * registres; u32 * registres;
TWaitState* waitState; TWaitState* waitState;
Status_Reg SPSR; Status_Reg SPSR;
// execute = FALSE; // emu_halt();
if(BIT15(i)==0) if(BIT15(i)==0)
{ {
if(cpu->CPSR.bits.mode==USR) if(cpu->CPSR.bits.mode==USR)
@ -7352,7 +7353,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA2()
start = cpu->R[REG_POS(i,16)]; start = cpu->R[REG_POS(i,16)];
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_STMIA2\n"); LOG("Untested opcode: OP_STMIA2\n");
for(b=0; b<16; ++b) for(b=0; b<16; ++b)
@ -7383,7 +7384,7 @@ TEMPLATE static u32 FASTCALL OP_STMIB2()
start = cpu->R[REG_POS(i,16)]; start = cpu->R[REG_POS(i,16)];
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_STMIB2\n"); LOG("Untested opcode: OP_STMIB2\n");
for(b=0; b<16; ++b) for(b=0; b<16; ++b)
@ -7414,7 +7415,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA2()
start = cpu->R[REG_POS(i,16)]; start = cpu->R[REG_POS(i,16)];
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_STMDA2\n"); LOG("Untested opcode: OP_STMDA2\n");
for(b=0; b<16; ++b) for(b=0; b<16; ++b)
@ -7473,7 +7474,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA2_W()
start = cpu->R[REG_POS(i,16)]; start = cpu->R[REG_POS(i,16)];
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_STMIA2_W\n"); LOG("Untested opcode: OP_STMIA2_W\n");
for(b=0; b<16; ++b) for(b=0; b<16; ++b)
@ -7533,7 +7534,7 @@ TEMPLATE static u32 FASTCALL OP_STMDA2_W()
c = 0; c = 0;
start = cpu->R[REG_POS(i,16)]; start = cpu->R[REG_POS(i,16)];
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_STMDA2_W\n"); LOG("Untested opcode: OP_STMDA2_W\n");
for(b=0; b<16; ++b) for(b=0; b<16; ++b)
@ -7567,7 +7568,7 @@ TEMPLATE static u32 FASTCALL OP_STMDB2_W()
start = cpu->R[REG_POS(i,16)]; start = cpu->R[REG_POS(i,16)];
oldmode = armcpu_switchMode(cpu, SYS); oldmode = armcpu_switchMode(cpu, SYS);
//execute = FALSE; //emu_halt();
LOG("Untested opcode: OP_STMDB2_W\n"); LOG("Untested opcode: OP_STMDB2_W\n");
for(b=0; b<16; ++b) for(b=0; b<16; ++b)
@ -7757,7 +7758,7 @@ TEMPLATE static u32 FASTCALL OP_MCR()
if(!cpu->coproc[cpnum]) if(!cpu->coproc[cpnum])
{ {
execute = FALSE; emu_halt();
LOG("Stopped (OP_MCR)\n"); LOG("Stopped (OP_MCR)\n");
return 2; return 2;
} }
@ -7776,7 +7777,7 @@ TEMPLATE static u32 FASTCALL OP_MRC()
if(!cpu->coproc[cpnum]) if(!cpu->coproc[cpnum])
{ {
execute = FALSE; emu_halt();
LOG("Stopped (OP_MRC)\n"); LOG("Stopped (OP_MRC)\n");
return 2; return 2;
} }
@ -7789,26 +7790,23 @@ TEMPLATE static u32 FASTCALL OP_MRC()
//--------------SWI------------------------------- //--------------SWI-------------------------------
TEMPLATE static u32 FASTCALL OP_SWI() TEMPLATE static u32 FASTCALL OP_SWI()
{ {
if (((cpu->intVector != 0) ^ (PROCNUM == ARMCPU_ARM9))) if(cpu->swi_tab) {
{ u32 swinum = (cpu->instruction>>16)&0x1F;
return cpu->swi_tab[swinum](cpu) + 3;
} else {
/* TODO (#1#): translocated SWI vectors */ /* TODO (#1#): translocated SWI vectors */
/* we use an irq thats not in the irq tab, as /* we use an irq thats not in the irq tab, as
it was replaced duie to a changed intVector */ it was replaced duie to a changed intVector */
Status_Reg tmp = cpu->CPSR; Status_Reg tmp = cpu->CPSR;
armcpu_switchMode(cpu, SVC); /* enter svc mode */ armcpu_switchMode(cpu, SVC); /* enter svc mode */
cpu->R[14] = cpu->R[15] - 4; /* jump to swi Vector */ cpu->R[14] = cpu->next_instruction;
cpu->SPSR = tmp; /* save old CPSR as new SPSR */ cpu->SPSR = tmp; /* save old CPSR as new SPSR */
cpu->CPSR.bits.T = 0; /* handle as ARM32 code */ cpu->CPSR.bits.T = 0; /* handle as ARM32 code */
cpu->CPSR.bits.I = cpu->SPSR.bits.I; /* keep int disable flag */ cpu->CPSR.bits.I = 1;
cpu->R[15] = cpu->intVector + 0x08; cpu->R[15] = cpu->intVector + 0x08;
cpu->next_instruction = cpu->R[15]; cpu->next_instruction = cpu->R[15];
return 4; return 4;
} }
else
{
u32 swinum = (cpu->instruction>>16)&0x1F;
return cpu->swi_tab[swinum](cpu) + 3;
}
} }
//----------------BKPT------------------------- //----------------BKPT-------------------------

5
desmume/src/armcpu.cpp
View File

@ -181,11 +181,6 @@ int armcpu_new( armcpu_t *armcpu, u32 id)
{ {
armcpu->proc_ID = id; armcpu->proc_ID = id;
if(id==0)
armcpu->swi_tab = ARM9_swi_tab;
else
armcpu->swi_tab = ARM7_swi_tab;
#ifdef GDB_STUB #ifdef GDB_STUB
armcpu->mem_if = mem_if; armcpu->mem_if = mem_if;

4
desmume/src/bios.cpp
View File

@ -212,7 +212,7 @@ static u32 intrWaitARM(armcpu_t * cpu)
u32 intr; u32 intr;
u32 intrFlag = 0; u32 intrFlag = 0;
//execute = FALSE; //emu_halt();
if(cpu->proc_ID) if(cpu->proc_ID)
{ {
intrFlagAdr = 0x380FFF8; intrFlagAdr = 0x380FFF8;
@ -246,7 +246,7 @@ static u32 waitVBlankARM(armcpu_t * cpu)
u32 intr; u32 intr;
u32 intrFlag = 0; u32 intrFlag = 0;
//execute = FALSE; //emu_halt();
if(cpu->proc_ID) if(cpu->proc_ID)
{ {
intrFlagAdr = 0x380FFF8; intrFlagAdr = 0x380FFF8;

21
desmume/src/gfx3d.cpp
View File

@ -624,23 +624,26 @@ static void SetVertex()
break; break;
} }
if(completed) { if(completed)
{
POLY &poly = polylist->list[polylist->count]; POLY &poly = polylist->list[polylist->count];
//todo - dont overrun proj list //todo - dont overrun proj list
//see if the last entry in the proj list matches the current matrix, if there is one. //see if the last entry in the proj list matches the current matrix, if there is one.
if(projlist->count != 0 && if(projlist->count != 0 &&
//but as a speed hack, we consider the matrices different if the first element differs. //here is an example of something that does not work.
//i think this should be good enough. //(for a speed hack, we consider the matrices different if the first element differs)
!MatrixCompare(mtxCurrent[0],projlist->projMatrix[projlist->count-1])
// if compare only one value this is broke some games
// zeromus check it please
//mtxCurrent[0][0] == projlist->projMatrix[projlist->count-1][0] //mtxCurrent[0][0] == projlist->projMatrix[projlist->count-1][0]
) {
//here is what we must do: make sure the matrices are identical
!MatrixCompare(mtxCurrent[0],projlist->projMatrix[projlist->count-1])
)
{
//it matches. use it //it matches. use it
poly.projIndex = projlist->count-1; poly.projIndex = projlist->count-1;
} else { }
else
{
MatrixCopy(projlist->projMatrix[projlist->count],mtxCurrent[0]); MatrixCopy(projlist->projMatrix[projlist->count],mtxCurrent[0]);
poly.projIndex = projlist->count; poly.projIndex = projlist->count;
projlist->count++; projlist->count++;

9
desmume/src/matrix.cpp
View File

@ -127,7 +127,14 @@ void MatrixTranspose(float *matrix)
void MATRIXFASTCALL MatrixIdentity (float *matrix) //============== TODO void MATRIXFASTCALL MatrixIdentity (float *matrix) //============== TODO
{ {
memset (matrix, 0, sizeof(float)*16); //memset (matrix, 0, sizeof(float)*16);
//this is fastest for SSE2 i think.
//study code generation and split into sse2 specific module later
for(int i=0;i<16;i++)
matrix[i] = 0.0f;
//matrix[1] = matrix[2] = matrix[3] = matrix[4] = 0.0f;
//matrix[6] = matrix[7] = matrix[8] = matrix[9] = 0.0f;
//matrix[11] = matrix[12] = matrix[13] = matrix[14] = 0.0f;
matrix[0] = matrix[5] = matrix[10] = matrix[15] = 1.f; matrix[0] = matrix[5] = matrix[10] = matrix[15] = 1.f;
} }

36
desmume/src/thumb_instructions.cpp
View File

@ -32,6 +32,7 @@
#include "bios.h" #include "bios.h"
#include "debug.h" #include "debug.h"
#include "MMU.h" #include "MMU.h"
#include "NDSSystem.h"
#define cpu (&ARMPROC) #define cpu (&ARMPROC)
#define TEMPLATE template<int PROCNUM> #define TEMPLATE template<int PROCNUM>
@ -59,7 +60,7 @@ extern volatile BOOL execute;
TEMPLATE static u32 FASTCALL OP_UND_THUMB() TEMPLATE static u32 FASTCALL OP_UND_THUMB()
{ {
execute = FALSE; emu_halt();
return 1; return 1;
} }
@ -448,7 +449,7 @@ TEMPLATE static u32 FASTCALL OP_CMN()
const u32 &i = cpu->instruction; const u32 &i = cpu->instruction;
u32 tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)]; u32 tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)];
//execute = FALSE; //emu_halt();
//log::ajouter("OP_CMN THUMB"); //log::ajouter("OP_CMN THUMB");
cpu->CPSR.bits.N = BIT31(tmp); cpu->CPSR.bits.N = BIT31(tmp);
cpu->CPSR.bits.Z = tmp == 0; cpu->CPSR.bits.Z = tmp == 0;
@ -891,29 +892,26 @@ TEMPLATE static u32 FASTCALL OP_B_COND()
TEMPLATE static u32 FASTCALL OP_SWI_THUMB() TEMPLATE static u32 FASTCALL OP_SWI_THUMB()
{ {
if (((cpu->intVector != 0) ^ (PROCNUM == ARMCPU_ARM9))) if(cpu->swi_tab) {
{
/* we use an irq thats not in the irq tab, as
it was replaced duie to a changed intVector */
Status_Reg tmp = cpu->CPSR;
armcpu_switchMode(cpu, SVC); /* enter svc mode */
cpu->R[14] = cpu->R[15] - 4; /* jump to swi Vector */
cpu->SPSR = tmp; /* save old CPSR as new SPSR */
cpu->CPSR.bits.T = 0; /* handle as ARM32 code */
cpu->CPSR.bits.I = cpu->SPSR.bits.I; /* keep int disable flag */
cpu->R[15] = cpu->intVector + 0x08;
cpu->next_instruction = cpu->R[15];
return 3;
}
else
{
//zero 25-dec-2008 - in arm, we were masking to 0x1F. //zero 25-dec-2008 - in arm, we were masking to 0x1F.
//this is probably safer since an invalid opcode could crash the emu //this is probably safer since an invalid opcode could crash the emu
//u32 swinum = cpu->instruction & 0xFF; //u32 swinum = cpu->instruction & 0xFF;
u32 swinum = cpu->instruction & 0x1F; u32 swinum = cpu->instruction & 0x1F;
return cpu->swi_tab[swinum](cpu) + 3; return cpu->swi_tab[swinum](cpu) + 3;
} }
//return 3; else {
/* we use an irq thats not in the irq tab, as
it was replaced duie to a changed intVector */
Status_Reg tmp = cpu->CPSR;
armcpu_switchMode(cpu, SVC); /* enter svc mode */
cpu->R[14] = cpu->next_instruction; /* jump to swi Vector */
cpu->SPSR = tmp; /* save old CPSR as new SPSR */
cpu->CPSR.bits.T = 0; /* handle as ARM32 code */
cpu->CPSR.bits.I = 1;
cpu->R[15] = cpu->intVector + 0x08;
cpu->next_instruction = cpu->R[15];
return 3;
}
} }
#define SIGNEEXT_IMM11(i) (((i)&0x7FF) | (BIT10(i) * 0xFFFFF800)) #define SIGNEEXT_IMM11(i) (((i)&0x7FF) | (BIT10(i) * 0xFFFFF800))

6
desmume/src/windows/main.cpp
View File

@ -1019,7 +1019,7 @@ DWORD WINAPI run()
if (frameAdvance) if (frameAdvance)
{ {
frameAdvance = false; frameAdvance = false;
execute = FALSE; emu_halt();
SPU_Pause(1); SPU_Pause(1);
} }
frameCounter++; frameCounter++;
@ -1043,7 +1043,7 @@ void NDS_Pause()
{ {
if (!paused) if (!paused)
{ {
execute = FALSE; emu_halt();
paused = TRUE; paused = TRUE;
SPU_Pause(1); SPU_Pause(1);
while (!paused) {} while (!paused) {}
@ -1229,7 +1229,7 @@ int RegClass(WNDPROC Proc, LPCTSTR szName)
static void ExitRunLoop() static void ExitRunLoop()
{ {
finished = TRUE; finished = TRUE;
execute = FALSE; emu_halt();
} }
int WINAPI WinMain (HINSTANCE hThisInstance, int WINAPI WinMain (HINSTANCE hThisInstance,

1
desmume/src/windows/resource.h
View File

@ -101,6 +101,7 @@
#define IDC_LANGENGLISH 210 #define IDC_LANGENGLISH 210
#define IDC_LANGFRENCH 211 #define IDC_LANGFRENCH 211
#define IDC_LANGDANISH 212 #define IDC_LANGDANISH 212
#define IDM_DEFSIZE 213
#define IDD_MEM_VIEWER 301 #define IDD_MEM_VIEWER 301
#define IDC_8_BIT 302 #define IDC_8_BIT 302
#define IDC_16_BIT 303 #define IDC_16_BIT 303

2
desmume/src/windows/resources.rc
View File

@ -8,6 +8,7 @@
// Generated from the TEXTINCLUDE 2 resource. // Generated from the TEXTINCLUDE 2 resource.
// //
#include "afxres.h" #include "afxres.h"
///////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////
#undef APSTUDIO_READONLY_SYMBOLS #undef APSTUDIO_READONLY_SYMBOLS
@ -2363,6 +2364,7 @@ END
// Generated from the TEXTINCLUDE 3 resource. // Generated from the TEXTINCLUDE 3 resource.
// //
///////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////
#endif // not APSTUDIO_INVOKED #endif // not APSTUDIO_INVOKED