AR: implemented some codes and fixed early my commit
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ea58962012
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438800961e
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@ -171,6 +171,8 @@ static void cheats_ARparser(CHEATS_LIST cheat)
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u8 subtype = 0;
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u32 hi = 0;
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u32 lo = 0;
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u32 addr = 0;
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u32 val = 0;
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// AR temporary vars & flags
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u32 offset = 0;
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u32 datareg = 0;
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@ -183,7 +185,7 @@ static void cheats_ARparser(CHEATS_LIST cheat)
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type = cheat.hi[i] >> 28;
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subtype = (cheat.hi[i] >> 24) & 0x0F;
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hi = cheat.hi[i] & 0x00FFFFFF;
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hi = cheat.hi[i] & 0x0FFFFFFF;
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lo = cheat.lo[i];
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#ifdef AR_DISASM
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cheatsDisassemble_AR(cheat.hi[i], cheat.lo[i]);
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@ -216,132 +218,238 @@ static void cheats_ARparser(CHEATS_LIST cheat)
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//parameter bytes 9..10 for above code (padded with 00s)
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}
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else
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi + offset, lo);
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{
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addr = hi + offset;
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][addr>>20], addr & MMU.MMU_MASK[ARMCPU_ARM9][addr>>20], lo);
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}
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}
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break;
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case 0x01:
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi + offset, lo & 0x0000FFFF);
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addr = hi + offset;
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][addr>>20], addr & MMU.MMU_MASK[ARMCPU_ARM9][addr>>20], lo & 0x0000FFFF);
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break;
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case 0x02:
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T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi + offset, lo & 0x000000FF);
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addr = hi + offset;
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T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM9][addr>>20], addr & MMU.MMU_MASK[ARMCPU_ARM9][addr>>20], lo & 0x000000FF);
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break;
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case 0x03:
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if ( lo > T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi) )
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val = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][hi>>20], hi & MMU.MMU_MASK[ARMCPU_ARM9][hi>>20]);
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if ( lo > val )
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{
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if (if_flag > 0) if_flag--;
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}
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else
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{
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if_flag++;
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if (if_flag > 32) {
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if (if_flag > 32)
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{
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LOG("AR: error in 'if' expression (type %i)\n", type);
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}
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}
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break;
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case 0x04:
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if ( lo < T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi) )
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val = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][hi>>20], hi & MMU.MMU_MASK[ARMCPU_ARM9][hi>>20]);
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if ( lo < val )
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{
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if (if_flag > 0) if_flag--;
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}
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else
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{
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if_flag++;
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if (if_flag > 32) {
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if (if_flag > 32)
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{
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LOG("AR: error in 'if' expression (type %i)\n", type);
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}
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}
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break;
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case 0x05:
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if ( lo == T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi) )
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val = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][hi>>20], hi & MMU.MMU_MASK[ARMCPU_ARM9][hi>>20]);
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if ( lo == val )
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{
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if (if_flag > 0) if_flag--;
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}
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else
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{
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if_flag++;
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if (if_flag > 32) {
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if (if_flag > 32)
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{
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LOG("AR: error in 'if' expression (type %i)\n", type);
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}
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}
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break;
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case 0x06:
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if ( lo != T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi) )
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val = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][hi>>20], hi & MMU.MMU_MASK[ARMCPU_ARM9][hi>>20]);
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if ( lo != val )
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{
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if (if_flag > 0) if_flag--;
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}
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else
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{
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if_flag++;
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if (if_flag > 32) {
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if (if_flag > 32)
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{
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LOG("AR: error in 'if' expression (type %i)\n", type);
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}
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}
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break;
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case 0x07:
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if ( (lo & 0xFFFF) > ( (~(lo >> 16)) & T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi)) )
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val = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][hi>>20], hi & MMU.MMU_MASK[ARMCPU_ARM9][hi>>20]) & 0x0000FFFF;
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if ( (lo & 0xFFFF) > ( (~(lo >> 16)) & val) )
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{
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if (if_flag > 0) if_flag--;
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}
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else
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{
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if_flag++;
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if (if_flag > 32) {
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if (if_flag > 32)
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{
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LOG("AR: error in 'if' expression (type %i)\n", type);
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}
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}
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break;
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case 0x08:
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if ( (lo & 0xFFFF) < ( (~(lo >> 16)) & T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi)) )
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val = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][hi>>20], hi & MMU.MMU_MASK[ARMCPU_ARM9][hi>>20]) & 0x0000FFFF;
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if ( (lo & 0xFFFF) < ( (~(lo >> 16)) & val) )
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{
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if (if_flag > 0) if_flag--;
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}
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else
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{
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if_flag++;
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if (if_flag > 32) {
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if (if_flag > 32)
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{
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LOG("AR: error in 'if' expression (type %i)\n", type);
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}
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}
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break;
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case 0x09:
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if ( (lo & 0xFFFF) == ( (~(lo >> 16)) & T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi)) )
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val = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][hi>>20], hi & MMU.MMU_MASK[ARMCPU_ARM9][hi>>20]);
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if ( (lo & 0xFFFF) == ( (~(lo >> 16)) & val) )
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{
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if (if_flag > 0) if_flag--;
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}
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else
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{
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if_flag++;
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if (if_flag > 32) {
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if (if_flag > 32)
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{
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LOG("AR: error in 'if' expression (type %i)\n", type);
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}
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}
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break;
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case 0x0A:
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if ( (lo & 0xFFFF) != ( (~(lo >> 16)) & T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi)) )
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val = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][hi>>20], hi & MMU.MMU_MASK[ARMCPU_ARM9][hi>>20]) & 0x0000FFFF;
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if ( (lo & 0xFFFF) != ( (~(lo >> 16)) & val) )
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{
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if (if_flag > 0) if_flag--;
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}
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else
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{
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if_flag++;
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if (if_flag > 32) {
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if (if_flag > 32)
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{
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LOG("AR: error in 'if' expression (type %i)\n", type);
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}
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}
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break;
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case 0x0B:
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offset = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x20], hi + offset);
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addr = hi + offset;
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offset = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][addr>>20], addr & MMU.MMU_MASK[ARMCPU_ARM9][addr>>20]) & 0x0000FFFF;
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break;
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case 0x0C:
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switch (subtype)
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{
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case 0x0:
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break;
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case 0x4:
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break;
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case 0x5:
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break;
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case 0x6:
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break;
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}
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break;
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case 0x0D:
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{
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switch (subtype)
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{
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case 0x0:
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case 0x1:
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case 0x2:
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break;
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case 0x3:
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offset = lo;
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break;
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case 0x4:
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datareg += lo;
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break;
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case 0x5:
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datareg = lo;
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break;
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case 0x6:
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addr = lo + offset;
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][addr>>20], addr & MMU.MMU_MASK[ARMCPU_ARM9][addr>>20], datareg);
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offset += 4;
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break;
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case 0x7:
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addr = lo + offset;
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][addr>>20], addr & MMU.MMU_MASK[ARMCPU_ARM9][addr>>20], datareg & 0x0000FFFF);
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offset += 2;
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break;
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case 0x8:
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addr = lo + offset;
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T1WriteByte(MMU.MMU_MEM[ARMCPU_ARM9][addr>>20], addr & MMU.MMU_MASK[ARMCPU_ARM9][addr>>20], datareg & 0x000000FF);
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offset += 1;
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break;
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case 0x9:
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addr = lo + offset;
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datareg = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][addr>>20], addr & MMU.MMU_MASK[ARMCPU_ARM9][addr>>20]);
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break;
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case 0xA:
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addr = lo + offset;
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datareg = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][addr>>20], addr & MMU.MMU_MASK[ARMCPU_ARM9][addr>>20]) & 0x0000FFFF;
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break;
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case 0xB:
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addr = lo + offset;
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datareg = T1ReadByte(MMU.MMU_MEM[ARMCPU_ARM9][addr>>20], addr & MMU.MMU_MASK[ARMCPU_ARM9][addr>>20]) & 0x000000FF;
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break;
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case 0xC:
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offset += lo;
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break;
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}
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}
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break;
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case 0xE:
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break;
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case 0xF:
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break;
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//default: INFO("AR: ERROR uknown command 0x%2X at %08X:%08X\n", type, hi, lo); break;
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