Minor correction related to commit e8328eda
.
- If this doesn't fix Linux builds (it probably won't), then I will partially revert commit e8328eda
to make it work.
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@ -295,7 +295,7 @@ typedef __m128i v128s32;
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// Note: Technically, the shift count of palignr can be any value of [0-255]. But practically speaking, the
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// shift count should be a value of [0-15]. If we assume that the value range will always be [0-15], we can
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// then substitute the palignr instruction with an SSE2 equivalent.
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#define _mm_alignr_epi8(a, b, immShiftCount) _mm_or_si128(_mm_slli_si128(a, 16-(immShiftCount)), _mm_srli_si128(b, (immShiftCount)))
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#define _mm_alignr_epi8(a, b, immShiftCount) _mm_or_si128(_mm_slli_si128((a), 16-(immShiftCount)), _mm_srli_si128((b), (immShiftCount)))
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#endif // ENABLE_SSSE3
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#ifdef ENABLE_SSE4_1
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