[ 2488334 ] fix (SPP affine rotation display bug)
also start capturing register disp3dcnt but not using it for anything yet
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0f8211ec84
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@ -1,6 +1,6 @@
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0.9 -> 0/10
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General/Core:
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bug: SF [ 2550645 ] Super Princess Peach: crash when starting a puzzle [zeromus]
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bug: [ 2550645 ] Super Princess Peach: crash when starting a puzzle [zeromus]
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bug: win32: fix spu wav file writer (regression from 0.8) [zeromus]
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bug: More variables added to savestate. Savestates probably invalidated.
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@ -14,6 +14,7 @@ Graphics:
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bug: fix texture coordinate generation from normal (fixes environment mapping) [zeromus]
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bug: fix display capturing from 2d+3d source when display mode is display-vram [zeromus]
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bug: more correct mosaic effects [zeromus]
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bug: [ 2488334 ].3 added affine BG parameter writebacks to support hdma of params instead of only auto mode [zeromus]
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enh: dont memcmp for texcache validity when the texture banks arent unmapping (speedup) [zeromus]
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Mac OS X Port:
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@ -1702,8 +1702,8 @@ FORCEINLINE void rot_scale_op(GPU * gpu, u8 * dst, u16 H, s32 X, s32 Y, s16 PA,
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u32 i;
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s32 auxX, auxY;
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x.val = X + (s32)PB*(s32)H;
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y.val = Y + (s32)PD*(s32)H;
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x.val = X + (s32)H;
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y.val = Y + (s32)H;
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for(i = 0; i < LG; ++i)
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{
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@ -1817,6 +1817,8 @@ void lineRot(GPU * gpu, u8 num, u16 l, u8 * DST)
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parms->BGxPC,
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parms->BGxPD,
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256);
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parms->BGxX += parms->BGxPB;
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parms->BGxY += parms->BGxPD;
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}
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void lineExtRot(GPU * gpu, u8 num, u16 l, u8 * DST)
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@ -1835,6 +1837,8 @@ void lineExtRot(GPU * gpu, u8 num, u16 l, u8 * DST)
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parms->BGxPC,
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parms->BGxPD,
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256);
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parms->BGxX += parms->BGxPB;
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parms->BGxY += parms->BGxPD;
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}
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void textBG(GPU * gpu, u8 num, u8 * DST)
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@ -2905,9 +2909,9 @@ static void GPU_ligne_layer(NDS_Screen * screen, u16 l)
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gpu3D->NDS_3D_GetLine(l, 0, 255, line3Dcolor, line3Dalpha);
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for(int k = 0, q = 0; k < 256; k++)
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for(int k = 0; k < 256; k++)
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{
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q = ((k + hofs) & 0x1FF);
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int q = ((k + hofs) & 0x1FF);
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if(line3Dcolor[q] & 0x8000)
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gpu->setFinalColor3D(gpu, (k << 1), dst, line3Dcolor[q], line3Dalpha[q], k);
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@ -1569,6 +1569,19 @@ static void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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{
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switch(adr)
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{
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case REG_DISPA_DISP3DCNT:
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{
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u32 &disp3dcnt = MainScreen.gpu->dispx_st->dispA_DISP3DCNT.val;
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disp3dcnt = (disp3dcnt&0xFF00) | val;
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break;
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}
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case REG_DISPA_DISP3DCNT+1:
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{
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u32 &disp3dcnt = MainScreen.gpu->dispx_st->dispA_DISP3DCNT.val;
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disp3dcnt = (disp3dcnt&0x00FF) | (val<<8);
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break;
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}
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case REG_DISPA_WIN0H:
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GPU_setWIN0_H1(MainScreen.gpu, val);
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break ;
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@ -1781,6 +1794,12 @@ static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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// Address is an IO register
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switch(adr)
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{
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case REG_DISPA_DISP3DCNT:
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{
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MainScreen.gpu->dispx_st->dispA_DISP3DCNT.val = val;
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break;
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}
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// Alpha test reference value - Parameters:1
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case 0x04000340:
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{
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