ShuriZma
/
desmume
mirror of https://github.com/TASEmulators/desmume.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

core: 

- added display memory FIFO;
This commit is contained in:
mtabachenko 2009-01-18 13:43:05 +00:00
parent 5b53b8c73e
commit 38bdc6c2f2
4 changed files with 50 additions and 36 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
desmume/src/FIFO.cpp
View File

@ -171,3 +171,29 @@ void GFX_FIFOsend(u32 cmd, u32 param)
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x600, gxstat);
}
// ========================================================= DISP FIFO
DISP_FIFO disp_fifo;
void DISP_FIFOinit()
{
memset(&disp_fifo, 0, sizeof(DISP_FIFO));
}
void DISP_FIFOsend(u32 val)
{
//INFO("DISP_FIFO send value 0x%08X (head 0x%06X, tail 0x%06X)\n", val, disp_fifo.head, disp_fifo.tail);
disp_fifo.buf[disp_fifo.tail] = val;
disp_fifo.tail++;
if (disp_fifo.tail > 0x5FFF)
disp_fifo.tail = 0;
}
u32 DISP_FIFOrecv()
{
u32 val = disp_fifo.buf[disp_fifo.head];
disp_fifo.head++;
if (disp_fifo.head > 0x5FFF)
disp_fifo.head = 0;
return (val);
}

17
desmume/src/FIFO.h
View File

@ -54,20 +54,15 @@ extern void GFX_FIFOclear();
extern void GFX_FIFOsend(u32 cmd, u32 param);
//=================================================== Display memory FIFO
#if 0
typedef struct
{
u32 buf[16]; // 16 words
u8 size; // tail
BOOL empty;
BOOL full;
BOOL error;
u32 buf[0x6000]; // 256x192 32K color
u32 head; // head
u32 tail; // tail
} DISP_FIFO;
extern void DISP_FIFOclear(DISP_FIFO * fifo);
extern void DISP_FIFOadd(DISP_FIFO * fifo, u32 val);
extern u32 DISP_FIFOget(DISP_FIFO * fifo);
#endif
extern void DISP_FIFOinit();
extern void DISP_FIFOsend(u32 val);
extern u32 DISP_FIFOrecv();
#endif

23
desmume/src/GPU.cpp
View File

@ -3109,9 +3109,6 @@ static INLINE void GPU_ligne_MasterBrightness(NDS_Screen * screen, u16 l)
// Bright up
case 1:
{
// when we wont do anything, we dont need to loop
if (!(gpu->MasterBrightFactor)) break ;
for(i16 = 0; i16 < 256; ++i16)
{
((u16*)dst)[i16] = fadeInColors[gpu->MasterBrightFactor][((u16*)dst)[i16]&0x7FFF];
@ -3122,9 +3119,6 @@ static INLINE void GPU_ligne_MasterBrightness(NDS_Screen * screen, u16 l)
// Bright down
case 2:
{
// when we wont do anything, we dont need to loop
if (!gpu->MasterBrightFactor) break;
for(i16 = 0; i16 < 256; ++i16)
{
((u16*)dst)[i16] = fadeOutColors[gpu->MasterBrightFactor][((u16*)dst)[i16]&0x7FFF];
@ -3172,23 +3166,12 @@ void GPU_ligne(NDS_Screen * screen, u16 l)
memcpy (dst, src, 512);
}
break;
case 3:
// Read from FIFO MAIN_MEMORY_DISP_FIFO, two pixels at once format is x555, bit15 unused
// Reference: http://nocash.emubase.de/gbatek.htm#dsvideocaptureandmainmemorydisplaymode
// (under DISP_MMEM_FIFO)
#if 0
case 3: // Display memory FIFO
{
u8 * dst = GPU_screen + (screen->offset + l) * 512;
for (int i=0; i<256;)
{
u32 c = FIFOget(&gpu->fifo);
T2WriteWord(dst, i << 1, c&0xFFFF); i++;
T2WriteWord(dst, i << 1, c>>16); i++;
}
for (int i=0; i < 128; i++)
T1WriteLong(dst, i << 2, DISP_FIFOrecv() & 0x7FFF7FFF);
}
#else
LOG("FIFO MAIN_MEMORY_DISP_FIFO\n");
#endif
break;
}

20
desmume/src/MMU.cpp
View File

@ -370,6 +370,7 @@ void MMU_Init(void) {
IPC_FIFOinit(ARMCPU_ARM9);
IPC_FIFOinit(ARMCPU_ARM7);
GFX_FIFOclear();
DISP_FIFOinit();
mc_init(&MMU.fw, MC_TYPE_FLASH); /* init fw device */
mc_alloc(&MMU.fw, NDS_FW_SIZE_V1);
@ -435,6 +436,7 @@ void MMU_clearMem()
IPC_FIFOinit(ARMCPU_ARM9);
IPC_FIFOinit(ARMCPU_ARM7);
GFX_FIFOclear();
DISP_FIFOinit();
MMU.DTCMRegion = 0x027C0000;
MMU.ITCMRegion = 0x00000000;
@ -742,7 +744,6 @@ static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
if (vram_map_addr != 0xFFFFFFFF)
{
//u32 vr = vram_map_addr;
u8 engine = (vram_map_addr >> 21);
vram_map_addr &= 0x001FFFFF;
u8 engine_offset = (vram_map_addr >> 14);
@ -752,9 +753,8 @@ static inline void MMU_VRAMmapControl(u8 block, u8 VRAMBankCnt)
for (unsigned int i = 0; i < LCDdata[block][1]; i++)
MMU.VRAM_MAP[engine][engine_offset + i] = (u8)block;
//INFO("VRAM %i mapping: eng=%i (offs=%i, size=%i), addr = 0x%X, MST=%i (faddr 0x%X)\n",
// block, engine, engine_offset, LCDdata[block][1]*0x4000, MMU.LCD_VRAM_ADDR[block], VRAMBankCnt & 0x07,
// vr + 0x6000000);
//INFO("VRAM %i mapping: eng=%i (offs=%i, size=%i), addr = 0x%X, MST=%i\n",
// block, engine, engine_offset, LCDdata[block][1]*0x4000, MMU.LCD_VRAM_ADDR[block], VRAMBankCnt & 0x07);
VRAM_blockEnabled[block] = 1;
return;
}
@ -1665,6 +1665,11 @@ static void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
case REG_VRAMCNTI:
MMU_VRAMmapControl(adr-REG_VRAMCNTA, val);
break;
case REG_DISPA_DISPMMEMFIFO:
{
DISP_FIFOsend(val);
return;
}
#ifdef LOG_CARD
case 0x040001A0 : /* TODO (clear): ??? */
case 0x040001A1 :
@ -2232,6 +2237,11 @@ static void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
}
return;
//case REG_AUXSPICNT : emu_halt();
case REG_DISPA_DISPMMEMFIFO:
{
DISP_FIFOsend(val);
return;
}
}
#ifdef _MMU_DEBUG
mmu_log_debug_ARM9(adr, "(write16) %0x%X", val);
@ -2736,7 +2746,7 @@ static void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
return;
case REG_DISPA_DISPMMEMFIFO:
{
//FIFOadd(&MainScreen.gpu->fifo, val);
DISP_FIFOsend(val);
return;
}
}