core:

- 1st step for MMU split for procs (speedup);
- some changes in FIFO;

desmume/src/FIFO.cpp

@@ -25,38 +25,48 @@
 #include <string.h>
 #include "debug.h"
 
-void FIFOclear(FIFO * fifo)
+void IPC_FIFOclear(IPC_FIFO * fifo)
 {
-	memset(fifo,0,sizeof(FIFO));
+	memset(fifo, 0, sizeof(fifo));
-	fifo->empty = true;
-}
 
-void FIFOadd(FIFO *fifo, u32 val)
+	fifo->empty = TRUE;
+	//LOG("FIFO is cleared\n");
+}
+void IPC_FIFOadd(IPC_FIFO * fifo, u32 val)
 {
 	if (fifo->full)
 	{
+		//LOG("FIFO send is full\n");
 		fifo->error = true;
 		return;
 	}
 
-	fifo->buf[fifo->sendPos] = val;
+	//LOG("IPC FIFO add value 0x%08X in pos %i\n", val, fifo->size);
-	fifo->sendPos = (fifo->sendPos+1) & 0x7FFF;
+
-	fifo->half = (fifo->sendPos < 0x4000);
+	fifo->buf[fifo->size] = val;
-	fifo->full = (fifo->sendPos == fifo->recvPos);
+	fifo->size++;
-	fifo->empty = false;
+	if (fifo->size == 16)
+		fifo->full = TRUE;
+	fifo->empty = FALSE;
 }
 
-u32 FIFOget(FIFO * fifo)
+extern void NDS_Pause();
+u32 IPC_FIFOget(IPC_FIFO * fifo)
 {
 	if (fifo->empty)
 	{
 		fifo->error = true;
-		return 0;
+		//LOG("FIFO get is empty\n");
+		return(0);
 	}
 
-	u32 val;
+	u32 val = fifo->buf[0];
-	val = fifo->buf[fifo->recvPos];
+	//LOG("IPC FIFO get value 0x%08X in pos %i\n", val, fifo->size);
-	fifo->recvPos = (fifo->recvPos+1) & 0x7FFF;
+	for (int i = 0; i < fifo->size; i++)
-	fifo->empty = (fifo->recvPos == fifo->sendPos);
+		fifo->buf[i] = fifo->buf[i+1];
+	fifo->size--;
+	if (fifo->size == 0)
+		fifo->empty = TRUE;
 	return val;
 }
+

desmume/src/FIFO.h

@@ -28,22 +28,40 @@
 
 typedef struct
 {
-	BOOL	error;
+	u32		buf[16];		// 16 words
-	BOOL	enable;	
+	u8		size;			// tail
 
 	BOOL	empty;
-	BOOL	half;
 	BOOL	full;
-	u8		irq;
+	BOOL	error;
+} IPC_FIFO;
 
-	u16		sendPos;
+typedef struct
-	u16		recvPos;
+{
+	u32		buf[16];		// 16 words
+	u8		size;			// tail
 
-	u32		buf[0x8000];
+	BOOL	empty;
-} FIFO;
+	BOOL	full;
+	BOOL	error;
+} GFX_FIFO;
 
-extern void FIFOclear(FIFO * fifo);
+typedef struct
-extern void FIFOadd(FIFO * fifo, u32 val);
+{
-extern u32 FIFOget(FIFO * fifo);
+	u32		buf[16];		// 16 words
+	u8		size;			// tail
+
+	BOOL	empty;
+	BOOL	full;
+	BOOL	error;
+} DISP_FIFO;
+
+extern void IPC_FIFOclear(IPC_FIFO * fifo);
+extern void IPC_FIFOadd(IPC_FIFO * fifo, u32 val);
+extern u32 IPC_FIFOget(IPC_FIFO * fifo);
+
+//extern void GFX_FIFOclear(GFX_FIFO * fifo);
+//extern void GFX_FIFOadd(GFX_FIFO * fifo, u32 val);
+//extern u32 GFX_FIFOget(GFX_FIFO * fifo);
 
 #endif

desmume/src/GPU.cpp

@@ -214,6 +214,7 @@ void GPU_Reset(GPU *g, u8 l)
 
 	delete osd;
 	osd = new OSDCLASS(-1);
+	//DISP_FIFOclear(&g->disp_fifo);
 }
 
 void GPU_DeInit(GPU * gpu)
@@ -317,6 +318,7 @@ void GPU_setVideoProp(GPU * gpu, u32 p)
 		case 2: // Display framebuffer
 	//              gpu->vramBlock = DISPCNT_VRAMBLOCK(p) ;
 			gpu->vramBlock = cnt->VRAM_Block;
+			gpu->VRAMaddr = (u8 *)ARM9Mem.ARM9_LCD + (cnt->VRAM_Block * 0x20000);
 			return;
 		case 3: // Display from Main RAM
 			// nothing to be done here
@@ -758,11 +760,9 @@ INLINE void renderline_textBG(const GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG,
 
 	map = (u8 *)MMU_RenderMapToLCD(gpu->BG_map_ram[num] + (tmp&31) * 64);
 	if (!map) return;
-
+	
 	if(tmp>31) 
-	{
 		map+= ADDRESS_STEP_512B << bgCnt->ScreenSize ;
-	}
 
 	tile = (u8*) MMU_RenderMapToLCD(gpu->BG_tile_ram[num]);
 	if(!tile) return; 	// no tiles
@@ -1044,7 +1044,9 @@ INLINE void apply_rot_fun(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16
 INLINE void rotBG2(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA, s16 PB, s16 PC, s16 PD, u16 LG)
 {
 	u8 * map = (u8 *)MMU_RenderMapToLCD(gpu->BG_map_ram[num]);
+	if (!map) return;
 	u8 * tile = (u8 *)MMU_RenderMapToLCD(gpu->BG_tile_ram[num]);
+	if (!tile) return;
 	u8 * pal = ARM9Mem.ARM9_VMEM + gpu->core * 0x400;
 //	printf("rot mode\n");
 	apply_rot_fun(gpu, num, dst, H,X,Y,PA,PB,PC,PD,LG, rot_tiled_8bit_entry, map, tile, pal);
@@ -1065,7 +1067,9 @@ INLINE void extRotBG2(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA,
 	case 0 :
 	case 1 :
 		map = (u8 *)MMU_RenderMapToLCD(gpu->BG_map_ram[num]);
+		if (!map) return;
 		tile = (u8 *)MMU_RenderMapToLCD(gpu->BG_tile_ram[num]);
+		if (!tile) return;
 		pal = ARM9Mem.ExtPal[gpu->core][gpu->BGExtPalSlot[num]];
 		if (!pal) return;
 
@@ -2343,11 +2347,10 @@ static INLINE void GPU_ligne_Brightness(NDS_Screen * screen, u16 l)
 #endif
 }
 
+extern void* memcpy_fast(void* dest, const void* src, size_t count);
 void GPU_ligne(NDS_Screen * screen, u16 l)
 {
 	GPU * gpu = screen->gpu;
-	u8 * dst =  GPU_screen + (screen->offset + l) * 512;
-
 	// initialize the scanline black
 	// not doing this causes invalid colors when all active BGs are prevented to draw at some place
 	// ZERO TODO - shouldnt this be BG palette color 0?
@@ -2357,8 +2360,12 @@ void GPU_ligne(NDS_Screen * screen, u16 l)
 	switch (gpu->dispMode)
 	{
 		case 0: // Display Off(Display white)
+			{
+				u8 * dst =  GPU_screen + (screen->offset + l) * 512;
+
 				for (int i=0; i<256; i++)
 					T2WriteWord(dst, i << 1, 0x7FFF);
+			}
 			break;
 
 		case 1: // Display BG and OBJ layers
@@ -2366,25 +2373,28 @@ void GPU_ligne(NDS_Screen * screen, u16 l)
 			break;
 
 		case 2: // Display framebuffer
-		{
+			{
-			struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
+				u8 * dst = GPU_screen + (screen->offset + l) * 512;
-			u8 * vram = ARM9Mem.ARM9_LCD + (dispCnt->VRAM_Block * 0x20000) + (l*512);
+				u8 * src = gpu->VRAMaddr + (l*512);
-			memcpy(dst, vram, 512);
+				memcpy(dst, gpu->VRAMaddr + (l*512), 512);
-		}
+			}
 			break;
 		case 3:
 	// Read from FIFO MAIN_MEMORY_DISP_FIFO, two pixels at once format is x555, bit15 unused
 	// Reference:  http://nocash.emubase.de/gbatek.htm#dsvideocaptureandmainmemorydisplaymode
 	// (under DISP_MMEM_FIFO)
-#if 1
+#if 0
-			for (int i=0; i<256;)
 			{
-				u32 c = FIFOget(&MMU.fifos[gpu->core]);		// TODO: this is incorrect
+				u8 * dst =  GPU_screen + (screen->offset + l) * 512;
-				T2WriteWord(dst, i << 1, c&0xFFFF); i++;
+				for (int i=0; i<256;)
-				T2WriteWord(dst, i << 1, c>>16); i++;
+				{
+					u32 c = FIFOget(&gpu->fifo);
+					T2WriteWord(dst, i << 1, c&0xFFFF); i++;
+					T2WriteWord(dst, i << 1, c>>16); i++;
+				}
 			}
 #else
-		INFO("FIFO MAIN_MEMORY_DISP_FIFO\n");
+		LOG("FIFO MAIN_MEMORY_DISP_FIFO\n");
 #endif
 			break;
 	}

desmume/src/GPU.h

@@ -615,6 +615,9 @@ struct _GPU
 
 	u8 dispMode;
 	u8 vramBlock;
+	u8 *VRAMaddr;
+
+	//FIFO	fifo;
 
 	BOOL dispBG[4];
 	BOOL dispOBJ;

desmume/src/MMU.h

@@ -2,7 +2,7 @@
     yopyop156@ifrance.com
     yopyop156.ifrance.com
 
-	Copyright (C) 2007 shash
+	Copyright (C) 2007-2008 DeSmuME team
 
     This file is part of DeSmuME
 
@@ -76,10 +76,10 @@ struct MMU_struct {
     
     u8 ARM9_RW_MODE;
 
-	FIFO	fifos[2];	// 0 - ARM9 FIFO
+	IPC_FIFO	ipc_fifo[2];	// 0 - ARM9 FIFO
-						// 1 - ARM7 FIFO
+								// 1 - ARM7 FIFO*/
 
-    static TWaitState MMU_WAIT16[2][16];
+	static TWaitState MMU_WAIT16[2][16];
     static TWaitState MMU_WAIT32[2][16];
 
     u32 DTCMRegion;

desmume/src/saves.cpp

@@ -209,24 +209,16 @@ SFORMAT SF_MMU[]={
 	{ "MCHD", 4, 1,       &MMU.CheckDMAs},
 
 	//fifos
-	{ "F0ER", 4, 1,       &MMU.fifos[0].error},
+	{ "F0ER", 4, 1,       &MMU.ipc_fifo[0].error},
-	{ "F0EN", 4, 1,       &MMU.fifos[0].enable},
+	{ "F0EM", 4, 1,       &MMU.ipc_fifo[0].empty},
-	{ "F0EM", 4, 1,       &MMU.fifos[0].empty},
+	{ "F0FU", 4, 1,       &MMU.ipc_fifo[0].full},
-	{ "F0HA", 4, 1,       &MMU.fifos[0].half},
+	{ "F0SZ", 1, 1,       &MMU.ipc_fifo[0].size},
-	{ "F0FU", 4, 1,       &MMU.fifos[0].full},
+	{ "F0BU", 4, 16,	  &MMU.ipc_fifo[0].buf},
-	{ "F0IR", 1, 1,       &MMU.fifos[0].irq},
+	{ "F1ER", 4, 1,       &MMU.ipc_fifo[1].error},
-	{ "F0SP", 1, 1,       &MMU.fifos[0].sendPos},
+	{ "F1EM", 4, 1,       &MMU.ipc_fifo[1].empty},
-	{ "F0RP", 1, 1,       &MMU.fifos[0].recvPos},
+	{ "F1FU", 4, 1,       &MMU.ipc_fifo[1].full},
-	{ "F0BU", 1, 0x8000,  &MMU.fifos[0].buf},
+	{ "F1SZ", 1, 1,       &MMU.ipc_fifo[1].size},
-	{ "F1ER", 4, 1,       &MMU.fifos[1].error},
+	{ "F1BU", 4, 16,	  &MMU.ipc_fifo[1].buf},
-	{ "F1EN", 4, 1,       &MMU.fifos[1].enable},
-	{ "F1EM", 4, 1,       &MMU.fifos[1].empty},
-	{ "F1HA", 4, 1,       &MMU.fifos[1].half},
-	{ "F1FU", 4, 1,       &MMU.fifos[1].full},
-	{ "F1IR", 1, 1,       &MMU.fifos[1].irq},
-	{ "F1SP", 1, 1,       &MMU.fifos[1].sendPos},
-	{ "F1RP", 1, 1,       &MMU.fifos[1].recvPos},
-	{ "F1BU", 1, 0x8000,  &MMU.fifos[1].buf},
 	{ 0 }
 };