ShuriZma
/
desmume
mirror of https://github.com/TASEmulators/desmume.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

core: 

- 1st step for MMU split for procs (speedup);
- some changes in FIFO;
This commit is contained in:
mtabachenko 2008-12-14 14:56:26 +00:00
parent 9e8dada75e
commit 36da3ccf07
7 changed files with 2763 additions and 2263 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
desmume/src/FIFO.cpp
View File

@ -25,38 +25,48 @@
#include <string.h>
#include "debug.h"
void FIFOclear(FIFO * fifo)
void IPC_FIFOclear(IPC_FIFO * fifo)
{
memset(fifo,0,sizeof(FIFO));
fifo->empty = true;
}
memset(fifo, 0, sizeof(fifo));
void FIFOadd(FIFO *fifo, u32 val)
fifo->empty = TRUE;
//LOG("FIFO is cleared\n");
}
void IPC_FIFOadd(IPC_FIFO * fifo, u32 val)
{
if (fifo->full)
{
//LOG("FIFO send is full\n");
fifo->error = true;
return;
}
fifo->buf[fifo->sendPos] = val;
fifo->sendPos = (fifo->sendPos+1) & 0x7FFF;
fifo->half = (fifo->sendPos < 0x4000);
fifo->full = (fifo->sendPos == fifo->recvPos);
fifo->empty = false;
//LOG("IPC FIFO add value 0x%08X in pos %i\n", val, fifo->size);
fifo->buf[fifo->size] = val;
fifo->size++;
if (fifo->size == 16)
fifo->full = TRUE;
fifo->empty = FALSE;
}
u32 FIFOget(FIFO * fifo)
extern void NDS_Pause();
u32 IPC_FIFOget(IPC_FIFO * fifo)
{
if (fifo->empty)
{
fifo->error = true;
return 0;
//LOG("FIFO get is empty\n");
return(0);
}
u32 val;
val = fifo->buf[fifo->recvPos];
fifo->recvPos = (fifo->recvPos+1) & 0x7FFF;
fifo->empty = (fifo->recvPos == fifo->sendPos);
u32 val = fifo->buf[0];
//LOG("IPC FIFO get value 0x%08X in pos %i\n", val, fifo->size);
for (int i = 0; i < fifo->size; i++)
fifo->buf[i] = fifo->buf[i+1];
fifo->size--;
if (fifo->size == 0)
fifo->empty = TRUE;
return val;
}

40
desmume/src/FIFO.h
View File

@ -28,22 +28,40 @@
typedef struct
{
BOOL error;
BOOL enable;
u32 buf[16]; // 16 words
u8 size; // tail
BOOL empty;
BOOL half;
BOOL full;
u8 irq;
BOOL error;
} IPC_FIFO;
u16 sendPos;
u16 recvPos;
typedef struct
{
u32 buf[16]; // 16 words
u8 size; // tail
u32 buf[0x8000];
} FIFO;
BOOL empty;
BOOL full;
BOOL error;
} GFX_FIFO;
extern void FIFOclear(FIFO * fifo);
extern void FIFOadd(FIFO * fifo, u32 val);
extern u32 FIFOget(FIFO * fifo);
typedef struct
{
u32 buf[16]; // 16 words
u8 size; // tail
BOOL empty;
BOOL full;
BOOL error;
} DISP_FIFO;
extern void IPC_FIFOclear(IPC_FIFO * fifo);
extern void IPC_FIFOadd(IPC_FIFO * fifo, u32 val);
extern u32 IPC_FIFOget(IPC_FIFO * fifo);
//extern void GFX_FIFOclear(GFX_FIFO * fifo);
//extern void GFX_FIFOadd(GFX_FIFO * fifo, u32 val);
//extern u32 GFX_FIFOget(GFX_FIFO * fifo);
#endif

42
desmume/src/GPU.cpp
View File

@ -214,6 +214,7 @@ void GPU_Reset(GPU *g, u8 l)
delete osd;
osd = new OSDCLASS(-1);
//DISP_FIFOclear(&g->disp_fifo);
}
void GPU_DeInit(GPU * gpu)
@ -317,6 +318,7 @@ void GPU_setVideoProp(GPU * gpu, u32 p)
case 2: // Display framebuffer
// gpu->vramBlock = DISPCNT_VRAMBLOCK(p) ;
gpu->vramBlock = cnt->VRAM_Block;
gpu->VRAMaddr = (u8 *)ARM9Mem.ARM9_LCD + (cnt->VRAM_Block * 0x20000);
return;
case 3: // Display from Main RAM
// nothing to be done here
@ -758,11 +760,9 @@ INLINE void renderline_textBG(const GPU * gpu, u8 num, u8 * dst, u32 Y, u16 XBG,
map = (u8 *)MMU_RenderMapToLCD(gpu->BG_map_ram[num] + (tmp&31) * 64);
if (!map) return;
if(tmp>31)
{
map+= ADDRESS_STEP_512B << bgCnt->ScreenSize ;
}
tile = (u8*) MMU_RenderMapToLCD(gpu->BG_tile_ram[num]);
if(!tile) return; // no tiles
@ -1044,7 +1044,9 @@ INLINE void apply_rot_fun(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16
INLINE void rotBG2(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA, s16 PB, s16 PC, s16 PD, u16 LG)
{
u8 * map = (u8 *)MMU_RenderMapToLCD(gpu->BG_map_ram[num]);
if (!map) return;
u8 * tile = (u8 *)MMU_RenderMapToLCD(gpu->BG_tile_ram[num]);
if (!tile) return;
u8 * pal = ARM9Mem.ARM9_VMEM + gpu->core * 0x400;
// printf("rot mode\n");
apply_rot_fun(gpu, num, dst, H,X,Y,PA,PB,PC,PD,LG, rot_tiled_8bit_entry, map, tile, pal);
@ -1065,7 +1067,9 @@ INLINE void extRotBG2(GPU * gpu, u8 num, u8 * dst, u16 H, s32 X, s32 Y, s16 PA,
case 0 :
case 1 :
map = (u8 *)MMU_RenderMapToLCD(gpu->BG_map_ram[num]);
if (!map) return;
tile = (u8 *)MMU_RenderMapToLCD(gpu->BG_tile_ram[num]);
if (!tile) return;
pal = ARM9Mem.ExtPal[gpu->core][gpu->BGExtPalSlot[num]];
if (!pal) return;
@ -2343,11 +2347,10 @@ static INLINE void GPU_ligne_Brightness(NDS_Screen * screen, u16 l)
#endif
}
extern void* memcpy_fast(void* dest, const void* src, size_t count);
void GPU_ligne(NDS_Screen * screen, u16 l)
{
GPU * gpu = screen->gpu;
u8 * dst = GPU_screen + (screen->offset + l) * 512;
// initialize the scanline black
// not doing this causes invalid colors when all active BGs are prevented to draw at some place
// ZERO TODO - shouldnt this be BG palette color 0?
@ -2357,8 +2360,12 @@ void GPU_ligne(NDS_Screen * screen, u16 l)
switch (gpu->dispMode)
{
case 0: // Display Off(Display white)
{
u8 * dst = GPU_screen + (screen->offset + l) * 512;
for (int i=0; i<256; i++)
T2WriteWord(dst, i << 1, 0x7FFF);
}
break;
case 1: // Display BG and OBJ layers
@ -2366,25 +2373,28 @@ void GPU_ligne(NDS_Screen * screen, u16 l)
break;
case 2: // Display framebuffer
{
struct _DISPCNT * dispCnt = &(gpu->dispx_st)->dispx_DISPCNT.bits;
u8 * vram = ARM9Mem.ARM9_LCD + (dispCnt->VRAM_Block * 0x20000) + (l*512);
memcpy(dst, vram, 512);
}
{
u8 * dst = GPU_screen + (screen->offset + l) * 512;
u8 * src = gpu->VRAMaddr + (l*512);
memcpy(dst, gpu->VRAMaddr + (l*512), 512);
}
break;
case 3:
// Read from FIFO MAIN_MEMORY_DISP_FIFO, two pixels at once format is x555, bit15 unused
// Reference: http://nocash.emubase.de/gbatek.htm#dsvideocaptureandmainmemorydisplaymode
// (under DISP_MMEM_FIFO)
#if 1
for (int i=0; i<256;)
#if 0
{
u32 c = FIFOget(&MMU.fifos[gpu->core]); // TODO: this is incorrect
T2WriteWord(dst, i << 1, c&0xFFFF); i++;
T2WriteWord(dst, i << 1, c>>16); i++;
u8 * dst = GPU_screen + (screen->offset + l) * 512;
for (int i=0; i<256;)
{
u32 c = FIFOget(&gpu->fifo);
T2WriteWord(dst, i << 1, c&0xFFFF); i++;
T2WriteWord(dst, i << 1, c>>16); i++;
}
}
#else
INFO("FIFO MAIN_MEMORY_DISP_FIFO\n");
LOG("FIFO MAIN_MEMORY_DISP_FIFO\n");
#endif
break;
}

3
desmume/src/GPU.h
View File

@ -615,6 +615,9 @@ struct _GPU
u8 dispMode;
u8 vramBlock;
u8 *VRAMaddr;
//FIFO fifo;
BOOL dispBG[4];
BOOL dispOBJ;

4863
desmume/src/MMU.cpp
View File

File diff suppressed because it is too large Load Diff

8
desmume/src/MMU.h
View File

@ -2,7 +2,7 @@
yopyop156@ifrance.com
yopyop156.ifrance.com
Copyright (C) 2007 shash
Copyright (C) 2007-2008 DeSmuME team
This file is part of DeSmuME
@ -76,10 +76,10 @@ struct MMU_struct {
u8 ARM9_RW_MODE;
FIFO fifos[2]; // 0 - ARM9 FIFO
// 1 - ARM7 FIFO
IPC_FIFO ipc_fifo[2]; // 0 - ARM9 FIFO
// 1 - ARM7 FIFO*/
static TWaitState MMU_WAIT16[2][16];
static TWaitState MMU_WAIT16[2][16];
static TWaitState MMU_WAIT32[2][16];
u32 DTCMRegion;

28
desmume/src/saves.cpp
View File

@ -209,24 +209,16 @@ SFORMAT SF_MMU[]={
{ "MCHD", 4, 1, &MMU.CheckDMAs},
//fifos
{ "F0ER", 4, 1, &MMU.fifos[0].error},
{ "F0EN", 4, 1, &MMU.fifos[0].enable},
{ "F0EM", 4, 1, &MMU.fifos[0].empty},
{ "F0HA", 4, 1, &MMU.fifos[0].half},
{ "F0FU", 4, 1, &MMU.fifos[0].full},
{ "F0IR", 1, 1, &MMU.fifos[0].irq},
{ "F0SP", 1, 1, &MMU.fifos[0].sendPos},
{ "F0RP", 1, 1, &MMU.fifos[0].recvPos},
{ "F0BU", 1, 0x8000, &MMU.fifos[0].buf},
{ "F1ER", 4, 1, &MMU.fifos[1].error},
{ "F1EN", 4, 1, &MMU.fifos[1].enable},
{ "F1EM", 4, 1, &MMU.fifos[1].empty},
{ "F1HA", 4, 1, &MMU.fifos[1].half},
{ "F1FU", 4, 1, &MMU.fifos[1].full},
{ "F1IR", 1, 1, &MMU.fifos[1].irq},
{ "F1SP", 1, 1, &MMU.fifos[1].sendPos},
{ "F1RP", 1, 1, &MMU.fifos[1].recvPos},
{ "F1BU", 1, 0x8000, &MMU.fifos[1].buf},
{ "F0ER", 4, 1, &MMU.ipc_fifo[0].error},
{ "F0EM", 4, 1, &MMU.ipc_fifo[0].empty},
{ "F0FU", 4, 1, &MMU.ipc_fifo[0].full},
{ "F0SZ", 1, 1, &MMU.ipc_fifo[0].size},
{ "F0BU", 4, 16, &MMU.ipc_fifo[0].buf},
{ "F1ER", 4, 1, &MMU.ipc_fifo[1].error},
{ "F1EM", 4, 1, &MMU.ipc_fifo[1].empty},
{ "F1FU", 4, 1, &MMU.ipc_fifo[1].full},
{ "F1SZ", 1, 1, &MMU.ipc_fifo[1].size},
{ "F1BU", 4, 16, &MMU.ipc_fifo[1].buf},
{ 0 }
};