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core-switch some hardcoded PROCNUM checks in opcode handlers to checks against the arm architecture version, which is what they really were

This commit is contained in:
zeromus 2012-03-29 23:03:06 +00:00
parent 1adec8da24
commit 30f6881980
4 changed files with 16 additions and 17 deletions
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25
desmume/src/arm_instructions.cpp
View File

@ -3653,7 +3653,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAW_T(const u32 i)
\
if(REG_POS(i,12)==15) \
{ \
if (PROCNUM == 0) \
if (cpu->LDTBit) \
{ \
cpu->CPSR.bits.T = BIT0(cpu->R[15]); \
cpu->R[15] &= 0xFFFFFFFE; \
@ -3675,7 +3675,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAW_T(const u32 i)
\
if(REG_POS(i,12)==15) \
{ \
if (PROCNUM == 0) \
if (cpu->LDTBit) \
{ \
cpu->CPSR.bits.T = BIT0(cpu->R[15]); \
cpu->R[15] &= 0xFFFFFFFE; \
@ -3698,7 +3698,7 @@ TEMPLATE static u32 FASTCALL OP_SMLAW_T(const u32 i)
\
if(REG_POS(i,12)==15) \
{ \
if (PROCNUM == 0) \
if (cpu->LDTBit) \
{ \
cpu->CPSR.bits.T = BIT0(cpu->R[15]); \
cpu->R[15] &= 0xFFFFFFFE; \
@ -4860,7 +4860,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA(const u32 i)
// T Bit = value[0]
//else
// pc = value AND 0xFFFFFFFC
if (PROCNUM == 0)
if (cpu->LDTBit)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@ -4904,7 +4904,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIB(const u32 i)
start += 4;
c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
u32 tmp = READ32(cpu->mem_if->data, start);
if (PROCNUM == 0)
if (cpu->LDTBit)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@ -4928,7 +4928,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDA(const u32 i)
if(BIT15(i))
{
u32 tmp = READ32(cpu->mem_if->data, start);
if (PROCNUM == 0)
if (cpu->LDTBit)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@ -4970,7 +4970,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDB(const u32 i)
{
start -= 4;
u32 tmp = READ32(cpu->mem_if->data, start);
if (PROCNUM == 0)
if (cpu->LDTBit)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@ -5027,7 +5027,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_W(const u32 i)
if(BIT15(i))
{
u32 tmp = READ32(cpu->mem_if->data, start);
if (PROCNUM == 0)
if (cpu->LDTBit)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@ -5079,7 +5079,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIB_W(const u32 i)
start += 4;
c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(start);
tmp = READ32(cpu->mem_if->data, start);
if (PROCNUM == 0)
if (cpu->LDTBit)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@ -5113,7 +5113,7 @@ TEMPLATE static u32 FASTCALL OP_LDMDA_W(const u32 i)
if(BIT15(i))
{
u32 tmp = READ32(cpu->mem_if->data, start);
if (PROCNUM == 0)
if (cpu->LDTBit)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
@ -5163,11 +5163,10 @@ TEMPLATE static u32 FASTCALL OP_LDMDB_W(const u32 i)
u32 tmp;
start -= 4;
tmp = READ32(cpu->mem_if->data, start);
if (PROCNUM == 0)
if (cpu->LDTBit)
{
cpu->CPSR.bits.T = BIT0(tmp);
registres[15] = tmp & 0xFFFFFFFE;
}
registres[15] = tmp & 0xFFFFFFFE; }
else
registres[15] = tmp & 0xFFFFFFFC;
cpu->next_instruction = registres[15];

2
desmume/src/armcpu.cpp
View File

@ -215,7 +215,7 @@ void armcpu_t::changeCPSR()
void armcpu_init(armcpu_t *armcpu, u32 adr)
{
armcpu->LDTBit = (armcpu->proc_ID==0); //Si ARM9 utiliser le syte v5 pour le load
armcpu->LDTBit = (armcpu->proc_ID==0); //arm9 is ARMv5 style. this should be renamed, or more likely, all references to this should poll a function to return an architecture level enum
armcpu->intVector = 0xFFFF0000 * (armcpu->proc_ID==0);
armcpu->waitIRQ = FALSE;
armcpu->halt_IE_and_IF = FALSE;

2
desmume/src/armcpu.h
View File

@ -203,7 +203,7 @@ struct armcpu_t
armcp_t *coproc[16];
u32 intVector;
u8 LDTBit; //1 : ARMv5 style 0 : non ARMv5
u8 LDTBit; //1 : ARMv5 style 0 : non ARMv5 (earlier)
BOOL waitIRQ;
BOOL halt_IE_and_IF; //the cpu is halted, waiting for IE&IF to signal something
u8 intrWaitARM_state;

4
desmume/src/thumb_instructions.cpp
View File

@ -637,7 +637,7 @@ TEMPLATE static u32 FASTCALL OP_MUL_REG(const u32 i)
//In earlier versions of the architecture, the value of the C flag was UNPREDICTABLE
//after a MUL instruction.
if (PROCNUM == 1) // ARM4T 1S + mI, m = 3
if (!cpu->LDTBit) // ARM4T 1S + mI, m = 3
return 4;
MUL_Mxx_END_THUMB(1);
@ -909,7 +909,7 @@ TEMPLATE static u32 FASTCALL OP_POP_PC(const u32 i)
v = READ32(cpu->mem_if->data, adr);
c += MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(adr);
if(PROCNUM==0)
if(cpu->LDTBit)
cpu->CPSR.bits.T = BIT0(v);
cpu->R[15] = v & 0xFFFFFFFE;