some minor optimization and cleanup
This commit is contained in:
nitsuja
parent
388c5253e3
commit
1d9c7c6bc4
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@ -3760,18 +3760,14 @@ static char * OP_BL_THUMB(u32 adr, u32 i, char * txt)
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return txt;
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}
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#define TYPE_RETOUR char *
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#define PARAMETRES u32 adr, u32 i, char * txt
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#define CALLTYPE
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#define NOM_TAB des_arm_instructions_set
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#define NOM_THUMB_TAB des_thumb_instructions_set
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#define TABDECL(x) x
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TYPE_RETOUR (*CALLTYPE NOM_TAB[4096])(PARAMETRES)={
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const DisasmOpFunc des_arm_instructions_set[4096] = {
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#include "instruction_tabdef.inc"
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};
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TYPE_RETOUR (*CALLTYPE NOM_THUMB_TAB[1024])(PARAMETRES)={
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const DisasmOpFunc des_thumb_instructions_set[1024] = {
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#include "thumb_tabdef.inc"
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};
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@ -24,8 +24,10 @@
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#include "types.h"
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extern char * (* des_arm_instructions_set[4096])(u32 adr, u32 i, char * txt);
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extern char * (* des_thumb_instructions_set[1024])(u32 adr, u32 i, char * txt);
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typedef char* (* DisasmOpFunc)(u32 adr, u32 i, char * txt);
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extern const DisasmOpFunc des_arm_instructions_set[4096];
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extern const DisasmOpFunc des_thumb_instructions_set[1024];
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#endif
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@ -1100,6 +1100,30 @@ FORCEINLINE void rot_scale_op(GPU * gpu, s32 X, s32 Y, s16 PA, s16 PB, s16 PC, s
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const s32 dx = (s32)PA;
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const s32 dy = (s32)PC;
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// as an optimization, specially handle the fairly common case of
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// "unrotated + unscaled + no boundary checking required"
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if(dx==0x100 && dy==0)
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{
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s32 auxX = x.bits.Integer;
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if(WRAP || auxX + LG < wh)
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{
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s32 auxY = y.bits.Integer;
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if(WRAP)
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{
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auxY = auxY & (ht-1);
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auxX = auxX & (wh-1);
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}
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for(int i = 0; i < LG; ++i)
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{
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fun(gpu, auxX, auxY, wh, map, tile, pal, i);
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auxX++;
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if(WRAP)
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auxX = auxX & (wh-1);
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}
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return;
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}
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}
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for(int i = 0; i < LG; ++i)
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{
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s32 auxX, auxY;
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@ -85,6 +85,8 @@ static u64 isqrt (u64 x) {
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u32 partie = 1;
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u32 _MMU_MAIN_MEM_MASK = 0x3FFFFF;
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u32 _MMU_MAIN_MEM_MASK16 = 0x3FFFFF & ~1;
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u32 _MMU_MAIN_MEM_MASK32 = 0x3FFFFF & ~3;
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#define ROM_MASK 3
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@ -1980,7 +1982,7 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped);
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if(unmapped) return;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
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MMU.MMU_MEM[ARMCPU_ARM9][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20]]=val;
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}
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@ -2460,7 +2462,7 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped);
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if(unmapped) return;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val);
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}
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@ -2859,7 +2861,7 @@ void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr, unmapped);
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if(unmapped) return;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM9][adr>>20], val);
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}
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@ -2887,12 +2889,12 @@ u16 FASTCALL _MMU_ARM9_read16(u32 adr)
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mmu_log_debug_ARM9(adr, "(read16) %0x%X", T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]));
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if(adr<0x02000000)
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return T1ReadWord(MMU.ARM9_ITCM, adr & 0x7FFF);
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return T1ReadWord_guaranteedAligned(MMU.ARM9_ITCM, adr & 0x7FFE);
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if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
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return addon.read16(adr);
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adr &= 0x0FFFFFFF;
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adr &= 0x0FFFFFFE;
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if (adr >> 24 == 4)
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{
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@ -2941,14 +2943,15 @@ u16 FASTCALL _MMU_ARM9_read16(u32 adr)
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return 1;
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}
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return T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]);
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return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]);
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}
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bool unmapped;
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr,unmapped);
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if(unmapped) return 0;
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return T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20) & 0xFF]);
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF
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return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM9][adr >> 20]);
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}
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//================================================= MMU ARM9 read 32
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@ -2957,12 +2960,12 @@ u32 FASTCALL _MMU_ARM9_read32(u32 adr)
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mmu_log_debug_ARM9(adr, "(read32) %0x%X", T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)]));
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if(adr<0x02000000)
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return T1ReadLong(MMU.ARM9_ITCM, adr&0x7FFF);
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return T1ReadLong_guaranteedAligned(MMU.ARM9_ITCM, adr&0x7FFC);
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if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
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return addon.read32(adr);
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adr &= 0x0FFFFFFF;
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adr &= 0x0FFFFFFC;
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// Address is an IO register
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if((adr >> 24) == 4)
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@ -3048,15 +3051,15 @@ u32 FASTCALL _MMU_ARM9_read32(u32 adr)
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case REG_GCDATAIN:
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return MMU_readFromGC<ARMCPU_ARM9>();
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}
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return T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)]);
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return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)]);
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}
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bool unmapped;
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adr = MMU_LCDmap<ARMCPU_ARM9>(adr,unmapped);
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if(unmapped) return 0;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [zeromus, inspired by shash]
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return T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)]);
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [zeromus, inspired by shash]
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return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)]);
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}
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//================================================================================================== ARM7 *
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//=========================================================================================================
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@ -3122,7 +3125,7 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
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adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped);
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if(unmapped) return;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
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MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]]=val;
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}
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@ -3438,7 +3441,7 @@ void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
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adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped);
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if(unmapped) return;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
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}
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//================================================= MMU ARM7 write 32
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@ -3573,7 +3576,7 @@ void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
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adr = MMU_LCDmap<ARMCPU_ARM7>(adr,unmapped);
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if(unmapped) return;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
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}
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@ -3618,7 +3621,7 @@ u16 FASTCALL _MMU_ARM7_read16(u32 adr)
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if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
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return addon.read16(adr);
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adr &= 0x0FFFFFFF;
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adr &= 0x0FFFFFFE;
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if(adr>>24==4)
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{
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@ -3660,7 +3663,7 @@ u16 FASTCALL _MMU_ARM7_read16(u32 adr)
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case REG_POSTFLG :
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return 1;
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}
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return T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20) & 0xFF]);
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return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]);
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}
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bool unmapped;
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@ -3668,7 +3671,8 @@ u16 FASTCALL _MMU_ARM7_read16(u32 adr)
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if(unmapped) return 0;
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/* Returns data from memory */
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return T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20) & 0xFF]);
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF
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return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]);
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}
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//================================================= MMU ARM7 read 32
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u32 FASTCALL _MMU_ARM7_read32(u32 adr)
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@ -3684,7 +3688,7 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr)
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if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
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return addon.read32(adr);
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adr &= 0x0FFFFFFF;
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adr &= 0x0FFFFFFC;
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if((adr >> 24) == 4)
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{
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@ -3718,7 +3722,7 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr)
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case REG_GCDATAIN:
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return MMU_readFromGC<ARMCPU_ARM7>();
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}
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return T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20)]);
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return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20)]);
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}
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bool unmapped;
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@ -3726,8 +3730,8 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr)
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if(unmapped) return 0;
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//Returns data from memory
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [zeromus, inspired by shash]
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return T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20)]);
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [zeromus, inspired by shash]
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return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][(adr >> 20)], adr & MMU.MMU_MASK[ARMCPU_ARM7][(adr >> 20)]);
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}
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//=========================================================================================================
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@ -307,12 +307,12 @@ template<int PROCNUM, MMU_ACCESS_TYPE AT> void _MMU_write08(u32 addr, u8 val);
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template<int PROCNUM, MMU_ACCESS_TYPE AT> void _MMU_write16(u32 addr, u16 val);
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template<int PROCNUM, MMU_ACCESS_TYPE AT> void _MMU_write32(u32 addr, u32 val);
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template<int PROCNUM> u8 _MMU_read08(u32 addr) { return _MMU_read08<PROCNUM, MMU_AT_DATA>(addr); }
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template<int PROCNUM> u16 _MMU_read16(u32 addr) { return _MMU_read16<PROCNUM, MMU_AT_DATA>(addr); }
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template<int PROCNUM> u32 _MMU_read32(u32 addr) { return _MMU_read32<PROCNUM, MMU_AT_DATA>(addr); }
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template<int PROCNUM> void _MMU_write08(u32 addr, u8 val) { _MMU_write08<PROCNUM, MMU_AT_DATA>(addr,val); }
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template<int PROCNUM> void _MMU_write16(u32 addr, u16 val) { _MMU_write16<PROCNUM, MMU_AT_DATA>(addr,val); }
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template<int PROCNUM> void _MMU_write32(u32 addr, u32 val) { _MMU_write32<PROCNUM, MMU_AT_DATA>(addr,val); }
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template<int PROCNUM> FORCEINLINE u8 _MMU_read08(u32 addr) { return _MMU_read08<PROCNUM, MMU_AT_DATA>(addr); }
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template<int PROCNUM> FORCEINLINE u16 _MMU_read16(u32 addr) { return _MMU_read16<PROCNUM, MMU_AT_DATA>(addr); }
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template<int PROCNUM> FORCEINLINE u32 _MMU_read32(u32 addr) { return _MMU_read32<PROCNUM, MMU_AT_DATA>(addr); }
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template<int PROCNUM> FORCEINLINE void _MMU_write08(u32 addr, u8 val) { _MMU_write08<PROCNUM, MMU_AT_DATA>(addr,val); }
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template<int PROCNUM> FORCEINLINE void _MMU_write16(u32 addr, u16 val) { _MMU_write16<PROCNUM, MMU_AT_DATA>(addr,val); }
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template<int PROCNUM> FORCEINLINE void _MMU_write32(u32 addr, u32 val) { _MMU_write32<PROCNUM, MMU_AT_DATA>(addr,val); }
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void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val);
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void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val);
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@ -331,9 +331,13 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr);
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extern u32 partie;
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extern u32 _MMU_MAIN_MEM_MASK;
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extern u32 _MMU_MAIN_MEM_MASK16;
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extern u32 _MMU_MAIN_MEM_MASK32;
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inline void SetupMMU(BOOL debugConsole) {
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if(debugConsole) _MMU_MAIN_MEM_MASK = 0x7FFFFF;
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else _MMU_MAIN_MEM_MASK = 0x3FFFFF;
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_MMU_MAIN_MEM_MASK16 = _MMU_MAIN_MEM_MASK & ~1;
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_MMU_MAIN_MEM_MASK32 = _MMU_MAIN_MEM_MASK & ~3;
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}
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//TODO: at one point some of the early access code included this. consider re-adding it
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@ -392,10 +396,10 @@ FORCEINLINE u16 _MMU_read16(const int PROCNUM, const MMU_ACCESS_TYPE AT, const u
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if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_CODE)
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{
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if ((addr & 0x0F000000) == 0x02000000)
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return T1ReadWord_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK);
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return T1ReadWord_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16);
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if(addr<0x02000000)
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return T1ReadWord_guaranteedAligned(MMU.ARM9_ITCM, addr&0x7FFF);
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return T1ReadWord_guaranteedAligned(MMU.ARM9_ITCM, addr&0x7FFE);
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goto dunno;
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}
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@ -404,11 +408,11 @@ FORCEINLINE u16 _MMU_read16(const int PROCNUM, const MMU_ACCESS_TYPE AT, const u
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if((addr&(~0x3FFF)) == MMU.DTCMRegion)
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{
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//Returns data from DTCM (ARM9 only)
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return T1ReadWord(MMU.ARM9_DTCM, addr & 0x3FFF);
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return T1ReadWord_guaranteedAligned(MMU.ARM9_DTCM, addr & 0x3FFE);
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}
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if ( (addr & 0x0F000000) == 0x02000000)
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return T1ReadWord( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK);
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return T1ReadWord_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16);
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dunno:
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if(PROCNUM==ARMCPU_ARM9) return _MMU_ARM9_read16(addr);
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@ -428,10 +432,10 @@ FORCEINLINE u32 _MMU_read32(const int PROCNUM, const MMU_ACCESS_TYPE AT, const u
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if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_CODE)
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{
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if ( (addr & 0x0F000000) == 0x02000000)
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return T1ReadLong_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK);
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return T1ReadLong_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32);
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if(addr<0x02000000)
|
||||
return T1ReadLong_guaranteedAligned(MMU.ARM9_ITCM, addr&0x7FFF);
|
||||
return T1ReadLong_guaranteedAligned(MMU.ARM9_ITCM, addr&0x7FFC);
|
||||
|
||||
goto dunno;
|
||||
}
|
||||
|
|
@ -440,11 +444,11 @@ FORCEINLINE u32 _MMU_read32(const int PROCNUM, const MMU_ACCESS_TYPE AT, const u
|
|||
if(PROCNUM==ARMCPU_ARM7)
|
||||
{
|
||||
if ( (addr & 0x0F000000) == 0x02000000)
|
||||
return T1ReadLong_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK);
|
||||
return T1ReadLong_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32);
|
||||
else if((addr & 0xFF800000) == 0x03800000)
|
||||
return T1ReadLong_guaranteedAligned(MMU.ARM7_ERAM, addr&0xFFFF);
|
||||
return T1ReadLong_guaranteedAligned(MMU.ARM7_ERAM, addr&0xFFFC);
|
||||
else if((addr & 0xFF800000) == 0x03000000)
|
||||
return T1ReadLong_guaranteedAligned(MMU.SWIRAM, addr&0x7FFF);
|
||||
return T1ReadLong_guaranteedAligned(MMU.SWIRAM, addr&0x7FFC);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -454,11 +458,11 @@ FORCEINLINE u32 _MMU_read32(const int PROCNUM, const MMU_ACCESS_TYPE AT, const u
|
|||
if((addr&(~0x3FFF)) == MMU.DTCMRegion)
|
||||
{
|
||||
//Returns data from DTCM (ARM9 only)
|
||||
return T1ReadLong(MMU.ARM9_DTCM, addr & 0x3FFF);
|
||||
return T1ReadLong_guaranteedAligned(MMU.ARM9_DTCM, addr & 0x3FFC);
|
||||
}
|
||||
|
||||
if ( (addr & 0x0F000000) == 0x02000000)
|
||||
return T1ReadLong( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK);
|
||||
return T1ReadLong_guaranteedAligned( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32);
|
||||
}
|
||||
|
||||
dunno:
|
||||
|
|
@ -503,12 +507,12 @@ FORCEINLINE void _MMU_write16(const int PROCNUM, const MMU_ACCESS_TYPE AT, const
|
|||
if(PROCNUM==ARMCPU_ARM9)
|
||||
if((addr&(~0x3FFF)) == MMU.DTCMRegion)
|
||||
{
|
||||
T1WriteWord(MMU.ARM9_DTCM, addr & 0x3FFF, val);
|
||||
T1WriteWord(MMU.ARM9_DTCM, addr & 0x3FFE, val);
|
||||
return;
|
||||
}
|
||||
|
||||
if ( (addr & 0x0F000000) == 0x02000000) {
|
||||
T1WriteWord( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK, val);
|
||||
T1WriteWord( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK16, val);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -528,12 +532,12 @@ FORCEINLINE void _MMU_write32(const int PROCNUM, const MMU_ACCESS_TYPE AT, const
|
|||
if(PROCNUM==ARMCPU_ARM9)
|
||||
if((addr&(~0x3FFF)) == MMU.DTCMRegion)
|
||||
{
|
||||
T1WriteLong(MMU.ARM9_DTCM, addr & 0x3FFF, val);
|
||||
T1WriteLong(MMU.ARM9_DTCM, addr & 0x3FFC, val);
|
||||
return;
|
||||
}
|
||||
|
||||
if ( (addr & 0x0F000000) == 0x02000000) {
|
||||
T1WriteLong( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK, val);
|
||||
T1WriteLong( MMU.MAIN_MEM, addr & _MMU_MAIN_MEM_MASK32, val);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -21,11 +21,13 @@
|
|||
#ifndef ARMINSTRUCTION_H
|
||||
#define ARMINSTRUCTION_H
|
||||
|
||||
#include "types.h"
|
||||
#include "armcpu.h"
|
||||
|
||||
extern u32 (FASTCALL* arm_instructions_set_0[4096])();
|
||||
extern u32 (FASTCALL* arm_instructions_set_1[4096])();
|
||||
typedef u32 (FASTCALL* ArmOpFunc)(const u32 i);
|
||||
|
||||
extern const ArmOpFunc arm_instructions_set_0[4096];
|
||||
extern const ArmOpFunc arm_instructions_set_1[4096];
|
||||
|
||||
extern const char* arm_instruction_names[4096];
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -413,6 +413,17 @@ FORCEINLINE static u32 armcpu_prefetch()
|
|||
armcpu->R[15] = curInstruction + 4;
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
if(PROCNUM==0)
|
||||
{
|
||||
// arm9 fetches 2 instructions at a time in thumb mode
|
||||
if(!(curInstruction == armcpu->instruct_adr + 2 && (curInstruction & 2)))
|
||||
return MMU.MMU_WAIT32[PROCNUM][(curInstruction>>24)&0xF];
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
return MMU.MMU_WAIT16[PROCNUM][(curInstruction>>24)&0xF];
|
||||
}
|
||||
|
||||
|
|
@ -535,13 +546,13 @@ u32 armcpu_exec()
|
|||
#ifdef DEVELOPER
|
||||
DEBUG_statistics.instructionHits[0].arm[INSTRUCTION_INDEX(ARMPROC.instruction)]++;
|
||||
#endif
|
||||
cExecute = arm_instructions_set_0[INSTRUCTION_INDEX(ARMPROC.instruction)]();
|
||||
cExecute = arm_instructions_set_0[INSTRUCTION_INDEX(ARMPROC.instruction)](ARMPROC.instruction);
|
||||
}
|
||||
else {
|
||||
#ifdef DEVELOPER
|
||||
DEBUG_statistics.instructionHits[1].arm[INSTRUCTION_INDEX(ARMPROC.instruction)]++;
|
||||
#endif
|
||||
cExecute = arm_instructions_set_1[INSTRUCTION_INDEX(ARMPROC.instruction)]();
|
||||
cExecute = arm_instructions_set_1[INSTRUCTION_INDEX(ARMPROC.instruction)](ARMPROC.instruction);
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
@ -562,13 +573,13 @@ u32 armcpu_exec()
|
|||
#ifdef DEVELOPER
|
||||
DEBUG_statistics.instructionHits[0].thumb[ARMPROC.instruction>>6]++;
|
||||
#endif
|
||||
cExecute = thumb_instructions_set_0[ARMPROC.instruction>>6]();
|
||||
cExecute = thumb_instructions_set_0[ARMPROC.instruction>>6](ARMPROC.instruction);
|
||||
}
|
||||
else {
|
||||
#ifdef DEVELOPER
|
||||
DEBUG_statistics.instructionHits[1].thumb[ARMPROC.instruction>>6]++;
|
||||
#endif
|
||||
cExecute = thumb_instructions_set_1[ARMPROC.instruction>>6]();
|
||||
cExecute = thumb_instructions_set_1[ARMPROC.instruction>>6](ARMPROC.instruction);
|
||||
}
|
||||
|
||||
#ifdef GDB_STUB
|
||||
|
|
|
|||
|
|
@ -35,20 +35,16 @@
|
|||
inline u32 ROR(u32 i, u32 j) { return ((((u32)(i))>>(j)) | (((u32)(i))<<(32-(j)))); }
|
||||
|
||||
template<typename T>
|
||||
inline T UNSIGNED_OVERFLOW(T a,T b,T c) { return ((BIT31(a)&BIT31(b)) |
|
||||
((BIT31(a)|BIT31(b))&BIT31(~c))); }
|
||||
inline T UNSIGNED_OVERFLOW(T a,T b,T c) { return BIT31(((a)&(b)) | (((a)|(b))&(~c))); }
|
||||
|
||||
template<typename T>
|
||||
inline T UNSIGNED_UNDERFLOW(T a,T b,T c) { return ((BIT31(~a)&BIT31(b)) |
|
||||
((BIT31(~a)|BIT31(b))&BIT31(c))); }
|
||||
inline T UNSIGNED_UNDERFLOW(T a,T b,T c) { return BIT31(((~a)&(b)) | (((~a)|(b))&(c))); }
|
||||
|
||||
template<typename T>
|
||||
inline T SIGNED_OVERFLOW(T a,T b,T c) { return ((BIT31(a)&BIT31(b)&BIT31(~c))|
|
||||
(BIT31(~a)&BIT31(~(b))&BIT31(c))); }
|
||||
inline T SIGNED_OVERFLOW(T a,T b,T c) { return BIT31(((a)&(b)&(~c)) | ((~a)&(~(b))&(c))); }
|
||||
|
||||
template<typename T>
|
||||
inline T SIGNED_UNDERFLOW(T a,T b,T c) { return ((BIT31(a)&BIT31(~(b))&BIT31(~c))|
|
||||
(BIT31(~a)&BIT31(b)&BIT31(c))); }
|
||||
inline T SIGNED_UNDERFLOW(T a,T b,T c) { return BIT31(((a)&(~(b))&(~c)) | ((~a)&(b)&(c))); }
|
||||
|
||||
//zero 15-feb-2009 - these werent getting used and they were getting in my way
|
||||
//#define EQ 0x0
|
||||
|
|
@ -69,7 +65,7 @@ inline T SIGNED_UNDERFLOW(T a,T b,T c) { return ((BIT31(a)&BIT31(~(b))&BIT31(~c)
|
|||
|
||||
extern const unsigned char arm_cond_table[16*16];
|
||||
|
||||
#define TEST_COND(cond, inst, CPSR) ((arm_cond_table[((CPSR.val >> 24) & 0xf0)+(cond)] >> (inst)) & 1)
|
||||
#define TEST_COND(cond, inst, CPSR) ((arm_cond_table[((CPSR.val >> 24) & 0xf0)|(cond)]) & (1 << (inst)))
|
||||
|
||||
|
||||
enum Mode
|
||||
|
|
|
|||
|
|
@ -251,9 +251,10 @@ TEMPLATE u32 intrWaitARM()
|
|||
//cpu->switchMode(oldmode[cpu->proc_ID]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
cpu->R[15] = cpu->instruct_adr;
|
||||
cpu->next_instruction = cpu->R[15];
|
||||
|
||||
u32 instructAddr = cpu->instruct_adr;
|
||||
cpu->R[15] = instructAddr;
|
||||
cpu->next_instruction = instructAddr;
|
||||
cpu->waitIRQ = 1;
|
||||
//oldmode[cpu->proc_ID] = cpu->switchMode(SVC);
|
||||
|
||||
|
|
@ -270,6 +271,7 @@ TEMPLATE static u32 waitVBlankARM()
|
|||
TEMPLATE static u32 wait4IRQ()
|
||||
{
|
||||
//execute= FALSE;
|
||||
u32 instructAddr = cpu->instruct_adr;
|
||||
if(cpu->wirq)
|
||||
{
|
||||
if(!cpu->waitIRQ)
|
||||
|
|
@ -279,14 +281,14 @@ TEMPLATE static u32 wait4IRQ()
|
|||
//cpu->switchMode(oldmode[cpu->proc_ID]);
|
||||
return 1;
|
||||
}
|
||||
cpu->R[15] = cpu->instruct_adr;
|
||||
cpu->next_instruction = cpu->R[15];
|
||||
cpu->R[15] = instructAddr;
|
||||
cpu->next_instruction = instructAddr;
|
||||
return 1;
|
||||
}
|
||||
cpu->waitIRQ = 1;
|
||||
cpu->wirq = 1;
|
||||
cpu->R[15] = cpu->instruct_adr;
|
||||
cpu->next_instruction = cpu->R[15];
|
||||
cpu->R[15] = instructAddr;
|
||||
cpu->next_instruction = instructAddr;
|
||||
//oldmode[cpu->proc_ID] = cpu->switchMode(SVC);
|
||||
return 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
#include "debug.h"
|
||||
#include "MMU.h"
|
||||
#include "NDSSystem.h"
|
||||
#include "thumb_instructions.h"
|
||||
#include <assert.h>
|
||||
|
||||
#define cpu (&ARMPROC)
|
||||
|
|
@ -37,15 +38,14 @@
|
|||
|
||||
extern volatile bool execute;
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_UND_THUMB()
|
||||
TEMPLATE static u32 FASTCALL OP_UND_THUMB(const u32 i)
|
||||
{
|
||||
emu_halt();
|
||||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSL_0()
|
||||
TEMPLATE static u32 FASTCALL OP_LSL_0(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)];
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
|
||||
|
|
@ -53,9 +53,8 @@ TEMPLATE static u32 FASTCALL OP_LSL_0()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSL()
|
||||
TEMPLATE static u32 FASTCALL OP_LSL(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 v = (i>>6) & 0x1F;
|
||||
cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], 32-v);
|
||||
cpu->R[REG_NUM(i, 0)] = (cpu->R[REG_NUM(i, 3)] << v);
|
||||
|
|
@ -65,9 +64,8 @@ TEMPLATE static u32 FASTCALL OP_LSL()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSR_0()
|
||||
TEMPLATE static u32 FASTCALL OP_LSR_0(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
// cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]);
|
||||
cpu->R[REG_NUM(i, 0)] = 0;
|
||||
|
|
@ -77,9 +75,8 @@ TEMPLATE static u32 FASTCALL OP_LSR_0()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSR()
|
||||
TEMPLATE static u32 FASTCALL OP_LSR(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 v = (i>>6) & 0x1F;
|
||||
cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], v-1);
|
||||
cpu->R[REG_NUM(i, 0)] = (cpu->R[REG_NUM(i, 3)] >> v);
|
||||
|
|
@ -89,9 +86,8 @@ TEMPLATE static u32 FASTCALL OP_LSR()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ASR_0()
|
||||
TEMPLATE static u32 FASTCALL OP_ASR_0(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]);
|
||||
cpu->R[REG_NUM(i, 0)] = BIT31(cpu->R[REG_NUM(i, 3)])*0xFFFFFFFF;
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
|
|
@ -100,9 +96,8 @@ TEMPLATE static u32 FASTCALL OP_ASR_0()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ASR()
|
||||
TEMPLATE static u32 FASTCALL OP_ASR(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 v = (i>>6) & 0x1F;
|
||||
cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], v-1);
|
||||
cpu->R[REG_NUM(i, 0)] = (((s32)cpu->R[REG_NUM(i, 3)]) >> v);
|
||||
|
|
@ -112,9 +107,8 @@ TEMPLATE static u32 FASTCALL OP_ASR()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_REG()
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_REG(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 a = cpu->R[REG_NUM(i, 3)];
|
||||
u32 b = cpu->R[REG_NUM(i, 6)];
|
||||
cpu->R[REG_NUM(i, 0)] = a + b;
|
||||
|
|
@ -126,9 +120,8 @@ TEMPLATE static u32 FASTCALL OP_ADD_REG()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_SUB_REG()
|
||||
TEMPLATE static u32 FASTCALL OP_SUB_REG(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 a = cpu->R[REG_NUM(i, 3)];
|
||||
u32 b = cpu->R[REG_NUM(i, 6)];
|
||||
cpu->R[REG_NUM(i, 0)] = a - b;
|
||||
|
|
@ -140,9 +133,8 @@ TEMPLATE static u32 FASTCALL OP_SUB_REG()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_IMM3()
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_IMM3(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 a = cpu->R[REG_NUM(i, 3)];
|
||||
cpu->R[REG_NUM(i, 0)] = a + REG_NUM(i, 6);
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
|
|
@ -153,9 +145,8 @@ TEMPLATE static u32 FASTCALL OP_ADD_IMM3()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_SUB_IMM3()
|
||||
TEMPLATE static u32 FASTCALL OP_SUB_IMM3(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 a = cpu->R[REG_NUM(i, 3)];
|
||||
cpu->R[REG_NUM(i, 0)] = a - REG_NUM(i, 6);
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
|
|
@ -166,9 +157,8 @@ TEMPLATE static u32 FASTCALL OP_SUB_IMM3()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_MOV_IMM8()
|
||||
TEMPLATE static u32 FASTCALL OP_MOV_IMM8(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[REG_NUM(i, 8)] = i & 0xFF;
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 8)]);
|
||||
cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 8)] == 0;
|
||||
|
|
@ -176,21 +166,20 @@ TEMPLATE static u32 FASTCALL OP_MOV_IMM8()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_CMP_IMM8()
|
||||
TEMPLATE static u32 FASTCALL OP_CMP_IMM8(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF);
|
||||
cpu->CPSR.bits.N = BIT31(tmp);
|
||||
cpu->CPSR.bits.Z = tmp == 0;
|
||||
cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(cpu->R[REG_NUM(i, 8)], (i & 0xFF), tmp);
|
||||
cpu->CPSR.bits.V = SIGNED_UNDERFLOW(cpu->R[REG_NUM(i, 8)], (i & 0xFF), tmp);
|
||||
|
||||
Status_Reg CPSR = cpu->CPSR;
|
||||
CPSR.bits.N = BIT31(tmp);
|
||||
CPSR.bits.Z = tmp == 0;
|
||||
CPSR.bits.C = !UNSIGNED_UNDERFLOW(cpu->R[REG_NUM(i, 8)], (i & 0xFF), tmp);
|
||||
CPSR.bits.V = SIGNED_UNDERFLOW(cpu->R[REG_NUM(i, 8)], (i & 0xFF), tmp);
|
||||
cpu->CPSR = CPSR;
|
||||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_IMM8()
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_IMM8(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 tmp = cpu->R[REG_NUM(i, 8)] + (i & 0xFF);
|
||||
cpu->CPSR.bits.N = BIT31(tmp);
|
||||
cpu->CPSR.bits.Z = tmp == 0;
|
||||
|
|
@ -201,9 +190,8 @@ TEMPLATE static u32 FASTCALL OP_ADD_IMM8()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_SUB_IMM8()
|
||||
TEMPLATE static u32 FASTCALL OP_SUB_IMM8(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF);
|
||||
cpu->CPSR.bits.N = BIT31(tmp);
|
||||
cpu->CPSR.bits.Z = tmp == 0;
|
||||
|
|
@ -214,9 +202,8 @@ TEMPLATE static u32 FASTCALL OP_SUB_IMM8()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_AND()
|
||||
TEMPLATE static u32 FASTCALL OP_AND(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[REG_NUM(i, 0)] &= cpu->R[REG_NUM(i, 3)];
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
|
||||
|
|
@ -224,9 +211,8 @@ TEMPLATE static u32 FASTCALL OP_AND()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_EOR()
|
||||
TEMPLATE static u32 FASTCALL OP_EOR(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[REG_NUM(i, 0)] ^= cpu->R[REG_NUM(i, 3)];
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
|
||||
|
|
@ -234,9 +220,8 @@ TEMPLATE static u32 FASTCALL OP_EOR()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSL_REG()
|
||||
TEMPLATE static u32 FASTCALL OP_LSL_REG(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
|
||||
|
||||
if(!v)
|
||||
|
|
@ -264,9 +249,8 @@ TEMPLATE static u32 FASTCALL OP_LSL_REG()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSR_REG()
|
||||
TEMPLATE static u32 FASTCALL OP_LSR_REG(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
|
||||
|
||||
if(!v)
|
||||
|
|
@ -294,9 +278,8 @@ TEMPLATE static u32 FASTCALL OP_LSR_REG()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ASR_REG()
|
||||
TEMPLATE static u32 FASTCALL OP_ASR_REG(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
|
||||
|
||||
if(!v)
|
||||
|
|
@ -322,9 +305,8 @@ TEMPLATE static u32 FASTCALL OP_ASR_REG()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADC_REG()
|
||||
TEMPLATE static u32 FASTCALL OP_ADC_REG(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 a = cpu->R[REG_NUM(i, 0)];
|
||||
u32 b = cpu->R[REG_NUM(i, 3)];
|
||||
u32 tmp = b + cpu->CPSR.bits.C;
|
||||
|
|
@ -351,9 +333,8 @@ TEMPLATE static u32 FASTCALL OP_ADC_REG()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_SBC_REG()
|
||||
TEMPLATE static u32 FASTCALL OP_SBC_REG(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 a = cpu->R[REG_NUM(i, 0)];
|
||||
u32 b = cpu->R[REG_NUM(i, 3)];
|
||||
u32 tmp = a - (!cpu->CPSR.bits.C);
|
||||
|
|
@ -381,9 +362,8 @@ TEMPLATE static u32 FASTCALL OP_SBC_REG()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ROR_REG()
|
||||
TEMPLATE static u32 FASTCALL OP_ROR_REG(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
|
||||
|
||||
if(v == 0)
|
||||
|
|
@ -408,9 +388,8 @@ TEMPLATE static u32 FASTCALL OP_ROR_REG()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_TST()
|
||||
TEMPLATE static u32 FASTCALL OP_TST(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 tmp = cpu->R[REG_NUM(i, 0)] & cpu->R[REG_NUM(i, 3)];
|
||||
cpu->CPSR.bits.N = BIT31(tmp);
|
||||
cpu->CPSR.bits.Z = tmp == 0;
|
||||
|
|
@ -418,9 +397,8 @@ TEMPLATE static u32 FASTCALL OP_TST()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_NEG()
|
||||
TEMPLATE static u32 FASTCALL OP_NEG(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 a = cpu->R[REG_NUM(i, 3)];
|
||||
cpu->R[REG_NUM(i, 0)] = -((signed int)a);
|
||||
|
||||
|
|
@ -432,9 +410,8 @@ TEMPLATE static u32 FASTCALL OP_NEG()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_CMP()
|
||||
TEMPLATE static u32 FASTCALL OP_CMP(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 tmp = cpu->R[REG_NUM(i, 0)] -cpu->R[REG_NUM(i, 3)];
|
||||
|
||||
cpu->CPSR.bits.N = BIT31(tmp);
|
||||
|
|
@ -445,9 +422,8 @@ TEMPLATE static u32 FASTCALL OP_CMP()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_CMN()
|
||||
TEMPLATE static u32 FASTCALL OP_CMN(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)];
|
||||
|
||||
//emu_halt();
|
||||
|
|
@ -460,9 +436,8 @@ TEMPLATE static u32 FASTCALL OP_CMN()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ORR()
|
||||
TEMPLATE static u32 FASTCALL OP_ORR(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[REG_NUM(i, 0)] |= cpu->R[REG_NUM(i, 3)];
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
|
||||
|
|
@ -470,9 +445,8 @@ TEMPLATE static u32 FASTCALL OP_ORR()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_MUL_REG()
|
||||
TEMPLATE static u32 FASTCALL OP_MUL_REG(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[REG_NUM(i, 0)] *= cpu->R[REG_NUM(i, 3)];
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
|
||||
|
|
@ -480,9 +454,8 @@ TEMPLATE static u32 FASTCALL OP_MUL_REG()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BIC()
|
||||
TEMPLATE static u32 FASTCALL OP_BIC(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[REG_NUM(i, 0)] &= (~cpu->R[REG_NUM(i, 3)]);
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
|
||||
|
|
@ -490,9 +463,8 @@ TEMPLATE static u32 FASTCALL OP_BIC()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_MVN()
|
||||
TEMPLATE static u32 FASTCALL OP_MVN(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[REG_NUM(i, 0)] = (~cpu->R[REG_NUM(i, 3)]);
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
|
||||
|
|
@ -500,9 +472,8 @@ TEMPLATE static u32 FASTCALL OP_MVN()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_SPE()
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_SPE(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 Rd = (i&7) | ((i>>4)&8);
|
||||
cpu->R[Rd] += cpu->R[REG_POS(i, 3)];
|
||||
|
||||
|
|
@ -512,9 +483,8 @@ TEMPLATE static u32 FASTCALL OP_ADD_SPE()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_CMP_SPE()
|
||||
TEMPLATE static u32 FASTCALL OP_CMP_SPE(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 Rn = (i&7) | ((i>>4)&8);
|
||||
u32 tmp = cpu->R[Rn] -cpu->R[REG_POS(i, 3)];
|
||||
|
||||
|
|
@ -526,9 +496,8 @@ TEMPLATE static u32 FASTCALL OP_CMP_SPE()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_MOV_SPE()
|
||||
TEMPLATE static u32 FASTCALL OP_MOV_SPE(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 Rd = (i&7) | ((i>>4)&8);
|
||||
cpu->R[Rd] = cpu->R[REG_POS(i, 3)];
|
||||
|
||||
|
|
@ -538,7 +507,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_SPE()
|
|||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BX_THUMB()
|
||||
TEMPLATE static u32 FASTCALL OP_BX_THUMB(const u32 i)
|
||||
{
|
||||
// When using PC as operand with BX opcode, switch to ARM state and jump to (instruct_adr+4)
|
||||
// Reference: http://nocash.emubase.de/gbatek.htm#thumb5hiregisteroperationsbranchexchange
|
||||
|
|
@ -560,7 +529,7 @@ TEMPLATE static u32 FASTCALL OP_BX_THUMB()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BLX_THUMB()
|
||||
TEMPLATE static u32 FASTCALL OP_BLX_THUMB(const u32 i)
|
||||
{
|
||||
u32 Rm = cpu->R[REG_POS(cpu->instruction, 3)];
|
||||
|
||||
|
|
@ -572,7 +541,7 @@ TEMPLATE static u32 FASTCALL OP_BLX_THUMB()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_PCREL()
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_PCREL(const u32 i)
|
||||
{
|
||||
u32 adr = (cpu->R[15]&0xFFFFFFFC) + ((cpu->instruction&0xFF)<<2);
|
||||
|
||||
|
|
@ -581,45 +550,40 @@ TEMPLATE static u32 FASTCALL OP_LDR_PCREL()
|
|||
return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STR_REG_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_STR_REG_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 6)] + cpu->R[REG_NUM(i, 3)];
|
||||
WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]);
|
||||
|
||||
return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STRH_REG_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_STRH_REG_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
WRITE16(cpu->mem_if->data, adr, ((u16)cpu->R[REG_NUM(i, 0)]));
|
||||
|
||||
return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STRB_REG_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_STRB_REG_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
WRITE8(cpu->mem_if->data, adr, ((u8)cpu->R[REG_NUM(i, 0)]));
|
||||
|
||||
return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRSB_REG_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_LDRSB_REG_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
cpu->R[REG_NUM(i, 0)] = (s32)((s8)READ8(cpu->mem_if->data, adr));
|
||||
|
||||
return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_REG_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_REG_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = (cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]);
|
||||
u32 tempValue = READ32(cpu->mem_if->data, adr&0xFFFFFFFC);
|
||||
|
||||
|
|
@ -630,45 +594,40 @@ TEMPLATE static u32 FASTCALL OP_LDR_REG_OFF()
|
|||
return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRH_REG_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_LDRH_REG_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
cpu->R[REG_NUM(i, 0)] = (u32)READ16(cpu->mem_if->data, adr);
|
||||
|
||||
return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRB_REG_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_LDRB_REG_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
cpu->R[REG_NUM(i, 0)] = (u32)READ8(cpu->mem_if->data, adr);
|
||||
|
||||
return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRSH_REG_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_LDRSH_REG_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
cpu->R[REG_NUM(i, 0)] = (s32)((s16)READ16(cpu->mem_if->data, adr));
|
||||
|
||||
return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STR_IMM_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_STR_IMM_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
|
||||
WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]);
|
||||
|
||||
return 2 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_IMM_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_IMM_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
|
||||
u32 tempValue = READ32(cpu->mem_if->data, adr&0xFFFFFFFC);
|
||||
adr = (adr&3)*8;
|
||||
|
|
@ -678,93 +637,84 @@ TEMPLATE static u32 FASTCALL OP_LDR_IMM_OFF()
|
|||
return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STRB_IMM_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_STRB_IMM_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
|
||||
WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_NUM(i, 0)]);
|
||||
|
||||
return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRB_IMM_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_LDRB_IMM_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
|
||||
cpu->R[REG_NUM(i, 0)] = READ8(cpu->mem_if->data, adr);
|
||||
|
||||
return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STRH_IMM_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_STRH_IMM_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
|
||||
WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_NUM(i, 0)]);
|
||||
|
||||
return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRH_IMM_OFF()
|
||||
TEMPLATE static u32 FASTCALL OP_LDRH_IMM_OFF(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
|
||||
cpu->R[REG_NUM(i, 0)] = READ16(cpu->mem_if->data, adr);
|
||||
|
||||
return 3 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STR_SPREL()
|
||||
TEMPLATE static u32 FASTCALL OP_STR_SPREL(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[13] + ((i&0xFF)<<2);
|
||||
WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 8)]);
|
||||
|
||||
return 2 + MMU.MMU_WAIT16[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_SPREL()
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_SPREL(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[13] + ((i&0xFF)<<2);
|
||||
cpu->R[REG_NUM(i, 8)] = READ32(cpu->mem_if->data, adr);
|
||||
|
||||
return 3 + MMU.MMU_WAIT32[PROCNUM][(adr>>24)&0xF];
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_2PC()
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_2PC(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[REG_NUM(i, 8)] = (cpu->R[15]&0xFFFFFFFC) + ((i&0xFF)<<2);
|
||||
|
||||
return 5;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_2SP()
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_2SP(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[REG_NUM(i, 8)] = cpu->R[13] + ((i&0xFF)<<2);
|
||||
|
||||
return 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADJUST_P_SP()
|
||||
TEMPLATE static u32 FASTCALL OP_ADJUST_P_SP(const u32 i)
|
||||
{
|
||||
cpu->R[13] += ((cpu->instruction&0x7F)<<2);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADJUST_M_SP()
|
||||
TEMPLATE static u32 FASTCALL OP_ADJUST_M_SP(const u32 i)
|
||||
{
|
||||
cpu->R[13] -= ((cpu->instruction&0x7F)<<2);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_PUSH()
|
||||
TEMPLATE static u32 FASTCALL OP_PUSH(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[13] - 4;
|
||||
u32 c = 0, j;
|
||||
|
||||
|
|
@ -780,9 +730,8 @@ TEMPLATE static u32 FASTCALL OP_PUSH()
|
|||
return c + 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_PUSH_LR()
|
||||
TEMPLATE static u32 FASTCALL OP_PUSH_LR(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[13] - 4;
|
||||
u32 c = 0, j;
|
||||
|
||||
|
|
@ -802,9 +751,8 @@ TEMPLATE static u32 FASTCALL OP_PUSH_LR()
|
|||
return c + 4;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_POP()
|
||||
TEMPLATE static u32 FASTCALL OP_POP(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[13];
|
||||
u32 c = 0, j;
|
||||
|
||||
|
|
@ -820,9 +768,8 @@ TEMPLATE static u32 FASTCALL OP_POP()
|
|||
return c + 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_POP_PC()
|
||||
TEMPLATE static u32 FASTCALL OP_POP_PC(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[13];
|
||||
u32 c = 0, j;
|
||||
u32 v;
|
||||
|
|
@ -847,14 +794,13 @@ TEMPLATE static u32 FASTCALL OP_POP_PC()
|
|||
return c + 5;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BKPT_THUMB()
|
||||
TEMPLATE static u32 FASTCALL OP_BKPT_THUMB(const u32 i)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STMIA_THUMB()
|
||||
TEMPLATE static u32 FASTCALL OP_STMIA_THUMB(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 adr = cpu->R[REG_NUM(i, 8)];
|
||||
u32 c = 0, j;
|
||||
|
||||
|
|
@ -869,9 +815,8 @@ TEMPLATE static u32 FASTCALL OP_STMIA_THUMB()
|
|||
return c + 2;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB()
|
||||
TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
u32 regIndex = REG_NUM(i, 8);
|
||||
u32 adr = cpu->R[regIndex];
|
||||
u32 c = 0, j;
|
||||
|
|
@ -891,9 +836,8 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB()
|
|||
return c + 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_B_COND()
|
||||
TEMPLATE static u32 FASTCALL OP_B_COND(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
if(!TEST_COND((i>>8)&0xF, 0, cpu->CPSR))
|
||||
return 1;
|
||||
|
||||
|
|
@ -902,7 +846,7 @@ TEMPLATE static u32 FASTCALL OP_B_COND()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_SWI_THUMB()
|
||||
TEMPLATE static u32 FASTCALL OP_SWI_THUMB(const u32 i)
|
||||
{
|
||||
u32 swinum = cpu->instruction & 0xFF;
|
||||
|
||||
|
|
@ -937,17 +881,15 @@ TEMPLATE static u32 FASTCALL OP_SWI_THUMB()
|
|||
|
||||
#define SIGNEEXT_IMM11(i) (((i)&0x7FF) | (BIT10(i) * 0xFFFFF800))
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_B_UNCOND()
|
||||
TEMPLATE static u32 FASTCALL OP_B_UNCOND(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[15] += (SIGNEEXT_IMM11(i)<<1);
|
||||
cpu->next_instruction = cpu->R[15];
|
||||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BLX()
|
||||
TEMPLATE static u32 FASTCALL OP_BLX(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1))&0xFFFFFFFC;
|
||||
cpu->R[14] = cpu->next_instruction | 1;
|
||||
cpu->next_instruction = cpu->R[15];
|
||||
|
|
@ -955,57 +897,37 @@ TEMPLATE static u32 FASTCALL OP_BLX()
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BL_10()
|
||||
TEMPLATE static u32 FASTCALL OP_BL_10(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[14] = cpu->R[15] + (SIGNEEXT_IMM11(i)<<12);
|
||||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BL_THUMB()
|
||||
TEMPLATE static u32 FASTCALL OP_BL_THUMB(const u32 i)
|
||||
{
|
||||
const u32 &i = cpu->instruction;
|
||||
cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1));
|
||||
cpu->R[14] = cpu->next_instruction | 1;
|
||||
cpu->next_instruction = cpu->R[15];
|
||||
return 3;
|
||||
}
|
||||
|
||||
#define TYPE_RETOUR u32
|
||||
#define CALLTYPE FASTCALL
|
||||
#define PARAMETRES
|
||||
#define NOM_THUMB_TAB thumb_instructions_set_0
|
||||
#define TABDECL(x) x<0>
|
||||
|
||||
TYPE_RETOUR (* CALLTYPE NOM_THUMB_TAB[1024])(PARAMETRES)={
|
||||
|
||||
|
||||
#define TABDECL(x) x<0>
|
||||
const ThumbOpFunc thumb_instructions_set_0[1024] = {
|
||||
#include "thumb_tabdef.inc"
|
||||
};
|
||||
|
||||
#undef TYPE_RETOUR
|
||||
#undef PARAMETRES
|
||||
#undef CALLTYPE
|
||||
#undef NOM_THUMB_TAB
|
||||
#undef TABDECL
|
||||
|
||||
#define TYPE_RETOUR u32
|
||||
#define PARAMETRES
|
||||
#define CALLTYPE FASTCALL
|
||||
#define NOM_THUMB_TAB thumb_instructions_set_1
|
||||
#define TABDECL(x) x<1>
|
||||
|
||||
TYPE_RETOUR (* CALLTYPE NOM_THUMB_TAB[1024])(PARAMETRES)={
|
||||
#define TABDECL(x) x<1>
|
||||
const ThumbOpFunc thumb_instructions_set_1[1024] = {
|
||||
#include "thumb_tabdef.inc"
|
||||
};
|
||||
|
||||
#undef TYPE_RETOUR
|
||||
#undef PARAMETRES
|
||||
#undef CALLTYPE
|
||||
#undef NOM_TAB
|
||||
#undef TABDECL
|
||||
|
||||
#define TABDECL(x) #x
|
||||
|
||||
const char* thumb_instruction_names[1024] = {
|
||||
#include "thumb_tabdef.inc"
|
||||
};
|
||||
|
||||
#undef TABDECL
|
||||
|
|
|
|||
|
|
@ -23,8 +23,11 @@
|
|||
|
||||
#include "armcpu.h"
|
||||
|
||||
extern u32 (FASTCALL* thumb_instructions_set_0[1024])();
|
||||
extern u32 (FASTCALL* thumb_instructions_set_1[1024])();
|
||||
typedef u32 (FASTCALL* ThumbOpFunc)(const u32 i);
|
||||
|
||||
extern const ThumbOpFunc thumb_instructions_set_0[1024];
|
||||
extern const ThumbOpFunc thumb_instructions_set_1[1024];
|
||||
|
||||
extern const char* thumb_instruction_names[1024];
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue