rename FASTCALL to DESMUME_FASTCALL
mingw's winnt.h uses FASTCALL for its own purposes, so depending on the include order the code uses either mingw's definition, or the one from types.h. that makes it almost impossible to reason which definition ends up being used, even though it's of utmost importance to have the jit perform correctly.
This commit is contained in:
rofl0r
parent
c2af88cd10
commit
18f166bc97
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@ -1293,7 +1293,7 @@ void GC_Command::fromCryptoBuffer(u32 buf[2])
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}
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template<int PROCNUM>
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void FASTCALL MMU_writeToGCControl(u32 val)
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void DESMUME_FASTCALL MMU_writeToGCControl(u32 val)
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{
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int dbsize = (val>>24)&7;
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@ -1374,7 +1374,7 @@ void FASTCALL MMU_writeToGCControl(u32 val)
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}
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/*template<int PROCNUM>
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u32 FASTCALL MMU_readFromGCControl()
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u32 DESMUME_FASTCALL MMU_readFromGCControl()
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{
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return T1ReadLong(MMU.MMU_MEM[0][0x40], 0x1A4);
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}*/
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@ -1452,7 +1452,7 @@ static void CalculateTouchPressure(int pressurePercent, u16 &z1, u16& z2)
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}
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void FASTCALL MMU_writeToSPIData(u16 val)
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void DESMUME_FASTCALL MMU_writeToSPIData(u16 val)
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{
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enum PM_Bits //from libnds
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@ -3332,7 +3332,7 @@ template bool MMU_WriteFromExternal<u32, 4>(const int targetProc, const u32 targ
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//=========================================================================================================
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//=========================================================================================================
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//================================================= MMU write 08
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void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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void DESMUME_FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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{
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adr &= 0x0FFFFFFF;
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const u32 adrBank = (adr >> 24);
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@ -3888,7 +3888,7 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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}
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//================================================= MMU ARM9 write 16
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void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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void DESMUME_FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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{
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adr &= 0x0FFFFFFE;
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const u32 adrBank = (adr >> 24);
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@ -4604,7 +4604,7 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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}
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//================================================= MMU ARM9 write 32
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void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
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void DESMUME_FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
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{
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adr &= 0x0FFFFFFC;
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const u32 adrBank = (adr >> 24);
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@ -5147,7 +5147,7 @@ void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
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}
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//================================================= MMU ARM9 read 08
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u8 FASTCALL _MMU_ARM9_read08(u32 adr)
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u8 DESMUME_FASTCALL _MMU_ARM9_read08(u32 adr)
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{
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adr &= 0x0FFFFFFF;
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@ -5270,7 +5270,7 @@ u8 FASTCALL _MMU_ARM9_read08(u32 adr)
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}
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//================================================= MMU ARM9 read 16
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u16 FASTCALL _MMU_ARM9_read16(u32 adr)
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u16 DESMUME_FASTCALL _MMU_ARM9_read16(u32 adr)
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{
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adr &= 0x0FFFFFFE;
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@ -5380,7 +5380,7 @@ u16 FASTCALL _MMU_ARM9_read16(u32 adr)
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}
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//================================================= MMU ARM9 read 32
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u32 FASTCALL _MMU_ARM9_read32(u32 adr)
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u32 DESMUME_FASTCALL _MMU_ARM9_read32(u32 adr)
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{
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adr &= 0x0FFFFFFC;
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@ -5530,7 +5530,7 @@ u32 FASTCALL _MMU_ARM9_read32(u32 adr)
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//=========================================================================================================
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//=========================================================================================================
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//================================================= MMU ARM7 write 08
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void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
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void DESMUME_FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
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{
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adr &= 0x0FFFFFFF;
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@ -5658,7 +5658,7 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
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}
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//================================================= MMU ARM7 write 16
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void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
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void DESMUME_FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
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{
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adr &= 0x0FFFFFFE;
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@ -5843,7 +5843,7 @@ void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
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}
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//================================================= MMU ARM7 write 32
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void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
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void DESMUME_FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
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{
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adr &= 0x0FFFFFFC;
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@ -5946,7 +5946,7 @@ void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
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}
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//================================================= MMU ARM7 read 08
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u8 FASTCALL _MMU_ARM7_read08(u32 adr)
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u8 DESMUME_FASTCALL _MMU_ARM7_read08(u32 adr)
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{
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adr &= 0x0FFFFFFF;
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@ -6028,7 +6028,7 @@ u8 FASTCALL _MMU_ARM7_read08(u32 adr)
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return MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]];
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}
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//================================================= MMU ARM7 read 16
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u16 FASTCALL _MMU_ARM7_read16(u32 adr)
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u16 DESMUME_FASTCALL _MMU_ARM7_read16(u32 adr)
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{
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adr &= 0x0FFFFFFE;
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@ -6114,7 +6114,7 @@ u16 FASTCALL _MMU_ARM7_read16(u32 adr)
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return T1ReadWord_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][adr >> 20], adr & MMU.MMU_MASK[ARMCPU_ARM7][adr >> 20]);
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}
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//================================================= MMU ARM7 read 32
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u32 FASTCALL _MMU_ARM7_read32(u32 adr)
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u32 DESMUME_FASTCALL _MMU_ARM7_read32(u32 adr)
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{
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adr &= 0x0FFFFFFC;
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@ -6198,7 +6198,7 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr)
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//=========================================================================================================
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u32 FASTCALL MMU_read32(u32 proc, u32 adr)
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u32 DESMUME_FASTCALL MMU_read32(u32 proc, u32 adr)
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{
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ASSERT_UNALIGNED((adr&3)==0);
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@ -6208,7 +6208,7 @@ u32 FASTCALL MMU_read32(u32 proc, u32 adr)
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return _MMU_ARM7_read32(adr);
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}
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u16 FASTCALL MMU_read16(u32 proc, u32 adr)
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u16 DESMUME_FASTCALL MMU_read16(u32 proc, u32 adr)
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{
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ASSERT_UNALIGNED((adr&1)==0);
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@ -6218,7 +6218,7 @@ u16 FASTCALL MMU_read16(u32 proc, u32 adr)
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return _MMU_ARM7_read16(adr);
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}
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u8 FASTCALL MMU_read8(u32 proc, u32 adr)
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u8 DESMUME_FASTCALL MMU_read8(u32 proc, u32 adr)
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{
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if(proc==0)
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return _MMU_ARM9_read08(adr);
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@ -6226,7 +6226,7 @@ u8 FASTCALL MMU_read8(u32 proc, u32 adr)
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return _MMU_ARM7_read08(adr);
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}
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void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
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void DESMUME_FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
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{
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ASSERT_UNALIGNED((adr&3)==0);
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@ -6236,7 +6236,7 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
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_MMU_ARM7_write32(adr,val);
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}
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void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val)
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void DESMUME_FASTCALL MMU_write16(u32 proc, u32 adr, u16 val)
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{
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ASSERT_UNALIGNED((adr&1)==0);
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@ -6246,7 +6246,7 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val)
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_MMU_ARM7_write16(adr,val);
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}
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void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val)
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void DESMUME_FASTCALL MMU_write8(u32 proc, u32 adr, u8 val)
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{
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if(proc==0)
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_MMU_ARM9_write08(adr, val);
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@ -6254,7 +6254,7 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val)
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_MMU_ARM7_write08(adr,val);
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}
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void FASTCALL MMU_DumpMemBlock(u8 proc, u32 address, u32 size, u8 *buffer)
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void DESMUME_FASTCALL MMU_DumpMemBlock(u8 proc, u32 address, u32 size, u8 *buffer)
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{
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u32 i;
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u32 curaddr;
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@ -6273,67 +6273,67 @@ template u32 MMU_struct::gen_IF<ARMCPU_ARM7>();
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////////////////////////////////////////////////////////////
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//function pointer handlers for gdb stub stuff
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static u16 FASTCALL arm9_prefetch16( void *data, u32 adr) {
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static u16 DESMUME_FASTCALL arm9_prefetch16( void *data, u32 adr) {
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return _MMU_read16<ARMCPU_ARM9,MMU_AT_CODE>(adr);
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}
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static u32 FASTCALL arm9_prefetch32( void *data, u32 adr) {
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static u32 DESMUME_FASTCALL arm9_prefetch32( void *data, u32 adr) {
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return _MMU_read32<ARMCPU_ARM9,MMU_AT_CODE>(adr);
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}
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static u8 FASTCALL arm9_read8( void *data, u32 adr) {
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static u8 DESMUME_FASTCALL arm9_read8( void *data, u32 adr) {
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return _MMU_read08<ARMCPU_ARM9>(adr);
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}
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static u16 FASTCALL arm9_read16( void *data, u32 adr) {
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static u16 DESMUME_FASTCALL arm9_read16( void *data, u32 adr) {
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return _MMU_read16<ARMCPU_ARM9>(adr);
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}
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static u32 FASTCALL arm9_read32( void *data, u32 adr) {
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static u32 DESMUME_FASTCALL arm9_read32( void *data, u32 adr) {
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return _MMU_read32<ARMCPU_ARM9>(adr);
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}
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static void FASTCALL arm9_write8(void *data, u32 adr, u8 val) {
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static void DESMUME_FASTCALL arm9_write8(void *data, u32 adr, u8 val) {
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_MMU_write08<ARMCPU_ARM9>(adr, val);
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}
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static void FASTCALL arm9_write16(void *data, u32 adr, u16 val) {
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static void DESMUME_FASTCALL arm9_write16(void *data, u32 adr, u16 val) {
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_MMU_write16<ARMCPU_ARM9>(adr, val);
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}
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static void FASTCALL arm9_write32(void *data, u32 adr, u32 val) {
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static void DESMUME_FASTCALL arm9_write32(void *data, u32 adr, u32 val) {
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_MMU_write32<ARMCPU_ARM9>(adr, val);
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}
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static u16 FASTCALL arm7_prefetch16( void *data, u32 adr) {
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static u16 DESMUME_FASTCALL arm7_prefetch16( void *data, u32 adr) {
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return _MMU_read16<ARMCPU_ARM7,MMU_AT_CODE>(adr);
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}
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static u32 FASTCALL arm7_prefetch32( void *data, u32 adr) {
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static u32 DESMUME_FASTCALL arm7_prefetch32( void *data, u32 adr) {
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return _MMU_read32<ARMCPU_ARM7,MMU_AT_CODE>(adr);
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}
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static u8 FASTCALL arm7_read8( void *data, u32 adr) {
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static u8 DESMUME_FASTCALL arm7_read8( void *data, u32 adr) {
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return _MMU_read08<ARMCPU_ARM7>(adr);
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}
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static u16 FASTCALL arm7_read16( void *data, u32 adr) {
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static u16 DESMUME_FASTCALL arm7_read16( void *data, u32 adr) {
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return _MMU_read16<ARMCPU_ARM7>(adr);
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}
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static u32 FASTCALL arm7_read32( void *data, u32 adr) {
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static u32 DESMUME_FASTCALL arm7_read32( void *data, u32 adr) {
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return _MMU_read32<ARMCPU_ARM7>(adr);
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}
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static void FASTCALL arm7_write8(void *data, u32 adr, u8 val) {
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static void DESMUME_FASTCALL arm7_write8(void *data, u32 adr, u8 val) {
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_MMU_write08<ARMCPU_ARM7>(adr, val);
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}
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static void FASTCALL arm7_write16(void *data, u32 adr, u16 val) {
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static void DESMUME_FASTCALL arm7_write16(void *data, u32 adr, u16 val) {
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_MMU_write16<ARMCPU_ARM7>(adr, val);
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}
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static void FASTCALL arm7_write32(void *data, u32 adr, u32 val) {
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static void DESMUME_FASTCALL arm7_write32(void *data, u32 adr, u32 val) {
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_MMU_write32<ARMCPU_ARM7>(adr, val);
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}
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@ -514,24 +514,24 @@ extern MMU_struct_new MMU_new;
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struct armcpu_memory_iface
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{
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/** the 32 bit instruction prefetch */
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u32 FASTCALL (*prefetch32)( void *data, u32 adr);
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u32 DESMUME_FASTCALL (*prefetch32)( void *data, u32 adr);
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/** the 16 bit instruction prefetch */
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u16 FASTCALL (*prefetch16)( void *data, u32 adr);
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u16 DESMUME_FASTCALL (*prefetch16)( void *data, u32 adr);
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/** read 8 bit data value */
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u8 FASTCALL (*read8)( void *data, u32 adr);
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u8 DESMUME_FASTCALL (*read8)( void *data, u32 adr);
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/** read 16 bit data value */
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u16 FASTCALL (*read16)( void *data, u32 adr);
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u16 DESMUME_FASTCALL (*read16)( void *data, u32 adr);
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/** read 32 bit data value */
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u32 FASTCALL (*read32)( void *data, u32 adr);
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u32 DESMUME_FASTCALL (*read32)( void *data, u32 adr);
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/** write 8 bit data value */
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void FASTCALL (*write8)( void *data, u32 adr, u8 val);
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void DESMUME_FASTCALL (*write8)( void *data, u32 adr, u8 val);
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/** write 16 bit data value */
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void FASTCALL (*write16)( void *data, u32 adr, u16 val);
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void DESMUME_FASTCALL (*write16)( void *data, u32 adr, u16 val);
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/** write 32 bit data value */
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void FASTCALL (*write32)( void *data, u32 adr, u32 val);
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void DESMUME_FASTCALL (*write32)( void *data, u32 adr, u32 val);
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void *data;
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};
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@ -545,14 +545,14 @@ void MMU_Reset( void);
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void print_memory_profiling( void);
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// Memory reading/writing (old)
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u8 FASTCALL MMU_read8(u32 proc, u32 adr);
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u16 FASTCALL MMU_read16(u32 proc, u32 adr);
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u32 FASTCALL MMU_read32(u32 proc, u32 adr);
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void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val);
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void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val);
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void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val);
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u8 DESMUME_FASTCALL MMU_read8(u32 proc, u32 adr);
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u16 DESMUME_FASTCALL MMU_read16(u32 proc, u32 adr);
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u32 DESMUME_FASTCALL MMU_read32(u32 proc, u32 adr);
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void DESMUME_FASTCALL MMU_write8(u32 proc, u32 adr, u8 val);
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void DESMUME_FASTCALL MMU_write16(u32 proc, u32 adr, u16 val);
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void DESMUME_FASTCALL MMU_write32(u32 proc, u32 adr, u32 val);
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//template<int PROCNUM> void FASTCALL MMU_doDMA(u32 num);
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//template<int PROCNUM> void DESMUME_FASTCALL MMU_doDMA(u32 num);
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//The base ARM memory interfaces
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extern const armcpu_memory_iface arm9_base_memory_iface;
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@ -645,19 +645,19 @@ template<int PROCNUM> FORCEINLINE void _MMU_write08(u32 addr, u8 val) { _MMU_wri
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template<int PROCNUM> FORCEINLINE void _MMU_write16(u32 addr, u16 val) { _MMU_write16<PROCNUM, MMU_AT_DATA>(addr,val); }
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template<int PROCNUM> FORCEINLINE void _MMU_write32(u32 addr, u32 val) { _MMU_write32<PROCNUM, MMU_AT_DATA>(addr,val); }
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void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val);
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void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val);
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void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val);
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u8 FASTCALL _MMU_ARM9_read08(u32 adr);
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u16 FASTCALL _MMU_ARM9_read16(u32 adr);
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u32 FASTCALL _MMU_ARM9_read32(u32 adr);
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void DESMUME_FASTCALL _MMU_ARM9_write08(u32 adr, u8 val);
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void DESMUME_FASTCALL _MMU_ARM9_write16(u32 adr, u16 val);
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void DESMUME_FASTCALL _MMU_ARM9_write32(u32 adr, u32 val);
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u8 DESMUME_FASTCALL _MMU_ARM9_read08(u32 adr);
|
||||
u16 DESMUME_FASTCALL _MMU_ARM9_read16(u32 adr);
|
||||
u32 DESMUME_FASTCALL _MMU_ARM9_read32(u32 adr);
|
||||
|
||||
void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val);
|
||||
void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val);
|
||||
void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val);
|
||||
u8 FASTCALL _MMU_ARM7_read08(u32 adr);
|
||||
u16 FASTCALL _MMU_ARM7_read16(u32 adr);
|
||||
u32 FASTCALL _MMU_ARM7_read32(u32 adr);
|
||||
void DESMUME_FASTCALL _MMU_ARM7_write08(u32 adr, u8 val);
|
||||
void DESMUME_FASTCALL _MMU_ARM7_write16(u32 adr, u16 val);
|
||||
void DESMUME_FASTCALL _MMU_ARM7_write32(u32 adr, u32 val);
|
||||
u8 DESMUME_FASTCALL _MMU_ARM7_read08(u32 adr);
|
||||
u16 DESMUME_FASTCALL _MMU_ARM7_read16(u32 adr);
|
||||
u32 DESMUME_FASTCALL _MMU_ARM7_read32(u32 adr);
|
||||
|
||||
extern u32 partie;
|
||||
|
||||
|
|
@ -1047,12 +1047,12 @@ FORCEINLINE void _MMU_write32(const int PROCNUM, const MMU_ACCESS_TYPE AT, const
|
|||
|
||||
|
||||
//#ifdef MMU_ENABLE_ACL
|
||||
// void FASTCALL MMU_write8_acl(u32 proc, u32 adr, u8 val);
|
||||
// void FASTCALL MMU_write16_acl(u32 proc, u32 adr, u16 val);
|
||||
// void FASTCALL MMU_write32_acl(u32 proc, u32 adr, u32 val);
|
||||
// u8 FASTCALL MMU_read8_acl(u32 proc, u32 adr, u32 access);
|
||||
// u16 FASTCALL MMU_read16_acl(u32 proc, u32 adr, u32 access);
|
||||
// u32 FASTCALL MMU_read32_acl(u32 proc, u32 adr, u32 access);
|
||||
// void DESMUME_FASTCALL MMU_write8_acl(u32 proc, u32 adr, u8 val);
|
||||
// void DESMUME_FASTCALL MMU_write16_acl(u32 proc, u32 adr, u16 val);
|
||||
// void DESMUME_FASTCALL MMU_write32_acl(u32 proc, u32 adr, u32 val);
|
||||
// u8 DESMUME_FASTCALL MMU_read8_acl(u32 proc, u32 adr, u32 access);
|
||||
// u16 DESMUME_FASTCALL MMU_read16_acl(u32 proc, u32 adr, u32 access);
|
||||
// u32 DESMUME_FASTCALL MMU_read32_acl(u32 proc, u32 adr, u32 access);
|
||||
//#else
|
||||
// #define MMU_write8_acl(proc, adr, val) _MMU_write08<proc>(adr, val)
|
||||
// #define MMU_write16_acl(proc, adr, val) _MMU_write16<proc>(adr, val)
|
||||
|
|
@ -1097,6 +1097,6 @@ FORCEINLINE void _MMU_write16(u32 addr, u16 val) { _MMU_write16(PROCNUM, AT, add
|
|||
template<int PROCNUM, MMU_ACCESS_TYPE AT>
|
||||
FORCEINLINE void _MMU_write32(u32 addr, u32 val) { _MMU_write32(PROCNUM, AT, addr, val); }
|
||||
|
||||
void FASTCALL MMU_DumpMemBlock(u8 proc, u32 address, u32 size, u8 *buffer);
|
||||
void DESMUME_FASTCALL MMU_DumpMemBlock(u8 proc, u32 address, u32 size, u8 *buffer);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1530,7 +1530,7 @@ static int OP_MSR_SPSR_IMM_VAL(const u32 i) { OP_MSR_(SPSR, IMM_VAL, 0); }
|
|||
//-----------------------------------------------------------------------------
|
||||
// LDR
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef u32 (FASTCALL* OpLDR)(u32, u32*);
|
||||
typedef u32 (DESMUME_FASTCALL* OpLDR)(u32, u32*);
|
||||
|
||||
// 98% of all memory accesses land in the same region as the first execution of
|
||||
// that instruction, so keep multiple copies with different fastpaths.
|
||||
|
|
@ -1561,7 +1561,7 @@ static u32 classify_adr(u32 adr, bool store)
|
|||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_LDR(u32 adr, u32 *dstreg)
|
||||
static u32 DESMUME_FASTCALL OP_LDR(u32 adr, u32 *dstreg)
|
||||
{
|
||||
u32 data = READ32(cpu->mem_if->data, adr);
|
||||
if(adr&3)
|
||||
|
|
@ -1571,28 +1571,28 @@ static u32 FASTCALL OP_LDR(u32 adr, u32 *dstreg)
|
|||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_LDRH(u32 adr, u32 *dstreg)
|
||||
static u32 DESMUME_FASTCALL OP_LDRH(u32 adr, u32 *dstreg)
|
||||
{
|
||||
*dstreg = READ16(cpu->mem_if->data, adr);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
|
||||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_LDRSH(u32 adr, u32 *dstreg)
|
||||
static u32 DESMUME_FASTCALL OP_LDRSH(u32 adr, u32 *dstreg)
|
||||
{
|
||||
*dstreg = (s16)READ16(cpu->mem_if->data, adr);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
|
||||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_LDRB(u32 adr, u32 *dstreg)
|
||||
static u32 DESMUME_FASTCALL OP_LDRB(u32 adr, u32 *dstreg)
|
||||
{
|
||||
*dstreg = READ8(cpu->mem_if->data, adr);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
|
||||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_LDRSB(u32 adr, u32 *dstreg)
|
||||
static u32 DESMUME_FASTCALL OP_LDRSB(u32 adr, u32 *dstreg)
|
||||
{
|
||||
*dstreg = (s8)READ8(cpu->mem_if->data, adr);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
|
||||
|
|
@ -1774,27 +1774,27 @@ static int OP_LDRSB_POS_INDE_M_REG_OFF(const u32 i) { OP_LDR_(LDRSB, REG_OFF, su
|
|||
// STR
|
||||
//-----------------------------------------------------------------------------
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_STR(u32 adr, u32 data)
|
||||
static u32 DESMUME_FASTCALL OP_STR(u32 adr, u32 data)
|
||||
{
|
||||
WRITE32(cpu->mem_if->data, adr, data);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
|
||||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_STRH(u32 adr, u32 data)
|
||||
static u32 DESMUME_FASTCALL OP_STRH(u32 adr, u32 data)
|
||||
{
|
||||
WRITE16(cpu->mem_if->data, adr, data);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
|
||||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_STRB(u32 adr, u32 data)
|
||||
static u32 DESMUME_FASTCALL OP_STRB(u32 adr, u32 data)
|
||||
{
|
||||
WRITE8(cpu->mem_if->data, adr, data);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
|
||||
}
|
||||
|
||||
typedef u32 (FASTCALL* OpSTR)(u32, u32);
|
||||
typedef u32 (DESMUME_FASTCALL* OpSTR)(u32, u32);
|
||||
#define T(op) op<0,0>, op<0,1>, op<0,2>, op<1,0>, op<1,1>, NULL
|
||||
static const OpSTR STR_tab[2][3] = { T(OP_STR) };
|
||||
static const OpSTR STRH_tab[2][3] = { T(OP_STRH) };
|
||||
|
|
@ -1913,9 +1913,9 @@ static int OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) { OP_STR_(STRB, ROR_IMM, s
|
|||
//-----------------------------------------------------------------------------
|
||||
// LDRD / STRD
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef u32 FASTCALL (*LDRD_STRD_REG)(u32);
|
||||
typedef u32 DESMUME_FASTCALL (*LDRD_STRD_REG)(u32);
|
||||
template<int PROCNUM, u8 Rnum>
|
||||
static u32 FASTCALL OP_LDRD_REG(u32 adr)
|
||||
static u32 DESMUME_FASTCALL OP_LDRD_REG(u32 adr)
|
||||
{
|
||||
cpu->R[Rnum] = READ32(cpu->mem_if->data, adr);
|
||||
|
||||
|
|
@ -1929,7 +1929,7 @@ static u32 FASTCALL OP_LDRD_REG(u32 adr)
|
|||
return MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(adr);
|
||||
}
|
||||
template<int PROCNUM, u8 Rnum>
|
||||
static u32 FASTCALL OP_STRD_REG(u32 adr)
|
||||
static u32 DESMUME_FASTCALL OP_STRD_REG(u32 adr)
|
||||
{
|
||||
WRITE32(cpu->mem_if->data, adr, cpu->R[Rnum]);
|
||||
|
||||
|
|
@ -2044,7 +2044,7 @@ static int OP_LDRD_STRD_OFFSET_PRE_INDEX(const u32 i)
|
|||
// SWP/SWPB
|
||||
//-----------------------------------------------------------------------------
|
||||
template<int PROCNUM>
|
||||
static u32 FASTCALL op_swp(u32 adr, u32 *Rd, u32 Rs)
|
||||
static u32 DESMUME_FASTCALL op_swp(u32 adr, u32 *Rd, u32 Rs)
|
||||
{
|
||||
u32 tmp = ROR(READ32(cpu->mem_if->data, adr), (adr & 3)<<3);
|
||||
WRITE32(cpu->mem_if->data, adr, Rs);
|
||||
|
|
@ -2052,7 +2052,7 @@ static u32 FASTCALL op_swp(u32 adr, u32 *Rd, u32 Rs)
|
|||
return (MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(adr) + MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(adr));
|
||||
}
|
||||
template<int PROCNUM>
|
||||
static u32 FASTCALL op_swpb(u32 adr, u32 *Rd, u32 Rs)
|
||||
static u32 DESMUME_FASTCALL op_swpb(u32 adr, u32 *Rd, u32 Rs)
|
||||
{
|
||||
u32 tmp = READ8(cpu->mem_if->data, adr);
|
||||
WRITE8(cpu->mem_if->data, adr, Rs);
|
||||
|
|
@ -2060,7 +2060,7 @@ static u32 FASTCALL op_swpb(u32 adr, u32 *Rd, u32 Rs)
|
|||
return (MMU_memAccessCycles<PROCNUM,8,MMU_AD_READ>(adr) + MMU_memAccessCycles<PROCNUM,8,MMU_AD_WRITE>(adr));
|
||||
}
|
||||
|
||||
typedef u32 FASTCALL (*OP_SWP_SWPB)(u32, u32*, u32);
|
||||
typedef u32 DESMUME_FASTCALL (*OP_SWP_SWPB)(u32, u32*, u32);
|
||||
static const OP_SWP_SWPB op_swp_tab[2][2] = {{ op_swp<0>, op_swp<1> }, { op_swpb<0>, op_swpb<1> }};
|
||||
|
||||
static int op_swp_(const u32 i, int b)
|
||||
|
|
@ -2119,7 +2119,7 @@ static u64 get_reg_list(u32 reg_mask, int dir)
|
|||
#endif
|
||||
|
||||
template <int PROCNUM, bool store, int dir>
|
||||
static LDM_INLINE FASTCALL u32 OP_LDM_STM_generic(u32 adr, u64 regs, int n)
|
||||
static LDM_INLINE DESMUME_FASTCALL u32 OP_LDM_STM_generic(u32 adr, u64 regs, int n)
|
||||
{
|
||||
u32 cycles = 0;
|
||||
adr &= ~3;
|
||||
|
|
@ -2140,7 +2140,7 @@ static LDM_INLINE FASTCALL u32 OP_LDM_STM_generic(u32 adr, u64 regs, int n)
|
|||
#endif
|
||||
|
||||
template <int PROCNUM, bool store, int dir>
|
||||
static LDM_INLINE FASTCALL u32 OP_LDM_STM_other(u32 adr, u64 regs, int n)
|
||||
static LDM_INLINE DESMUME_FASTCALL u32 OP_LDM_STM_other(u32 adr, u64 regs, int n)
|
||||
{
|
||||
u32 cycles = 0;
|
||||
adr &= ~3;
|
||||
|
|
@ -2162,7 +2162,7 @@ static LDM_INLINE FASTCALL u32 OP_LDM_STM_other(u32 adr, u64 regs, int n)
|
|||
}
|
||||
|
||||
template <int PROCNUM, bool store, int dir, bool null_compiled>
|
||||
static FORCEINLINE FASTCALL u32 OP_LDM_STM_main(u32 adr, u64 regs, int n, u8 *ptr, u32 cycles)
|
||||
static FORCEINLINE DESMUME_FASTCALL u32 OP_LDM_STM_main(u32 adr, u64 regs, int n, u8 *ptr, u32 cycles)
|
||||
{
|
||||
#ifdef ENABLE_ADVANCED_TIMING
|
||||
cycles = 0;
|
||||
|
|
@ -2201,7 +2201,7 @@ static FORCEINLINE FASTCALL u32 OP_LDM_STM_main(u32 adr, u64 regs, int n, u8 *pt
|
|||
}
|
||||
|
||||
template <int PROCNUM, bool store, int dir>
|
||||
static u32 FASTCALL OP_LDM_STM(u32 adr, u64 regs, int n)
|
||||
static u32 DESMUME_FASTCALL OP_LDM_STM(u32 adr, u64 regs, int n)
|
||||
{
|
||||
// TODO use classify_adr?
|
||||
u32 cycles;
|
||||
|
|
@ -2242,7 +2242,7 @@ static u32 FASTCALL OP_LDM_STM(u32 adr, u64 regs, int n)
|
|||
return OP_LDM_STM_main<PROCNUM, store, dir, store>(adr, regs, n, ptr, cycles);
|
||||
}
|
||||
|
||||
typedef u32 FASTCALL (*LDMOpFunc)(u32,u64,int);
|
||||
typedef u32 DESMUME_FASTCALL (*LDMOpFunc)(u32,u64,int);
|
||||
static const LDMOpFunc op_ldm_stm_tab[2][2][2] = {{
|
||||
{ OP_LDM_STM<0,0,-1>, OP_LDM_STM<0,0,+1> },
|
||||
{ OP_LDM_STM<0,1,-1>, OP_LDM_STM<0,1,+1> },
|
||||
|
|
@ -3849,7 +3849,7 @@ static const ArmOpCompiler thumb_instruction_compilers[1024] = {
|
|||
//-----------------------------------------------------------------------------
|
||||
|
||||
template<int PROCNUM, int thumb>
|
||||
static u32 FASTCALL OP_DECODE()
|
||||
static u32 DESMUME_FASTCALL OP_DECODE()
|
||||
{
|
||||
u32 cycles;
|
||||
u32 adr = cpu->instruct_adr;
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
typedef u32 (FASTCALL* ArmOpCompiled)();
|
||||
typedef u32 (DESMUME_FASTCALL* ArmOpCompiled)();
|
||||
|
||||
void arm_jit_reset(bool enable, bool suppress_msg = false);
|
||||
void arm_jit_close();
|
||||
|
|
|
|||
|
|
@ -460,23 +460,23 @@ FORCEINLINE static u32 armcpu_prefetch()
|
|||
}
|
||||
|
||||
#if 0 /* not used */
|
||||
static BOOL FASTCALL test_EQ(Status_Reg CPSR) { return ( CPSR.bits.Z); }
|
||||
static BOOL FASTCALL test_NE(Status_Reg CPSR) { return (!CPSR.bits.Z); }
|
||||
static BOOL FASTCALL test_CS(Status_Reg CPSR) { return ( CPSR.bits.C); }
|
||||
static BOOL FASTCALL test_CC(Status_Reg CPSR) { return (!CPSR.bits.C); }
|
||||
static BOOL FASTCALL test_MI(Status_Reg CPSR) { return ( CPSR.bits.N); }
|
||||
static BOOL FASTCALL test_PL(Status_Reg CPSR) { return (!CPSR.bits.N); }
|
||||
static BOOL FASTCALL test_VS(Status_Reg CPSR) { return ( CPSR.bits.V); }
|
||||
static BOOL FASTCALL test_VC(Status_Reg CPSR) { return (!CPSR.bits.V); }
|
||||
static BOOL FASTCALL test_HI(Status_Reg CPSR) { return (CPSR.bits.C) && (!CPSR.bits.Z); }
|
||||
static BOOL FASTCALL test_LS(Status_Reg CPSR) { return (CPSR.bits.Z) || (!CPSR.bits.C); }
|
||||
static BOOL FASTCALL test_GE(Status_Reg CPSR) { return (CPSR.bits.N==CPSR.bits.V); }
|
||||
static BOOL FASTCALL test_LT(Status_Reg CPSR) { return (CPSR.bits.N!=CPSR.bits.V); }
|
||||
static BOOL FASTCALL test_GT(Status_Reg CPSR) { return (!CPSR.bits.Z) && (CPSR.bits.N==CPSR.bits.V); }
|
||||
static BOOL FASTCALL test_LE(Status_Reg CPSR) { return ( CPSR.bits.Z) || (CPSR.bits.N!=CPSR.bits.V); }
|
||||
static BOOL FASTCALL test_AL(Status_Reg CPSR) { return 1; }
|
||||
static BOOL DESMUME_FASTCALL test_EQ(Status_Reg CPSR) { return ( CPSR.bits.Z); }
|
||||
static BOOL DESMUME_FASTCALL test_NE(Status_Reg CPSR) { return (!CPSR.bits.Z); }
|
||||
static BOOL DESMUME_FASTCALL test_CS(Status_Reg CPSR) { return ( CPSR.bits.C); }
|
||||
static BOOL DESMUME_FASTCALL test_CC(Status_Reg CPSR) { return (!CPSR.bits.C); }
|
||||
static BOOL DESMUME_FASTCALL test_MI(Status_Reg CPSR) { return ( CPSR.bits.N); }
|
||||
static BOOL DESMUME_FASTCALL test_PL(Status_Reg CPSR) { return (!CPSR.bits.N); }
|
||||
static BOOL DESMUME_FASTCALL test_VS(Status_Reg CPSR) { return ( CPSR.bits.V); }
|
||||
static BOOL DESMUME_FASTCALL test_VC(Status_Reg CPSR) { return (!CPSR.bits.V); }
|
||||
static BOOL DESMUME_FASTCALL test_HI(Status_Reg CPSR) { return (CPSR.bits.C) && (!CPSR.bits.Z); }
|
||||
static BOOL DESMUME_FASTCALL test_LS(Status_Reg CPSR) { return (CPSR.bits.Z) || (!CPSR.bits.C); }
|
||||
static BOOL DESMUME_FASTCALL test_GE(Status_Reg CPSR) { return (CPSR.bits.N==CPSR.bits.V); }
|
||||
static BOOL DESMUME_FASTCALL test_LT(Status_Reg CPSR) { return (CPSR.bits.N!=CPSR.bits.V); }
|
||||
static BOOL DESMUME_FASTCALL test_GT(Status_Reg CPSR) { return (!CPSR.bits.Z) && (CPSR.bits.N==CPSR.bits.V); }
|
||||
static BOOL DESMUME_FASTCALL test_LE(Status_Reg CPSR) { return ( CPSR.bits.Z) || (CPSR.bits.N!=CPSR.bits.V); }
|
||||
static BOOL DESMUME_FASTCALL test_AL(Status_Reg CPSR) { return 1; }
|
||||
|
||||
static BOOL (FASTCALL* test_conditions[])(Status_Reg CPSR)= {
|
||||
static BOOL (DESMUME_FASTCALL* test_conditions[])(Status_Reg CPSR)= {
|
||||
test_EQ , test_NE ,
|
||||
test_CS , test_CC ,
|
||||
test_MI , test_PL ,
|
||||
|
|
|
|||
|
|
@ -1386,7 +1386,7 @@ WINAPI listenerThread_gdb( void *data) {
|
|||
* The memory interface
|
||||
*
|
||||
*/
|
||||
static uint32_t FASTCALL gdb_prefetch32( void *data, uint32_t adr) {
|
||||
static uint32_t DESMUME_FASTCALL gdb_prefetch32( void *data, uint32_t adr) {
|
||||
struct gdb_stub_state *stub = (struct gdb_stub_state *)data;
|
||||
int breakpoint;
|
||||
|
||||
|
|
@ -1397,7 +1397,7 @@ static uint32_t FASTCALL gdb_prefetch32( void *data, uint32_t adr) {
|
|||
return 0;
|
||||
}
|
||||
|
||||
static uint16_t FASTCALL gdb_prefetch16( void *data, uint32_t adr) {
|
||||
static uint16_t DESMUME_FASTCALL gdb_prefetch16( void *data, uint32_t adr) {
|
||||
struct gdb_stub_state *stub = (struct gdb_stub_state *)data;
|
||||
int breakpoint;
|
||||
|
||||
|
|
@ -1409,7 +1409,7 @@ static uint16_t FASTCALL gdb_prefetch16( void *data, uint32_t adr) {
|
|||
}
|
||||
|
||||
/** read 8 bit data value */
|
||||
static uint8_t FASTCALL
|
||||
static uint8_t DESMUME_FASTCALL
|
||||
gdb_read8( void *data, uint32_t adr) {
|
||||
struct gdb_stub_state *stub = (struct gdb_stub_state *)data;
|
||||
uint8_t value = 0;
|
||||
|
|
@ -1428,7 +1428,7 @@ gdb_read8( void *data, uint32_t adr) {
|
|||
}
|
||||
|
||||
/** read 16 bit data value */
|
||||
static uint16_t FASTCALL
|
||||
static uint16_t DESMUME_FASTCALL
|
||||
gdb_read16( void *data, uint32_t adr) {
|
||||
struct gdb_stub_state *stub = (struct gdb_stub_state *)data;
|
||||
uint16_t value;
|
||||
|
|
@ -1446,7 +1446,7 @@ gdb_read16( void *data, uint32_t adr) {
|
|||
return value;
|
||||
}
|
||||
/** read 32 bit data value */
|
||||
static uint32_t FASTCALL
|
||||
static uint32_t DESMUME_FASTCALL
|
||||
gdb_read32( void *data, uint32_t adr) {
|
||||
struct gdb_stub_state *stub = (struct gdb_stub_state *)data;
|
||||
uint32_t value;
|
||||
|
|
@ -1465,7 +1465,7 @@ gdb_read32( void *data, uint32_t adr) {
|
|||
}
|
||||
|
||||
/** write 8 bit data value */
|
||||
static void FASTCALL
|
||||
static void DESMUME_FASTCALL
|
||||
gdb_write8( void *data, uint32_t adr, uint8_t val) {
|
||||
struct gdb_stub_state *stub = (struct gdb_stub_state *)data;
|
||||
int breakpoint;
|
||||
|
|
@ -1481,7 +1481,7 @@ gdb_write8( void *data, uint32_t adr, uint8_t val) {
|
|||
}
|
||||
|
||||
/** write 16 bit data value */
|
||||
static void FASTCALL
|
||||
static void DESMUME_FASTCALL
|
||||
gdb_write16( void *data, uint32_t adr, uint16_t val) {
|
||||
struct gdb_stub_state *stub = (struct gdb_stub_state *)data;
|
||||
int breakpoint;
|
||||
|
|
@ -1497,7 +1497,7 @@ gdb_write16( void *data, uint32_t adr, uint16_t val) {
|
|||
}
|
||||
|
||||
/** write 32 bit data value */
|
||||
static void FASTCALL
|
||||
static void DESMUME_FASTCALL
|
||||
gdb_write32( void *data, uint32_t adr, uint32_t val) {
|
||||
struct gdb_stub_state *stub = (struct gdb_stub_state *)data;
|
||||
int breakpoint;
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
|
||||
#include "types.h"
|
||||
|
||||
typedef u32 (FASTCALL* OpFunc)(const u32 i);
|
||||
typedef u32 (DESMUME_FASTCALL* OpFunc)(const u32 i);
|
||||
extern const OpFunc arm_instructions_set[2][4096];
|
||||
extern const char* arm_instruction_names[4096];
|
||||
extern const OpFunc thumb_instructions_set[2][1024];
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@
|
|||
//-----------------------------------------------------------------------------
|
||||
// Undefined instruction
|
||||
//-----------------------------------------------------------------------------
|
||||
TEMPLATE static u32 FASTCALL OP_UND_THUMB(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_UND_THUMB(const u32 i)
|
||||
{
|
||||
INFO("THUMB%c: Undefined instruction: 0x%08X PC=0x%08X\n", cpu->proc_ID?'7':'9', cpu->instruction, cpu->instruct_adr);
|
||||
TRAPUNDEF(cpu);
|
||||
|
|
@ -48,7 +48,7 @@ TEMPLATE static u32 FASTCALL OP_UND_THUMB(const u32 i)
|
|||
// LSL
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSL_0(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LSL_0(const u32 i)
|
||||
{
|
||||
cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)];
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
|
|
@ -57,7 +57,7 @@ TEMPLATE static u32 FASTCALL OP_LSL_0(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSL(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LSL(const u32 i)
|
||||
{
|
||||
u32 v = (i>>6) & 0x1F;
|
||||
cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], 32-v);
|
||||
|
|
@ -68,7 +68,7 @@ TEMPLATE static u32 FASTCALL OP_LSL(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSL_REG(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LSL_REG(const u32 i)
|
||||
{
|
||||
u32 v = cpu->R[REG_NUM(i, 3)] & 0xFF;
|
||||
|
||||
|
|
@ -102,7 +102,7 @@ TEMPLATE static u32 FASTCALL OP_LSL_REG(const u32 i)
|
|||
// LSR
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSR_0(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LSR_0(const u32 i)
|
||||
{
|
||||
cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]);
|
||||
cpu->R[REG_NUM(i, 0)] = 0;
|
||||
|
|
@ -112,7 +112,7 @@ TEMPLATE static u32 FASTCALL OP_LSR_0(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSR(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LSR(const u32 i)
|
||||
{
|
||||
u32 v = (i>>6) & 0x1F;
|
||||
cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], v-1);
|
||||
|
|
@ -123,7 +123,7 @@ TEMPLATE static u32 FASTCALL OP_LSR(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LSR_REG(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LSR_REG(const u32 i)
|
||||
{
|
||||
u32 v = cpu->R[REG_NUM(i, 3)] & 0xFF;
|
||||
|
||||
|
|
@ -156,7 +156,7 @@ TEMPLATE static u32 FASTCALL OP_LSR_REG(const u32 i)
|
|||
// ASR
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ASR_0(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ASR_0(const u32 i)
|
||||
{
|
||||
cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]);
|
||||
cpu->R[REG_NUM(i, 0)] = BIT31(cpu->R[REG_NUM(i, 3)])*0xFFFFFFFF;
|
||||
|
|
@ -166,7 +166,7 @@ TEMPLATE static u32 FASTCALL OP_ASR_0(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ASR(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ASR(const u32 i)
|
||||
{
|
||||
u32 v = (i>>6) & 0x1F;
|
||||
cpu->CPSR.bits.C = BIT_N(cpu->R[REG_NUM(i, 3)], v-1);
|
||||
|
|
@ -177,7 +177,7 @@ TEMPLATE static u32 FASTCALL OP_ASR(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ASR_REG(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ASR_REG(const u32 i)
|
||||
{
|
||||
u32 v = cpu->R[REG_NUM(i, 3)] & 0xFF;
|
||||
|
||||
|
|
@ -208,7 +208,7 @@ TEMPLATE static u32 FASTCALL OP_ASR_REG(const u32 i)
|
|||
// ADD
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_IMM3(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ADD_IMM3(const u32 i)
|
||||
{
|
||||
u32 imm3 = (i >> 6) & 0x07;
|
||||
u32 Rn = cpu->R[REG_NUM(i, 3)];
|
||||
|
|
@ -233,7 +233,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_IMM3(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_IMM8(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ADD_IMM8(const u32 i)
|
||||
{
|
||||
u32 imm8 = (i & 0xFF);
|
||||
u32 Rd = cpu->R[REG_NUM(i, 8)];
|
||||
|
|
@ -247,7 +247,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_IMM8(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_REG(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ADD_REG(const u32 i)
|
||||
{
|
||||
u32 Rn = cpu->R[REG_NUM(i, 3)];
|
||||
u32 Rm = cpu->R[REG_NUM(i, 6)];
|
||||
|
|
@ -261,7 +261,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_REG(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_SPE(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ADD_SPE(const u32 i)
|
||||
{
|
||||
u32 Rd = REG_NUM(i, 0) | ((i>>4)&8);
|
||||
|
||||
|
|
@ -276,14 +276,14 @@ TEMPLATE static u32 FASTCALL OP_ADD_SPE(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_2PC(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ADD_2PC(const u32 i)
|
||||
{
|
||||
cpu->R[REG_NUM(i, 8)] = (cpu->R[15]&0xFFFFFFFC) + ((i&0xFF)<<2);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADD_2SP(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ADD_2SP(const u32 i)
|
||||
{
|
||||
cpu->R[REG_NUM(i, 8)] = cpu->R[13] + ((i&0xFF)<<2);
|
||||
|
||||
|
|
@ -294,7 +294,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_2SP(const u32 i)
|
|||
// SUB
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_SUB_IMM3(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_SUB_IMM3(const u32 i)
|
||||
{
|
||||
u32 imm3 = (i>>6) & 0x07;
|
||||
u32 Rn = cpu->R[REG_NUM(i, 3)];
|
||||
|
|
@ -309,7 +309,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_IMM3(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_SUB_IMM8(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_SUB_IMM8(const u32 i)
|
||||
{
|
||||
u32 imm8 = (i & 0xFF);
|
||||
u32 Rd = cpu->R[REG_NUM(i, 8)];
|
||||
|
|
@ -324,7 +324,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_IMM8(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_SUB_REG(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_SUB_REG(const u32 i)
|
||||
{
|
||||
u32 Rn = cpu->R[REG_NUM(i, 3)];
|
||||
u32 Rm = cpu->R[REG_NUM(i, 6)];
|
||||
|
|
@ -343,7 +343,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_REG(const u32 i)
|
|||
// MOV
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_MOV_IMM8(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_MOV_IMM8(const u32 i)
|
||||
{
|
||||
cpu->R[REG_NUM(i, 8)] = (i & 0xFF);
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 8)]);
|
||||
|
|
@ -352,7 +352,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_IMM8(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_MOV_SPE(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_MOV_SPE(const u32 i)
|
||||
{
|
||||
u32 Rd = REG_NUM(i, 0) | ((i>>4)&8);
|
||||
|
||||
|
|
@ -370,7 +370,7 @@ TEMPLATE static u32 FASTCALL OP_MOV_SPE(const u32 i)
|
|||
//-----------------------------------------------------------------------------
|
||||
// CMP
|
||||
//-----------------------------------------------------------------------------
|
||||
TEMPLATE static u32 FASTCALL OP_CMP_IMM8(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_CMP_IMM8(const u32 i)
|
||||
{
|
||||
u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF);
|
||||
|
||||
|
|
@ -382,7 +382,7 @@ TEMPLATE static u32 FASTCALL OP_CMP_IMM8(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_CMP(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_CMP(const u32 i)
|
||||
{
|
||||
u32 tmp = cpu->R[REG_NUM(i, 0)] - cpu->R[REG_NUM(i, 3)];
|
||||
|
||||
|
|
@ -394,7 +394,7 @@ TEMPLATE static u32 FASTCALL OP_CMP(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_CMP_SPE(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_CMP_SPE(const u32 i)
|
||||
{
|
||||
u32 Rn = (i&7) | ((i>>4)&8);
|
||||
|
||||
|
|
@ -412,7 +412,7 @@ TEMPLATE static u32 FASTCALL OP_CMP_SPE(const u32 i)
|
|||
// AND
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_AND(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_AND(const u32 i)
|
||||
{
|
||||
cpu->R[REG_NUM(i, 0)] &= cpu->R[REG_NUM(i, 3)];
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
|
|
@ -424,7 +424,7 @@ TEMPLATE static u32 FASTCALL OP_AND(const u32 i)
|
|||
// EOR
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_EOR(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_EOR(const u32 i)
|
||||
{
|
||||
cpu->R[REG_NUM(i, 0)] ^= cpu->R[REG_NUM(i, 3)];
|
||||
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
|
||||
|
|
@ -437,7 +437,7 @@ TEMPLATE static u32 FASTCALL OP_EOR(const u32 i)
|
|||
// ADC
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADC_REG(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ADC_REG(const u32 i)
|
||||
{
|
||||
u32 Rd = cpu->R[REG_NUM(i, 0)];
|
||||
u32 Rm = cpu->R[REG_NUM(i, 3)];
|
||||
|
|
@ -462,7 +462,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_REG(const u32 i)
|
|||
//-----------------------------------------------------------------------------
|
||||
// SBC
|
||||
//-----------------------------------------------------------------------------
|
||||
TEMPLATE static u32 FASTCALL OP_SBC_REG(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_SBC_REG(const u32 i)
|
||||
{
|
||||
u32 Rd = cpu->R[REG_NUM(i, 0)];
|
||||
u32 Rm = cpu->R[REG_NUM(i, 3)];
|
||||
|
|
@ -489,7 +489,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_REG(const u32 i)
|
|||
// ROR
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ROR_REG(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ROR_REG(const u32 i)
|
||||
{
|
||||
u32 v = cpu->R[REG_NUM(i, 3)] & 0xFF;
|
||||
|
||||
|
|
@ -520,7 +520,7 @@ TEMPLATE static u32 FASTCALL OP_ROR_REG(const u32 i)
|
|||
// TST
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_TST(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_TST(const u32 i)
|
||||
{
|
||||
u32 tmp = cpu->R[REG_NUM(i, 0)] & cpu->R[REG_NUM(i, 3)];
|
||||
cpu->CPSR.bits.N = BIT31(tmp);
|
||||
|
|
@ -533,7 +533,7 @@ TEMPLATE static u32 FASTCALL OP_TST(const u32 i)
|
|||
// NEG
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_NEG(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_NEG(const u32 i)
|
||||
{
|
||||
u32 Rm = cpu->R[REG_NUM(i, 3)];
|
||||
|
||||
|
|
@ -551,7 +551,7 @@ TEMPLATE static u32 FASTCALL OP_NEG(const u32 i)
|
|||
// CMN
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_CMN(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_CMN(const u32 i)
|
||||
{
|
||||
u32 tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)];
|
||||
|
||||
|
|
@ -567,7 +567,7 @@ TEMPLATE static u32 FASTCALL OP_CMN(const u32 i)
|
|||
// ORR
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ORR(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ORR(const u32 i)
|
||||
{
|
||||
cpu->R[REG_NUM(i, 0)] |= cpu->R[REG_NUM(i, 3)];
|
||||
|
||||
|
|
@ -581,7 +581,7 @@ TEMPLATE static u32 FASTCALL OP_ORR(const u32 i)
|
|||
// BIC
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BIC(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_BIC(const u32 i)
|
||||
{
|
||||
cpu->R[REG_NUM(i, 0)] &= (~cpu->R[REG_NUM(i, 3)]);
|
||||
|
||||
|
|
@ -595,7 +595,7 @@ TEMPLATE static u32 FASTCALL OP_BIC(const u32 i)
|
|||
// MVN
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_MVN(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_MVN(const u32 i)
|
||||
{
|
||||
cpu->R[REG_NUM(i, 0)] = (~cpu->R[REG_NUM(i, 3)]);
|
||||
|
||||
|
|
@ -621,7 +621,7 @@ TEMPLATE static u32 FASTCALL OP_MVN(const u32 i)
|
|||
return c+3; \
|
||||
return c+4; \
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_MUL_REG(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_MUL_REG(const u32 i)
|
||||
{
|
||||
u32 v = cpu->R[REG_NUM(i, 3)];
|
||||
|
||||
|
|
@ -648,7 +648,7 @@ TEMPLATE static u32 FASTCALL OP_MUL_REG(const u32 i)
|
|||
// STRB / LDRB
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STRB_IMM_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_STRB_IMM_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
|
||||
WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_NUM(i, 0)]);
|
||||
|
|
@ -656,7 +656,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_IMM_OFF(const u32 i)
|
|||
return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2, adr);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRB_IMM_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LDRB_IMM_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
|
||||
cpu->R[REG_NUM(i, 0)] = (u32)READ8(cpu->mem_if->data, adr);
|
||||
|
|
@ -665,7 +665,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_IMM_OFF(const u32 i)
|
|||
}
|
||||
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STRB_REG_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_STRB_REG_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
WRITE8(cpu->mem_if->data, adr, (u8)cpu->R[REG_NUM(i, 0)]);
|
||||
|
|
@ -673,7 +673,7 @@ TEMPLATE static u32 FASTCALL OP_STRB_REG_OFF(const u32 i)
|
|||
return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2, adr);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRB_REG_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LDRB_REG_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
cpu->R[REG_NUM(i, 0)] = (u32)READ8(cpu->mem_if->data, adr);
|
||||
|
|
@ -685,7 +685,7 @@ TEMPLATE static u32 FASTCALL OP_LDRB_REG_OFF(const u32 i)
|
|||
// LDRSB
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRSB_REG_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LDRSB_REG_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
cpu->R[REG_NUM(i, 0)] = (u32)((s8)READ8(cpu->mem_if->data, adr));
|
||||
|
|
@ -697,7 +697,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSB_REG_OFF(const u32 i)
|
|||
// STRH / LDRH
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STRH_IMM_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_STRH_IMM_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
|
||||
WRITE16(cpu->mem_if->data, adr, (u16)cpu->R[REG_NUM(i, 0)]);
|
||||
|
|
@ -705,7 +705,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_IMM_OFF(const u32 i)
|
|||
return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2, adr);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRH_IMM_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LDRH_IMM_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
|
||||
cpu->R[REG_NUM(i, 0)] = (u32)READ16(cpu->mem_if->data, adr);
|
||||
|
|
@ -714,7 +714,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_IMM_OFF(const u32 i)
|
|||
}
|
||||
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STRH_REG_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_STRH_REG_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
WRITE16(cpu->mem_if->data, adr, ((u16)cpu->R[REG_NUM(i, 0)]));
|
||||
|
|
@ -722,7 +722,7 @@ TEMPLATE static u32 FASTCALL OP_STRH_REG_OFF(const u32 i)
|
|||
return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2, adr);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRH_REG_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LDRH_REG_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
cpu->R[REG_NUM(i, 0)] = (u32)READ16(cpu->mem_if->data, adr);
|
||||
|
|
@ -734,7 +734,7 @@ TEMPLATE static u32 FASTCALL OP_LDRH_REG_OFF(const u32 i)
|
|||
// LDRSH
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDRSH_REG_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LDRSH_REG_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
|
||||
cpu->R[REG_NUM(i, 0)] = (u32)((s16)READ16(cpu->mem_if->data, adr));
|
||||
|
|
@ -746,7 +746,7 @@ TEMPLATE static u32 FASTCALL OP_LDRSH_REG_OFF(const u32 i)
|
|||
// STR / LDR
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STR_IMM_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_STR_IMM_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
|
||||
WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]);
|
||||
|
|
@ -754,7 +754,7 @@ TEMPLATE static u32 FASTCALL OP_STR_IMM_OFF(const u32 i)
|
|||
return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2, adr);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_IMM_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LDR_IMM_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
|
||||
u32 tempValue = READ32(cpu->mem_if->data, adr);
|
||||
|
|
@ -766,7 +766,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_IMM_OFF(const u32 i)
|
|||
}
|
||||
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STR_REG_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_STR_REG_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 6)] + cpu->R[REG_NUM(i, 3)];
|
||||
WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 0)]);
|
||||
|
|
@ -774,7 +774,7 @@ TEMPLATE static u32 FASTCALL OP_STR_REG_OFF(const u32 i)
|
|||
return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2, adr);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_REG_OFF(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LDR_REG_OFF(const u32 i)
|
||||
{
|
||||
u32 adr = (cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]);
|
||||
u32 tempValue = READ32(cpu->mem_if->data, adr);
|
||||
|
|
@ -785,7 +785,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_REG_OFF(const u32 i)
|
|||
return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(3, adr);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STR_SPREL(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_STR_SPREL(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[13] + ((i&0xFF)<<2);
|
||||
WRITE32(cpu->mem_if->data, adr, cpu->R[REG_NUM(i, 8)]);
|
||||
|
|
@ -793,7 +793,7 @@ TEMPLATE static u32 FASTCALL OP_STR_SPREL(const u32 i)
|
|||
return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2, adr);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_SPREL(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LDR_SPREL(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[13] + ((i&0xFF)<<2);
|
||||
cpu->R[REG_NUM(i, 8)] = READ32(cpu->mem_if->data, adr);
|
||||
|
|
@ -801,7 +801,7 @@ TEMPLATE static u32 FASTCALL OP_LDR_SPREL(const u32 i)
|
|||
return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_READ>(3, adr);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDR_PCREL(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LDR_PCREL(const u32 i)
|
||||
{
|
||||
u32 adr = (cpu->R[15]&0xFFFFFFFC) + ((i&0xFF)<<2);
|
||||
|
||||
|
|
@ -814,14 +814,14 @@ TEMPLATE static u32 FASTCALL OP_LDR_PCREL(const u32 i)
|
|||
// Adjust SP
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADJUST_P_SP(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ADJUST_P_SP(const u32 i)
|
||||
{
|
||||
cpu->R[13] += ((i&0x7F)<<2);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_ADJUST_M_SP(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_ADJUST_M_SP(const u32 i)
|
||||
{
|
||||
cpu->R[13] -= ((i&0x7F)<<2);
|
||||
|
||||
|
|
@ -832,7 +832,7 @@ TEMPLATE static u32 FASTCALL OP_ADJUST_M_SP(const u32 i)
|
|||
// PUSH / POP
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_PUSH(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_PUSH(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[13] - 4;
|
||||
u32 c = 0, j;
|
||||
|
|
@ -849,7 +849,7 @@ TEMPLATE static u32 FASTCALL OP_PUSH(const u32 i)
|
|||
return MMU_aluMemCycles<PROCNUM>(3, c);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_PUSH_LR(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_PUSH_LR(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[13] - 4;
|
||||
u32 c = 0, j;
|
||||
|
|
@ -870,7 +870,7 @@ TEMPLATE static u32 FASTCALL OP_PUSH_LR(const u32 i)
|
|||
return MMU_aluMemCycles<PROCNUM>(4, c);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_POP(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_POP(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[13];
|
||||
u32 c = 0, j;
|
||||
|
|
@ -894,7 +894,7 @@ TEMPLATE static u32 FASTCALL OP_POP(const u32 i)
|
|||
// In T variants of ARMv4, bit[0] of the loaded value is ignored and execution continues in Thumb state, as
|
||||
// though the following instruction had been executed:
|
||||
// MOV PC,(loaded_value)
|
||||
TEMPLATE static u32 FASTCALL OP_POP_PC(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_POP_PC(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[13];
|
||||
u32 c = 0, j;
|
||||
|
|
@ -924,7 +924,7 @@ TEMPLATE static u32 FASTCALL OP_POP_PC(const u32 i)
|
|||
// STMIA / LDMIA
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_STMIA_THUMB(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_STMIA_THUMB(const u32 i)
|
||||
{
|
||||
u32 adr = cpu->R[REG_NUM(i, 8)];
|
||||
u32 c = 0, j;
|
||||
|
|
@ -955,7 +955,7 @@ TEMPLATE static u32 FASTCALL OP_STMIA_THUMB(const u32 i)
|
|||
return MMU_aluMemCycles<PROCNUM>(2, c);
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_LDMIA_THUMB(const u32 i)
|
||||
{
|
||||
u32 regIndex = REG_NUM(i, 8);
|
||||
u32 adr = cpu->R[regIndex];
|
||||
|
|
@ -992,7 +992,7 @@ TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB(const u32 i)
|
|||
// BKPT
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BKPT_THUMB(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_BKPT_THUMB(const u32 i)
|
||||
{
|
||||
printf("THUMB%c: OP_BKPT triggered\n", PROCNUM?'7':'9');
|
||||
Status_Reg tmp = cpu->CPSR;
|
||||
|
|
@ -1011,7 +1011,7 @@ TEMPLATE static u32 FASTCALL OP_BKPT_THUMB(const u32 i)
|
|||
// SWI
|
||||
//-----------------------------------------------------------------------------
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_SWI_THUMB(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_SWI_THUMB(const u32 i)
|
||||
{
|
||||
u32 swinum = i & 0xFF;
|
||||
|
||||
|
|
@ -1060,7 +1060,7 @@ TEMPLATE static u32 FASTCALL OP_SWI_THUMB(const u32 i)
|
|||
#define SIGNEEXT_IMM11(i) (((i)&0x7FF) | (BIT10(i) * 0xFFFFF800))
|
||||
#define SIGNEXTEND_11(i) (((s32)i<<21)>>21)
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_B_COND(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_B_COND(const u32 i)
|
||||
{
|
||||
if(!TEST_COND((i>>8)&0xF, 0, cpu->CPSR))
|
||||
return 1;
|
||||
|
|
@ -1070,7 +1070,7 @@ TEMPLATE static u32 FASTCALL OP_B_COND(const u32 i)
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_B_UNCOND(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_B_UNCOND(const u32 i)
|
||||
{
|
||||
//nocash message detection
|
||||
const u16 last = _MMU_read16<PROCNUM,MMU_AT_DEBUG>(cpu->instruct_adr-2);
|
||||
|
|
@ -1086,7 +1086,7 @@ TEMPLATE static u32 FASTCALL OP_B_UNCOND(const u32 i)
|
|||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BLX(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_BLX(const u32 i)
|
||||
{
|
||||
cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1))&0xFFFFFFFC;
|
||||
cpu->R[14] = cpu->next_instruction | 1;
|
||||
|
|
@ -1095,13 +1095,13 @@ TEMPLATE static u32 FASTCALL OP_BLX(const u32 i)
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BL_10(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_BL_10(const u32 i)
|
||||
{
|
||||
cpu->R[14] = cpu->R[15] + (SIGNEXTEND_11(i)<<12);
|
||||
return 1;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BL_11(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_BL_11(const u32 i)
|
||||
{
|
||||
cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1));
|
||||
cpu->R[14] = cpu->next_instruction | 1;
|
||||
|
|
@ -1109,7 +1109,7 @@ TEMPLATE static u32 FASTCALL OP_BL_11(const u32 i)
|
|||
return 4;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BX_THUMB(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_BX_THUMB(const u32 i)
|
||||
{
|
||||
// When using PC as operand with BX opcode, switch to ARM state and jump to (instruct_adr+4)
|
||||
// Reference: http://nocash.emubase.de/gbatek.htm#thumb5hiregisteroperationsbranchexchange
|
||||
|
|
@ -1149,7 +1149,7 @@ TEMPLATE static u32 FASTCALL OP_BX_THUMB(const u32 i)
|
|||
return 3;
|
||||
}
|
||||
|
||||
TEMPLATE static u32 FASTCALL OP_BLX_THUMB(const u32 i)
|
||||
TEMPLATE static u32 DESMUME_FASTCALL OP_BLX_THUMB(const u32 i)
|
||||
{
|
||||
u32 Rm = cpu->R[REG_POS(i, 3)];
|
||||
cpu->CPSR.bits.T = BIT0(Rm);
|
||||
|
|
|
|||
|
|
@ -178,16 +178,16 @@
|
|||
//---------------------------------------------
|
||||
|
||||
#ifdef __MINGW32__
|
||||
#define FASTCALL __attribute__((fastcall))
|
||||
#define DESMUME_FASTCALL __attribute__((fastcall))
|
||||
#define ASMJIT_CALL_CONV kX86FuncConvGccFastCall
|
||||
#elif defined (__i386__) && !defined(__clang__)
|
||||
#define FASTCALL __attribute__((regparm(3)))
|
||||
#define DESMUME_FASTCALL __attribute__((regparm(3)))
|
||||
#define ASMJIT_CALL_CONV kX86FuncConvGccRegParm3
|
||||
#elif defined(_MSC_VER) || defined(__INTEL_COMPILER)
|
||||
#define FASTCALL
|
||||
#define DESMUME_FASTCALL
|
||||
#define ASMJIT_CALL_CONV kX86FuncConvDefault
|
||||
#else
|
||||
#define FASTCALL
|
||||
#define DESMUME_FASTCALL
|
||||
#define ASMJIT_CALL_CONV kX86FuncConvDefault
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -388,7 +388,7 @@ static void _armlog(u8 proc, u32 addr, u32 opcode);
|
|||
//-----------------------------------------------------------------------------
|
||||
|
||||
template<int PROCNUM, int thumb>
|
||||
static u32 FASTCALL OP_DECODE()
|
||||
static u32 DESMUME_FASTCALL OP_DECODE()
|
||||
{
|
||||
u32 cycles;
|
||||
u32 adr = cpu->instruct_adr;
|
||||
|
|
@ -1442,7 +1442,7 @@ static int OP_MSR_SPSR_IMM_VAL(const u32 i) { OP_MSR_(SPSR, IMM_VAL, 0); }
|
|||
//-----------------------------------------------------------------------------
|
||||
// LDR
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef u32 (FASTCALL* OpLDR)(u32, u32*);
|
||||
typedef u32 (DESMUME_FASTCALL* OpLDR)(u32, u32*);
|
||||
|
||||
// 98% of all memory accesses land in the same region as the first execution of
|
||||
// that instruction, so keep multiple copies with different fastpaths.
|
||||
|
|
@ -1473,7 +1473,7 @@ static u32 classify_adr(u32 adr, bool store)
|
|||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_LDR(u32 adr, u32 *dstreg)
|
||||
static u32 DESMUME_FASTCALL OP_LDR(u32 adr, u32 *dstreg)
|
||||
{
|
||||
u32 data = READ32(cpu->mem_if->data, adr);
|
||||
if(adr&3)
|
||||
|
|
@ -1483,21 +1483,21 @@ static u32 FASTCALL OP_LDR(u32 adr, u32 *dstreg)
|
|||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_LDRH(u32 adr, u32 *dstreg)
|
||||
static u32 DESMUME_FASTCALL OP_LDRH(u32 adr, u32 *dstreg)
|
||||
{
|
||||
*dstreg = READ16(cpu->mem_if->data, adr);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
|
||||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_LDRSH(u32 adr, u32 *dstreg)
|
||||
static u32 DESMUME_FASTCALL OP_LDRSH(u32 adr, u32 *dstreg)
|
||||
{
|
||||
*dstreg = (s16)READ16(cpu->mem_if->data, adr);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_READ>(3,adr);
|
||||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_LDRB(u32 adr, u32 *dstreg)
|
||||
static u32 DESMUME_FASTCALL OP_LDRB(u32 adr, u32 *dstreg)
|
||||
{
|
||||
*dstreg = READ8(cpu->mem_if->data, adr);
|
||||
u32 ret = MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
|
||||
|
|
@ -1505,7 +1505,7 @@ static u32 FASTCALL OP_LDRB(u32 adr, u32 *dstreg)
|
|||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_LDRSB(u32 adr, u32 *dstreg)
|
||||
static u32 DESMUME_FASTCALL OP_LDRSB(u32 adr, u32 *dstreg)
|
||||
{
|
||||
*dstreg = (s8)READ8(cpu->mem_if->data, adr);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_READ>(3,adr);
|
||||
|
|
@ -1688,27 +1688,27 @@ static int OP_LDRSB_POS_INDE_M_REG_OFF(const u32 i) { OP_LDR_(LDRSB, REG_OFF, su
|
|||
// STR
|
||||
//-----------------------------------------------------------------------------
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_STR(u32 adr, u32 data)
|
||||
static u32 DESMUME_FASTCALL OP_STR(u32 adr, u32 data)
|
||||
{
|
||||
WRITE32(cpu->mem_if->data, adr, data);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,32,MMU_AD_WRITE>(2,adr);
|
||||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_STRH(u32 adr, u32 data)
|
||||
static u32 DESMUME_FASTCALL OP_STRH(u32 adr, u32 data)
|
||||
{
|
||||
WRITE16(cpu->mem_if->data, adr, data);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,16,MMU_AD_WRITE>(2,adr);
|
||||
}
|
||||
|
||||
template<int PROCNUM, int memtype>
|
||||
static u32 FASTCALL OP_STRB(u32 adr, u32 data)
|
||||
static u32 DESMUME_FASTCALL OP_STRB(u32 adr, u32 data)
|
||||
{
|
||||
WRITE8(cpu->mem_if->data, adr, data);
|
||||
return MMU_aluMemAccessCycles<PROCNUM,8,MMU_AD_WRITE>(2,adr);
|
||||
}
|
||||
|
||||
typedef u32 (FASTCALL* OpSTR)(u32, u32);
|
||||
typedef u32 (DESMUME_FASTCALL* OpSTR)(u32, u32);
|
||||
#define T(op) op<0,0>, op<0,1>, op<0,2>, op<1,0>, op<1,1>, NULL
|
||||
static const OpSTR STR_tab[2][3] = { T(OP_STR) };
|
||||
static const OpSTR STRH_tab[2][3] = { T(OP_STRH) };
|
||||
|
|
@ -1829,9 +1829,9 @@ static int OP_STRB_M_ROR_IMM_OFF_POSTIND(const u32 i) { OP_STR_(STRB, ROR_IMM, s
|
|||
//-----------------------------------------------------------------------------
|
||||
// LDRD / STRD
|
||||
//-----------------------------------------------------------------------------
|
||||
typedef u32 FASTCALL (*LDRD_STRD_REG)(u32);
|
||||
typedef u32 DESMUME_FASTCALL (*LDRD_STRD_REG)(u32);
|
||||
template<int PROCNUM, u8 Rnum>
|
||||
static u32 FASTCALL OP_LDRD_REG(u32 adr)
|
||||
static u32 DESMUME_FASTCALL OP_LDRD_REG(u32 adr)
|
||||
{
|
||||
cpu->R[Rnum] = READ32(cpu->mem_if->data, adr);
|
||||
|
||||
|
|
@ -1845,7 +1845,7 @@ static u32 FASTCALL OP_LDRD_REG(u32 adr)
|
|||
return MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(adr);
|
||||
}
|
||||
template<int PROCNUM, u8 Rnum>
|
||||
static u32 FASTCALL OP_STRD_REG(u32 adr)
|
||||
static u32 DESMUME_FASTCALL OP_STRD_REG(u32 adr)
|
||||
{
|
||||
WRITE32(cpu->mem_if->data, adr, cpu->R[Rnum]);
|
||||
|
||||
|
|
@ -1992,7 +1992,7 @@ static int OP_LDRD_STRD_OFFSET_PRE_INDEX(const u32 i)
|
|||
// SWP/SWPB
|
||||
//-----------------------------------------------------------------------------
|
||||
template<int PROCNUM>
|
||||
static u32 FASTCALL op_swp(u32 adr, u32 *Rd, u32 Rs)
|
||||
static u32 DESMUME_FASTCALL op_swp(u32 adr, u32 *Rd, u32 Rs)
|
||||
{
|
||||
u32 tmpt = ROR(READ32(cpu->mem_if->data, adr), (adr & 3)<<3);
|
||||
WRITE32(cpu->mem_if->data, adr, Rs);
|
||||
|
|
@ -2000,7 +2000,7 @@ static u32 FASTCALL op_swp(u32 adr, u32 *Rd, u32 Rs)
|
|||
return (MMU_memAccessCycles<PROCNUM,32,MMU_AD_READ>(adr) + MMU_memAccessCycles<PROCNUM,32,MMU_AD_WRITE>(adr));
|
||||
}
|
||||
template<int PROCNUM>
|
||||
static u32 FASTCALL op_swpb(u32 adr, u32 *Rd, u32 Rs)
|
||||
static u32 DESMUME_FASTCALL op_swpb(u32 adr, u32 *Rd, u32 Rs)
|
||||
{
|
||||
u32 tmpt = READ8(cpu->mem_if->data, adr);
|
||||
WRITE8(cpu->mem_if->data, adr, Rs);
|
||||
|
|
@ -2008,7 +2008,7 @@ static u32 FASTCALL op_swpb(u32 adr, u32 *Rd, u32 Rs)
|
|||
return (MMU_memAccessCycles<PROCNUM,8,MMU_AD_READ>(adr) + MMU_memAccessCycles<PROCNUM,8,MMU_AD_WRITE>(adr));
|
||||
}
|
||||
|
||||
typedef u32 FASTCALL (*OP_SWP_SWPB)(u32, u32*, u32);
|
||||
typedef u32 DESMUME_FASTCALL (*OP_SWP_SWPB)(u32, u32*, u32);
|
||||
static const OP_SWP_SWPB op_swp_tab[2][2] = {{ op_swp<0>, op_swp<1> }, { op_swpb<0>, op_swpb<1> }};
|
||||
|
||||
static int op_swp_(const u32 i, int b)
|
||||
|
|
@ -2083,7 +2083,7 @@ static u64 get_reg_list(u32 reg_mask, int dir)
|
|||
#endif
|
||||
|
||||
template <int PROCNUM, bool store, int dir>
|
||||
static LDM_INLINE FASTCALL u32 OP_LDM_STM_generic(u32 adr, u64 regs, int n)
|
||||
static LDM_INLINE DESMUME_FASTCALL u32 OP_LDM_STM_generic(u32 adr, u64 regs, int n)
|
||||
{
|
||||
u32 cycles = 0;
|
||||
adr &= ~3;
|
||||
|
|
@ -2104,7 +2104,7 @@ static LDM_INLINE FASTCALL u32 OP_LDM_STM_generic(u32 adr, u64 regs, int n)
|
|||
#endif
|
||||
|
||||
template <int PROCNUM, bool store, int dir>
|
||||
static LDM_INLINE FASTCALL u32 OP_LDM_STM_other(u32 adr, u64 regs, int n)
|
||||
static LDM_INLINE DESMUME_FASTCALL u32 OP_LDM_STM_other(u32 adr, u64 regs, int n)
|
||||
{
|
||||
u32 cycles = 0;
|
||||
adr &= ~3;
|
||||
|
|
@ -2126,7 +2126,7 @@ static LDM_INLINE FASTCALL u32 OP_LDM_STM_other(u32 adr, u64 regs, int n)
|
|||
}
|
||||
|
||||
template <int PROCNUM, bool store, int dir, bool null_compiled>
|
||||
static FORCEINLINE FASTCALL u32 OP_LDM_STM_main(u32 adr, u64 regs, int n, u8 *ptr, u32 cycles)
|
||||
static FORCEINLINE DESMUME_FASTCALL u32 OP_LDM_STM_main(u32 adr, u64 regs, int n, u8 *ptr, u32 cycles)
|
||||
{
|
||||
#ifdef ENABLE_ADVANCED_TIMING
|
||||
cycles = 0;
|
||||
|
|
@ -2165,7 +2165,7 @@ static FORCEINLINE FASTCALL u32 OP_LDM_STM_main(u32 adr, u64 regs, int n, u8 *pt
|
|||
}
|
||||
|
||||
template <int PROCNUM, bool store, int dir>
|
||||
static u32 FASTCALL OP_LDM_STM(u32 adr, u32 regslo, u32 regshi, int n)
|
||||
static u32 DESMUME_FASTCALL OP_LDM_STM(u32 adr, u32 regslo, u32 regshi, int n)
|
||||
{
|
||||
// TODO use classify_adr?
|
||||
u32 cycles;
|
||||
|
|
@ -2207,7 +2207,7 @@ static u32 FASTCALL OP_LDM_STM(u32 adr, u32 regslo, u32 regshi, int n)
|
|||
return OP_LDM_STM_main<PROCNUM, store, dir, store>(adr, regs, n, ptr, cycles);
|
||||
}
|
||||
|
||||
typedef u32 FASTCALL (*LDMOpFunc)(u32,u32,u32,int);
|
||||
typedef u32 DESMUME_FASTCALL (*LDMOpFunc)(u32,u32,u32,int);
|
||||
static const LDMOpFunc op_ldm_stm_tab[2][2][2] = {{
|
||||
{ OP_LDM_STM<0,0,-1>, OP_LDM_STM<0,0,+1> },
|
||||
{ OP_LDM_STM<0,1,-1>, OP_LDM_STM<0,1,+1> },
|
||||
|
|
|
|||
Loading…
Reference in New Issue