fix new linux compile issues and use more symbolic constants instead of magic numbers

desmume/src/FIFO.cpp

@@ -121,17 +121,6 @@ u32 IPC_FIFOrecv(u8 proc)
 	return (val);
 }
 
-#define IPCFIFOCNT_SENDEMPTY 0x0001
-#define IPCFIFOCNT_SENDFULL 0x0002
-#define IPCFIFOCNT_SENDIRQEN 0x0004
-#define IPCFIFOCNT_SENDCLEAR 0x0008
-#define IPCFIFOCNT_RECVEMPTY 0x0100
-#define IPCFIFOCNT_RECVFULL 0x0200
-#define IPCFIFOCNT_RECVIRQEN 0x0400
-#define IPCFIFOCNT_FIFOERROR 0x4000
-#define IPCFIFOCNT_FIFOENABLE 0x8000
-#define IPCFIFOCNT_WRITEABLE (IPCFIFOCNT_SENDIRQEN | IPCFIFOCNT_RECVIRQEN | IPCFIFOCNT_FIFOENABLE)
-
 void IPC_FIFOcnt(u8 proc, u16 val)
 {
 	u16 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184);

desmume/src/MMU.cpp

@@ -1271,11 +1271,11 @@ u32 MMU_struct::gen_IF()
 			break;
 		case 1: //less than half full
 			if(gxFIFO.size <= 127) 
-				IF |= (1<<21);
+				IF |= IRQ_MASK_ARM9_GXFIFO;
 			break;
 		case 2: //empty
 			if(gxFIFO.size == 0) 
-				IF |= (1<<21);
+				IF |= IRQ_MASK_ARM9_GXFIFO;
 			break;
 		case 3: //reserved/unknown
 			break;
@@ -1284,31 +1284,14 @@ u32 MMU_struct::gen_IF()
 
 	//generate IPC IF states from the ipc registers
 	u16 ipc = T1ReadWord(MMU.MMU_MEM[PROCNUM][0x40], 0x184);
-	if(ipc&0x8000)
+	if(ipc&IPCFIFOCNT_FIFOENABLE)
 	{
-		if(ipc&0x0004) if(ipc&0x0001) 
+		if(ipc&IPCFIFOCNT_SENDIRQEN) if(ipc&IPCFIFOCNT_SENDEMPTY) 
-			IF |= (1<<17); //IPC Send FIFO Empty
+			IF |= IRQ_MASK_IPCFIFO_SENDEMPTY;
-		if(ipc&0x0400) if(!(ipc&0x0100))
+		if(ipc&IPCFIFOCNT_RECVIRQEN) if(!(ipc&IPCFIFOCNT_RECVEMPTY))
-			IF |= (1<<18); //IPC Recv FIFO Not Empty
+			IF |= IRQ_MASK_IPCFIFO_RECVNONEMPTY;
 	}
 
-	//4000184h - NDS9/NDS7 - IPCFIFOCNT - IPC Fifo Control Register (R/W)
-	//
-	//  Bit   Dir  Expl.
-	//  0     R    Send Fifo Empty Status      (0=Not Empty, 1=Empty)
-	//  1     R    Send Fifo Full Status       (0=Not Full, 1=Full)
-	//  2     R/W  Send Fifo Empty IRQ         (0=Disable, 1=Enable)
-	//  3     W    Send Fifo Clear             (0=Nothing, 1=Flush Send Fifo)
-	//  4-7   -    Not used
-	//  8     R    Receive Fifo Empty          (0=Not Empty, 1=Empty)
-	//  9     R    Receive Fifo Full           (0=Not Full, 1=Full)
-	//  10    R/W  Receive Fifo Not Empty IRQ  (0=Disable, 1=Enable)
-	//  11-13 -    Not used
-	//  14    R/W  Error, Read Empty/Send Full (0=No Error, 1=Error/Acknowledge)
-	//  15    R/W  Enable Send/Receive Fifo    (0=Disable, 1=Enable)
-	//  16-31 -    Not used
-
-
 	return IF;
 }
 
@@ -2212,6 +2195,11 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
 				writereg_POWCNT1(8,adr,val);
 				break;
 
+			case REG_IF: REG_IF_WriteByte<ARMCPU_ARM9>(0,val); break;
+			case REG_IF+1: REG_IF_WriteByte<ARMCPU_ARM9>(1,val); break;
+			case REG_IF+2: REG_IF_WriteByte<ARMCPU_ARM9>(2,val); break;
+			case REG_IF+3: REG_IF_WriteByte<ARMCPU_ARM9>(3,val); break;
+
 			case eng_3D_CLEAR_COLOR+0: case eng_3D_CLEAR_COLOR+1:
 			case eng_3D_CLEAR_COLOR+2: case eng_3D_CLEAR_COLOR+3:
 				T1WriteByte((u8*)&gfx3d.state.clearColor,adr-eng_3D_CLEAR_COLOR,val); 
@@ -2627,12 +2615,8 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
 				NDS_Reschedule();
 				MMU.reg_IE[ARMCPU_ARM9] = (MMU.reg_IE[ARMCPU_ARM9]&0xFFFF) | (((u32)val)<<16);
 				return;
-			case REG_IF :
+			case REG_IF: REG_IF_WriteWord<ARMCPU_ARM9>(0,val); return;
-				REG_IF_WriteWord<ARMCPU_ARM9>(0,val);
+			case REG_IF+2: REG_IF_WriteWord<ARMCPU_ARM9>(2,val); return;
-				return;
-			case REG_IF + 2 :
-				REG_IF_WriteWord<ARMCPU_ARM9>(2,val);
-				return;
 
             case REG_IPCSYNC :
 					MMU_IPCSync(ARMCPU_ARM9, val);
@@ -3042,9 +3026,7 @@ void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
 				MMU.reg_IE[ARMCPU_ARM9] = val;
 				return;
 			
-			case REG_IF :
+			case REG_IF: REG_IF_WriteLong<ARMCPU_ARM9>(val); return;
-				REG_IF_WriteLong<ARMCPU_ARM9>(val);
-				return;
 
             case REG_TM0CNTL:
             case REG_TM1CNTL:
@@ -3486,6 +3468,11 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
 
 		switch(adr)
 		{
+			case REG_IF: REG_IF_WriteByte<ARMCPU_ARM7>(0,val); break;
+			case REG_IF+1: REG_IF_WriteByte<ARMCPU_ARM7>(1,val); break;
+			case REG_IF+2: REG_IF_WriteByte<ARMCPU_ARM7>(2,val); break;
+			case REG_IF+3: REG_IF_WriteByte<ARMCPU_ARM7>(3,val); break;
+
 			case REG_POSTFLG:
 				// hack for patched firmwares
 				if (val == 1)
@@ -3791,13 +3778,8 @@ void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
 				MMU.reg_IE[ARMCPU_ARM7] = (MMU.reg_IE[ARMCPU_ARM7]&0xFFFF) | (((u32)val)<<16);
 				return;
 				
-			case REG_IF:
+			case REG_IF: REG_IF_WriteWord<ARMCPU_ARM7>(0,val); return;
-				REG_IF_WriteWord<ARMCPU_ARM7>(0,val);
+			case REG_IF+2: REG_IF_WriteWord<ARMCPU_ARM7>(2,val); return;
-				return;
-			
-			case REG_IF+2:
-				REG_IF_WriteWord<ARMCPU_ARM7>(2,val);
-				return;
 				
             case REG_IPCSYNC :
 				MMU_IPCSync(ARMCPU_ARM7, val);
@@ -3885,9 +3867,7 @@ void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
 				MMU.reg_IE[ARMCPU_ARM7] = val;
 				return;
 			
-			case REG_IF :
+			case REG_IF: REG_IF_WriteLong<ARMCPU_ARM7>(val); return;
-				REG_IF_WriteLong<ARMCPU_ARM7>(val);
-				return;
 
             case REG_TM0CNTL:
             case REG_TM1CNTL:
@@ -3972,7 +3952,15 @@ u8 FASTCALL _MMU_ARM7_read08(u32 adr)
 		if(MMU_new.is_dma(adr)) return MMU_new.read_dma(ARMCPU_ARM7,8,adr); 
 
 		// Address is an IO register
-		//switch(adr) {}
+
+		switch(adr)
+		{
+			case REG_IF: return MMU.gen_IF<ARMCPU_ARM7>();
+			case REG_IF+1: return (MMU.gen_IF<ARMCPU_ARM7>()>>8);
+			case REG_IF+2: return (MMU.gen_IF<ARMCPU_ARM7>()>>16);
+			case REG_IF+3: return (MMU.gen_IF<ARMCPU_ARM7>()>>24);
+		}
+
 		return MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]];
 	}
 
@@ -4215,6 +4203,11 @@ void FASTCALL MMU_DumpMemBlock(u8 proc, u32 address, u32 size, u8 *buffer)
 	}
 }
 
+
+//these templates needed to be instantiated manually
+template u32 MMU_struct::gen_IF<ARMCPU_ARM9>();
+template u32 MMU_struct::gen_IF<ARMCPU_ARM7>();
+
 ////////////////////////////////////////////////////////////
 //function pointer handlers for gdb stub stuff
 

desmume/src/gtk/tools/ioregsView.cpp

@@ -156,14 +156,14 @@ static void crea_REG_IF(int c)
 static void updt_REG_IF(int c)
 {
 	int i;
-	for(i = 0; i < 24; i++) { INTERRUPT_SKIP(c); gtk_toggle_button_set_active(GTK_TOGGLE_BUTTON(Widgets_REG_IF[c][i]), (MMU.reg_IF[c] & (1<<i)) ? 1 : 0); }
+	for(i = 0; i < 24; i++) { INTERRUPT_SKIP(c); gtk_toggle_button_set_active(GTK_TOGGLE_BUTTON(Widgets_REG_IF[c][i]), ((c==0?MMU.gen_IF<0>():MMU.gen_IF<1>()) & (1<<i)) ? 1 : 0); }
 }
 static void dest_REG_IF(int c)
 {
 	int i;
 	for(i = 0; i < 24; i++) { INTERRUPT_SKIP(c); gtk_widget_destroy(Widgets_REG_IF[c][i]); }
 }
-static u32 val_REG_IF(int c) { return MMU.reg_IF[c]; }
+static u32 val_REG_IF(int c) { return (c==0?MMU.gen_IF<0>():MMU.gen_IF<1>()); }
 
 /////////////////////////////// REG_IPCFIFOCNT ///////////////////////////////
 static const char *fifocnt_strings[] =

desmume/src/registers.h

@@ -346,6 +346,65 @@
 #define eng_3D_VEC_RESULT      0x04000630
 #define eng_3D_CLIPMTX_RESULT  0x04000640
 #define eng_3D_VECMTX_RESULT   0x04000680
-  
+
+#define IPCFIFOCNT_SENDEMPTY 0x0001
+#define IPCFIFOCNT_SENDFULL 0x0002
+#define IPCFIFOCNT_SENDIRQEN 0x0004
+#define IPCFIFOCNT_SENDCLEAR 0x0008
+#define IPCFIFOCNT_RECVEMPTY 0x0100
+#define IPCFIFOCNT_RECVFULL 0x0200
+#define IPCFIFOCNT_RECVIRQEN 0x0400
+#define IPCFIFOCNT_FIFOERROR 0x4000
+#define IPCFIFOCNT_FIFOENABLE 0x8000
+#define IPCFIFOCNT_WRITEABLE (IPCFIFOCNT_SENDIRQEN | IPCFIFOCNT_RECVIRQEN | IPCFIFOCNT_FIFOENABLE)
+
+#define IRQ_BIT_LCD_VBLANK 0
+#define IRQ_BIT_LCD_HBLANK 1
+#define IRQ_BIT_LCD_VMATCH 2
+#define IRQ_BIT_TIMER_0 3
+#define IRQ_BIT_TIMER_1 4
+#define IRQ_BIT_TIMER_2 5
+#define IRQ_BIT_TIMER_3 6
+#define IRQ_BIT_ARM7_SIO 7
+#define IRQ_BIT_DMA_0 8
+#define IRQ_BIT_DMA_2 9
+#define IRQ_BIT_DMA_3 10
+#define IRQ_BIT_DMA_4 11
+#define IRQ_BIT_KEYPAD 12
+#define IRQ_BIT_GAMEPAK 13
+#define IRQ_BIT_IPCSYNC 16
+#define IRQ_BIT_IPCFIFO_SENDEMPTY 17
+#define IRQ_BIT_IPCFIFO_RECVNONEMPTY 18
+#define IRQ_BIT_GC_TRANSFER_COMPLETE 19
+#define IRQ_BIT_GC_IREQ_MC 20
+#define IRQ_BIT_ARM9_GXFIFO 21
+#define IRQ_BIT_ARM7_FOLD 22
+#define IRQ_BIT_ARM7_SPI 23
+#define IRQ_BIT_ARM7_WIFI 24
+
+#define IRQ_MASK_LCD_VBLANK (1<<0)
+#define IRQ_MASK_LCD_HBLANK (1<<1)
+#define IRQ_MASK_LCD_VMATCH (1<<2)
+#define IRQ_MASK_TIMER_0 (1<<3)
+#define IRQ_MASK_TIMER_1 (1<<4)
+#define IRQ_MASK_TIMER_2 (1<<5)
+#define IRQ_MASK_TIMER_3 (1<<6)
+#define IRQ_MASK_ARM7_SIO (1<<7)
+#define IRQ_MASK_DMA_0 (1<<8)
+#define IRQ_MASK_DMA_2 (1<<9)
+#define IRQ_MASK_DMA_3 (1<<10)
+#define IRQ_MASK_DMA_4 (1<<11)
+#define IRQ_MASK_KEYPAD (1<<12)
+#define IRQ_MASK_GAMEPAK (1<<13)
+#define IRQ_MASK_IPCSYNC (1<<16)
+#define IRQ_MASK_IPCFIFO_SENDEMPTY (1<<17)
+#define IRQ_MASK_IPCFIFO_RECVNONEMPTY (1<<18)
+#define IRQ_MASK_GC_TRANSFER_COMPLETE (1<<19)
+#define IRQ_MASK_GC_IREQ_MC (1<<20)
+#define IRQ_MASK_ARM9_GXFIFO (1<<21)
+#define IRQ_MASK_ARM7_FOLD (1<<22)
+#define IRQ_MASK_ARM7_SPI (1<<23)
+#define IRQ_MASK_ARM7_WIFI (1<<24)
+
 
 #endif