MMU: wifi registers/RAM are only in range 04800000-0480FFFF, not 04800000-04FFFFFF.
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455e2c7080
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@ -3642,7 +3642,7 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
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return;
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}
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if ((adr & 0xFF800000) == 0x04800000)
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if ((adr & 0xFFFF0000) == 0x04800000)
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{
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/* is wifi hardware, dont intermix with regular hardware registers */
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// 8-bit writes to wifi I/O and RAM are ignored
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@ -3721,7 +3721,7 @@ void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
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}
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//wifi mac access
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if ((adr>=0x04800000)&&(adr<0x05000000))
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if ((adr & 0xFFFF0000) == 0x04800000)
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{
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WIFI_write16(adr,val);
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][0x48], adr&MMU.MMU_MASK[ARMCPU_ARM7][0x48], val);
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@ -4026,10 +4026,8 @@ void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
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return;
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}
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if ((adr & 0xFF800000) == 0x04800000)
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if ((adr & 0xFFFF0000) == 0x04800000)
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{
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// access to non regular hw registers
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// return to not overwrite valid data
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WIFI_write16(adr, val & 0xFFFF);
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WIFI_write16(adr+2, val >> 16);
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM7][0x48], adr&MMU.MMU_MASK[ARMCPU_ARM7][0x48], val);
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@ -4125,7 +4123,7 @@ u8 FASTCALL _MMU_ARM7_read08(u32 adr)
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}
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// wifi mac access
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if ((adr>=0x04800000)&&(adr<0x05000000))
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if ((adr & 0xFFFF0000) == 0x04800000)
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{
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if (adr & 1)
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return (WIFI_read16(adr-1) >> 8) & 0xFF;
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@ -4174,7 +4172,7 @@ u16 FASTCALL _MMU_ARM7_read16(u32 adr)
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}
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//wifi mac access
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if ((adr>=0x04800000)&&(adr<0x05000000))
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if ((adr & 0xFFFF0000) == 0x04800000)
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return WIFI_read16(adr) ;
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if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
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@ -4267,7 +4265,7 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr)
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}
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//wifi mac access
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if ((adr>=0x04800000)&&(adr<0x05000000))
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if ((adr & 0xFFFF0000) == 0x04800000)
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return (WIFI_read16(adr) | (WIFI_read16(adr+2) << 16));
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if ( (adr >= 0x08000000) && (adr < 0x0A010000) )
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