clean up fake bios definition (add some asm comments and merge old codepaths); fix SWI3 patch on arm7; fix disassembler to be able to view arm7 bios (bios protection logic had crept in to interfere)
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@ -4410,7 +4410,7 @@ void FASTCALL _MMU_ARM7_write16(u32 adr, u16 val)
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFF [shash]
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][adr>>20], adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20], val);
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}
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}
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//================================================= MMU ARM7 write 32
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void FASTCALL _MMU_ARM7_write32(u32 adr, u32 val)
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{
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@ -4526,10 +4526,9 @@ u8 FASTCALL _MMU_ARM7_read08(u32 adr)
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if (adr < 0x4000)
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{
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//u32 prot = T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x04000308 & MMU.MMU_MASK[ARMCPU_ARM7][0x40]);
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//if (prot) INFO("MMU7 read 08 at 0x%08X (PC 0x%08X) BIOSPROT address 0x%08X\n", adr, NDS_ARM7.R[15], prot);
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//How accurate is this? our R[15] may not be exactly what the hardware uses (may use something less by up to 0x08)
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//the ARM7 bios can't be read by instructions outside of itself.
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//TODO - use REG_BIOSPROT
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//How accurate is this? our instruct_adr may not be exactly what the hardware uses (may use something +/- 0x08 or so)
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//This may be inaccurate at the very edge cases.
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if (NDS_ARM7.instruct_adr > 0x3FFF)
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return 0xFF;
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@ -4596,8 +4595,6 @@ u16 FASTCALL _MMU_ARM7_read16(u32 adr)
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if (adr < 0x4000)
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{
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//u32 prot = T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x04000308 & MMU.MMU_MASK[ARMCPU_ARM7][0x40]);
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//if (prot) INFO("MMU7 read 16 at 0x%08X (PC 0x%08X) BIOSPROT address 0x%08X\n", adr, NDS_ARM7.R[15], prot);
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if (NDS_ARM7.instruct_adr > 0x3FFF)
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return 0xFFFF;
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}
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@ -4696,8 +4693,10 @@ u32 FASTCALL _MMU_ARM7_read32(u32 adr)
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if (adr < 0x4000)
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{
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//u32 prot = T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x04000308 & MMU.MMU_MASK[ARMCPU_ARM7][0x40]);
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//if (prot) INFO("MMU7 read 32 at 0x%08X (PC 0x%08X) BIOSPROT address 0x%08X\n", adr, NDS_ARM7.R[15], prot);
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//the ARM7 bios can't be read by instructions outside of itself.
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//TODO - use REG_BIOSPROT
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//How accurate is this? our instruct_adr may not be exactly what the hardware uses (may use something +/- 0x08 or so)
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//This may be inaccurate at the very edge cases.
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if (NDS_ARM7.instruct_adr > 0x3FFF)
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return 0xFFFFFFFF;
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}
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@ -655,6 +655,12 @@ FORCEINLINE u8 _MMU_read08(const int PROCNUM, const MMU_ACCESS_TYPE AT, const u3
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{
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CheckMemoryDebugEvent(DEBUG_EVENT_READ,AT,PROCNUM,addr,8,0);
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//special handling to un-protect the ARM7 bios during debug reading
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if(PROCNUM == ARMCPU_ARM7 && AT == MMU_AT_DEBUG && addr<0x00004000)
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{
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return T1ReadByte(MMU.ARM7_BIOS, addr);
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}
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//special handling for DMA: read 0 from TCM
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if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)
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{
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@ -684,6 +690,12 @@ FORCEINLINE u16 _MMU_read16(const int PROCNUM, const MMU_ACCESS_TYPE AT, const u
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{
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CheckMemoryDebugEvent(DEBUG_EVENT_READ,AT,PROCNUM,addr,16,0);
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//special handling to un-protect the ARM7 bios during debug reading
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if(PROCNUM == ARMCPU_ARM7 && AT == MMU_AT_DEBUG && addr<0x00004000)
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{
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return T1ReadWord_guaranteedAligned(MMU.ARM7_BIOS, addr);
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}
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//special handling for DMA: read 0 from TCM
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if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)
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{
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@ -726,6 +738,12 @@ FORCEINLINE u32 _MMU_read32(const int PROCNUM, const MMU_ACCESS_TYPE AT, const u
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{
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CheckMemoryDebugEvent(DEBUG_EVENT_READ,AT,PROCNUM,addr,32,0);
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//special handling to un-protect the ARM7 bios during debug reading
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if(PROCNUM == ARMCPU_ARM7 && AT == MMU_AT_DEBUG && addr<0x00004000)
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{
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return T1ReadLong_guaranteedAligned(MMU.ARM7_BIOS, addr);
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}
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//special handling for DMA: read 0 from TCM
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if(PROCNUM==ARMCPU_ARM9 && AT == MMU_AT_DMA)
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{
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@ -2235,7 +2235,10 @@ static void PrepareBiosARM7()
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//if we used routines from bios, apply patches
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if (CommonSettings.PatchSWI3)
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_MMU_write16<ARMCPU_ARM7>(0x00002F08, 0x4770);
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{
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//[3801] SUB R0, #1 -> [4770] BX LR
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T1WriteWord(MMU.ARM7_BIOS,0x2F08, 0x4770);
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}
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}
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else
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NDS_ARM7.swi_tab = ARM_swi_tab[ARMCPU_ARM7];
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@ -2248,25 +2251,20 @@ static void PrepareBiosARM7()
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{
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//fake bios content, critical to normal operations, since we dont have a real bios.
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#if 0
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//someone please document what is in progress here
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// TODO
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T1WriteLong(MMU.ARM7_BIOS, 0x0000, 0xEAFFFFFE); // loop for Reset !!!
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T1WriteLong(MMU.ARM7_BIOS, 0x0004, 0xEAFFFFFE); // loop for Undef instr expection
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T1WriteLong(MMU.ARM7_BIOS, 0x0008, 0xEA00009C); // SWI
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T1WriteLong(MMU.ARM7_BIOS, 0x000C, 0xEAFFFFFE); // loop for Prefetch Abort
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T1WriteLong(MMU.ARM7_BIOS, 0x0010, 0xEAFFFFFE); // loop for Data Abort
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T1WriteLong(MMU.ARM7_BIOS, 0x0014, 0x00000000); // Reserved
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T1WriteLong(MMU.ARM7_BIOS, 0x001C, 0x00000000); // Fast IRQ
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#endif
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T1WriteLong(MMU.ARM7_BIOS, 0x0000, 0xE25EF002);
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T1WriteLong(MMU.ARM7_BIOS, 0x0018, 0xEA000000);
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T1WriteLong(MMU.ARM7_BIOS, 0x0020, 0xE92D500F);
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T1WriteLong(MMU.ARM7_BIOS, 0x0024, 0xE3A00301);
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T1WriteLong(MMU.ARM7_BIOS, 0x0028, 0xE28FE000);
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T1WriteLong(MMU.ARM7_BIOS, 0x002C, 0xE510F004);
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T1WriteLong(MMU.ARM7_BIOS, 0x0030, 0xE8BD500F);
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T1WriteLong(MMU.ARM7_BIOS, 0x0034, 0xE25EF004);
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T1WriteLong(MMU.ARM7_BIOS, 0x0000, 0xEAFFFFFE); //B 00000000 (reset: infinite loop) (originally: 0xE25EF002 - SUBS PC, LR, #2
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T1WriteLong(MMU.ARM7_BIOS, 0x0004, 0xEAFFFFFE); //B 00000004 (undefined instruction: infinite loop)
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T1WriteLong(MMU.ARM7_BIOS, 0x0008, 0xEAFFFFFE); //B 00000280 (SWI: infinite loop [since we will be HLEing the SWI routines])
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T1WriteLong(MMU.ARM7_BIOS, 0x000C, 0xEAFFFFFE); //B 0000000C (prefetch abort: infinite loop)
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T1WriteLong(MMU.ARM7_BIOS, 0x0010, 0xEAFFFFFE); //B 00000010 (data abort: infinite loop)
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T1WriteLong(MMU.ARM7_BIOS, 0x0018, 0xEA000000); //B 00000020 (IRQ: branch to handler)
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T1WriteLong(MMU.ARM7_BIOS, 0x001C, 0xEAFFFFFE); //B 0000001C (FIQ vector: infinite loop)
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//IRQ handler
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T1WriteLong(MMU.ARM7_BIOS, 0x0020, 0xE92D500F); //STMDB SP!, {R0-R3,R12,LR}
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T1WriteLong(MMU.ARM7_BIOS, 0x0024, 0xE3A00301); //MOV R0, #4000000
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T1WriteLong(MMU.ARM7_BIOS, 0x0028, 0xE28FE000); //ADD LR, PC, #0
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T1WriteLong(MMU.ARM7_BIOS, 0x002C, 0xE510F004); //LDR PC, [R0, -#4]
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T1WriteLong(MMU.ARM7_BIOS, 0x0030, 0xE8BD500F); //LDMIA SP!, {R0-R3,R12,LR}
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T1WriteLong(MMU.ARM7_BIOS, 0x0034, 0xE25EF004); //SUBS PC, LR, #4
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}
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}
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@ -2291,8 +2289,9 @@ static void PrepareBiosARM9()
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NDS_ARM9.swi_tab = 0;
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//if we used routines from bios, apply patches
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//[3801] SUB R0, #1 -> [4770] BX LR
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if (CommonSettings.PatchSWI3)
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_MMU_write16<ARMCPU_ARM9>(0xFFFF07CC, 0x4770);
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T1WriteWord(MMU.ARM9_BIOS, 0x07CC, 0x4770);
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}
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else NDS_ARM9.swi_tab = ARM_swi_tab[ARMCPU_ARM9];
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@ -2334,12 +2333,12 @@ static void PrepareBiosARM9()
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//copy the logo content into the bios - Pokemon Platinum uses this in Pal Park trade
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//it compares the logo from the arm9 bios to the logo in the GBA header.
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//NOTE: we could solve this by patching the rom of a mounted GBA game with whatever's here, even if its all zeroes.
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//NOTE: we could MAYBE solve this by patching the rom of a mounted GBA game with whatever's here, even if its all zeroes.
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for (int t = 0; t < 0x9C; t++)
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MMU.ARM9_BIOS[t + 0x20] = logo_data[t];
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//... and with that we are at 0xBC:
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//(now what goes in this gap??)
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//(now what goes in this gap?? nothing we need, i guess)
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//IRQ handler: get dtcm address and jump to a vector in it
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T1WriteLong(MMU.ARM9_BIOS, 0x0274, 0xE92D500F); //STMDB SP!, {R0-R3,R12,LR}
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@ -90,7 +90,7 @@ LRESULT DisViewBox_OnPaint(HWND hwnd, disview_struct *win, WPARAM wParam, LPARAM
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for(i = 0; i < nbligne; ++i)
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{
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u32 ins = MMU_read32(win->cpu->proc_ID, adr);
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u32 ins = _MMU_read32(win->cpu->proc_ID, MMU_AT_DEBUG, adr);
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des_arm_instructions_set[INDEX(ins)](adr, ins, txt);
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sprintf(text, "%04X:%04X %08X %s", (int)(adr>>16), (int)(adr&0xFFFF), (int)ins, txt);
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DrawText(mem_dc, text, -1, &rect, DT_TOP | DT_LEFT | DT_NOPREFIX);
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@ -124,7 +124,7 @@ LRESULT DisViewBox_OnPaint(HWND hwnd, disview_struct *win, WPARAM wParam, LPARAM
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for(i = 0; i < nbligne; ++i)
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{
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u32 ins = MMU_read16(win->cpu->proc_ID, adr);
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u32 ins = _MMU_read16(win->cpu->proc_ID, MMU_AT_DEBUG, adr);
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des_thumb_instructions_set[ins>>6](adr, ins, txt);
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sprintf(text, "%04X:%04X %04X %s", (int)(adr>>16), (int)(adr&0xFFFF), (int)ins, txt);
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DrawText(mem_dc, text, -1, &rect, DT_TOP | DT_LEFT | DT_NOPREFIX);
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