Oops, I forgot that the div/sqrt cycles are in 33 mhz units, not 66mhz units...

This commit is contained in:
luigi__ 2008-12-26 17:35:28 +00:00
parent 99edea516b
commit 026bbe304d
1 changed files with 4 additions and 4 deletions

View File

@ -730,7 +730,7 @@ void execsqrt() {
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B4, 0); T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B4, 0);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B0, cnt | 0x8000); T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B0, cnt | 0x8000);
MMU.sqrtCycles = (nds.cycles + 26); MMU.sqrtCycles = (nds.cycles + 13);
MMU.sqrtResult = ret; MMU.sqrtResult = ret;
MMU.sqrtCnt = (cnt & 0x7FFF); MMU.sqrtCnt = (cnt & 0x7FFF);
MMU.sqrtRunning = TRUE; MMU.sqrtRunning = TRUE;
@ -746,18 +746,18 @@ void execdiv() {
case 0: case 0:
num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x290); num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298); den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
MMU.divCycles = (nds.cycles + 34); MMU.divCycles = (nds.cycles + 18);
break; break;
case 3: //gbatek says this is same as mode 1 case 3: //gbatek says this is same as mode 1
case 1: case 1:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290); num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298); den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298);
MMU.divCycles = (nds.cycles + 68); MMU.divCycles = (nds.cycles + 34);
break; break;
case 2: case 2:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290); num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290);
den = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x298); den = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x298);
MMU.divCycles = (nds.cycles + 68); MMU.divCycles = (nds.cycles + 34);
break; break;
} }