* cleaning do_DMA
* factored some code in read/write_acl * skeleton for 3D vertices
This commit is contained in:
damdoum
parent
8b44d9fade
commit
0013777236
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@ -27,12 +27,13 @@
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#include <math.h>
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#include <string.h>
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#include "gl_vertex.h"
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#include "debug.h"
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#include "NDSSystem.h"
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#include "cflash.h"
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#include "cp15.h"
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#include "wifi.h"
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#include "registers.h"
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#define ROM_MASK 3
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@ -225,21 +226,21 @@ void MMU_clearMem()
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{
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int i;
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memset(ARM9Mem.ARM9_ABG, 0, 0x80000);
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memset(ARM9Mem.ARM9_AOBJ, 0, 0x40000);
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memset(ARM9Mem.ARM9_BBG, 0, 0x20000);
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memset(ARM9Mem.ARM9_BOBJ, 0, 0x20000);
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memset(ARM9Mem.ARM9_ABG, 0, 0x080000);
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memset(ARM9Mem.ARM9_AOBJ, 0, 0x040000);
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memset(ARM9Mem.ARM9_BBG, 0, 0x020000);
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memset(ARM9Mem.ARM9_BOBJ, 0, 0x020000);
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memset(ARM9Mem.ARM9_DTCM, 0, 0x4000);
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memset(ARM9Mem.ARM9_ITCM, 0, 0x8000);
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memset(ARM9Mem.ARM9_LCD, 0, 0xA4000);
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memset(ARM9Mem.ARM9_OAM, 0, 0x800);
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memset(ARM9Mem.ARM9_REG, 0, 0x1000000);
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memset(ARM9Mem.ARM9_VMEM, 0, 0x800);
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memset(ARM9Mem.ARM9_WRAM, 0, 0x1000000);
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memset(ARM9Mem.ARM9_LCD, 0, 0x0A4000);
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memset(ARM9Mem.ARM9_OAM, 0, 0x0800);
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memset(ARM9Mem.ARM9_REG, 0, 0x01000000);
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memset(ARM9Mem.ARM9_VMEM, 0, 0x0800);
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memset(ARM9Mem.ARM9_WRAM, 0, 0x01000000);
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memset(ARM9Mem.MAIN_MEM, 0, 0x400000);
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memset(MMU.ARM7_ERAM, 0, 0x10000);
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memset(MMU.ARM7_REG, 0, 0x10000);
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memset(MMU.ARM7_ERAM, 0, 0x010000);
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memset(MMU.ARM7_REG, 0, 0x010000);
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for(i = 0;i < 16;i++)
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FIFOInit(MMU.fifos + i);
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@ -1853,55 +1854,10 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
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switch(adr)
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{
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#ifdef RENDER3D
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case 0x040004AC :
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T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x4AC, val);
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if(proc==ARMCPU_ARM9)
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OGLRender::glTexImage2D(testval, TRUE);
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//execute = FALSE;
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return;
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case 0x040004A8 :
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case 0x04000350 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::glTexImage2D(val, FALSE);
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//execute = FALSE;
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testval = val;
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}
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return;
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case 0x04000488 :
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if(proc==ARMCPU_ARM9)
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{
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OGLRender::glTexCoord(val);
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//execute = FALSE;
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}
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return;
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case 0x0400046C :
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if(proc==ARMCPU_ARM9)
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{
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OGLRender::glScale(val);
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}
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return;
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case 0x04000490 :
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if(proc==ARMCPU_ARM9)
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{
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//GPULOG("VERTEX 10 %d\r\n",val);
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}
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return;
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case 0x04000494 :
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if(proc==ARMCPU_ARM9)
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{
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//GPULOG(printf(txt, "VERTEXY %d\r\n",val);
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}
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return;
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case 0x04000498 :
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if(proc==ARMCPU_ARM9)
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{
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//GPULOG("VERTEXZ %d\r\n",val);
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}
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return;
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case 0x0400049C :
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if(proc==ARMCPU_ARM9)
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{
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//GPULOG("VERTEYZ %d\r\n",val);
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OGLRender::glClearColor(val);
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}
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return;
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case 0x04000400 :
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@ -1910,48 +1866,12 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
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OGLRender::glCallList(val);
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}
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return;
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case 0x04000450 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::glRestore();
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}
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return;
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case 0x04000580 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::glViewPort(val);
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}
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return;
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case 0x04000350 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::glClearColor(val);
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}
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return;
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case 0x04000440 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::glMatrixMode(val);
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}
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return;
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case 0x04000458 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::ML4x4ajouter(val);
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}
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return;
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case 0x0400044C :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::glStoreMatrix(val);
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}
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return;
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case 0x0400045C :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::ML4x3ajouter(val);
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}
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return;
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case 0x04000444 :
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if(proc == ARMCPU_ARM9)
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{
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@ -1964,10 +1884,34 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
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OGLRender::glPopMatrix(val);
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}
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return;
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case 0x04000470 :
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case 0x0400044C :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::addTrans(val);
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OGLRender::glStoreMatrix(val);
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}
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return;
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case 0x04000450 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::glRestore();
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}
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return;
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case 0x04000454 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::glLoadIdentity();
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}
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return;
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case 0x04000458 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::ML4x4ajouter(val);
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}
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return;
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case 0x0400045C :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::ML4x3ajouter(val);
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}
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return;
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case 0x04000460 :
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@ -1988,16 +1932,16 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
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OGLRender::glMultMatrix3x3(val);
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}
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return;
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case 0x04000500 :
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case 0x0400046C :
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if(proc==ARMCPU_ARM9)
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{
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OGLRender::glBegin(val);
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OGLRender::glScale(val);
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}
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return;
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case 0x04000504 :
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case 0x04000470 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::glEnd();
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OGLRender::addTrans(val);
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}
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return;
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case 0x04000480 :
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@ -2006,22 +1950,89 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
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OGLRender::glColor3b(val);
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}
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return;
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case 0x0400048C :
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case 0x04000488 :
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if(proc==ARMCPU_ARM9)
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{
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OGLRender::glVertex3(val);
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OGLRender::glTexCoord(val);
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//execute = FALSE;
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}
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return;
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#endif
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case 0x0400048C :
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if(proc == ARMCPU_ARM9) {
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//OGLRender::glVertex3(val);
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}
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return;
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case 0x04000490 :
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if(proc==ARMCPU_ARM9) {
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//GPULOG("VERTEX 10 %d\r\n",val);
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gl_VTX_10(val);
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}
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return;
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case 0x04000494 :
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if(proc==ARMCPU_ARM9) {
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//GPULOG(printf(txt, "VERTEXY %d\r\n",val);
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gl_VTX_XY(val);
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}
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return;
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case 0x04000498 :
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if(proc==ARMCPU_ARM9) {
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//GPULOG("VERTEXZ %d\r\n",val);
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gl_VTX_XZ(val);
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}
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return;
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case 0x0400049C :
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if(proc==ARMCPU_ARM9) {
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//GPULOG("VERTEYZ %d\r\n",val);
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gl_VTX_YZ(val);
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}
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return;
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case 0x040004A0 :
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if(proc==ARMCPU_ARM9) {
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gl_VTX_DIFF(val);
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}
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return;
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#ifdef RENDER3D
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case 0x040004A8 :
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if(proc==ARMCPU_ARM9)
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{
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OGLRender::glTexImage2D(val, FALSE);
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//execute = FALSE;
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testval = val;
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}
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return;
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case 0x040004AC :
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T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x4AC, val);
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if(proc==ARMCPU_ARM9)
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OGLRender::glTexImage2D(testval, TRUE);
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//execute = FALSE;
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return;
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#endif
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case 0x04000500 :
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if(proc == ARMCPU_ARM9)
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{
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// OGLRender::glBegin(val);
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gl_VTX_begin(val);
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}
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return;
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case 0x04000504 :
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if(proc == ARMCPU_ARM9)
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{
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// OGLRender::glEnd();
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gl_VTX_end();
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}
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return;
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#ifdef RENDER3D
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case 0x04000540 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::glFlush();
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}
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return;
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case 0x04000454 :
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case 0x04000580 :
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if(proc == ARMCPU_ARM9)
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{
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OGLRender::glLoadIdentity();
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OGLRender::glViewPort(val);
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}
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return;
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#endif
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@ -2615,336 +2626,115 @@ void FASTCALL MMU_doDMA(u32 proc, u32 num)
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(((MMU.DMACrt[proc][num]>>26)&1) == 1)) // Transfer mode must be 32bit wide
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taille = 256*192/2;
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if(MMU.DMAStartTime[proc][num] == 5) taille *= 0x80;
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if(MMU.DMAStartTime[proc][num] == 5)
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taille *= 0x80;
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MMU.DMACycle[proc][num] = taille + nds.cycles;
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MMU.DMAing[proc][num] = TRUE;
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DMALOG("proc %d, dma %d src %08X dst %08X start %d taille %d repeat %s %08X\r\n", proc, num, src, dst, MMU.DMAStartTime[proc][num], taille, (MMU.DMACrt[proc][num]&(1<<25))?"on":"off",MMU.DMACrt[proc][num]);
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DMALOG("proc %d, dma %d src %08X dst %08X start %d taille %d repeat %s %08X\r\n",
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proc, num, src, dst, MMU.DMAStartTime[proc][num], taille,
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(MMU.DMACrt[proc][num]&(1<<25))?"on":"off",MMU.DMACrt[proc][num]);
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if(!(MMU.DMACrt[proc][num]&(1<<25))) MMU.DMAStartTime[proc][num] = 0;
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if(!(MMU.DMACrt[proc][num]&(1<<25)))
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MMU.DMAStartTime[proc][num] = 0;
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switch((MMU.DMACrt[proc][num]>>26)&1)
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// transfer
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{
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case 1 : /* 32 bit DMA transfers */
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switch(((MMU.DMACrt[proc][num]>>21)&0xF))
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{
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u32 i;
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case 0 : /* dst and src increment */
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for(i = 0; i < taille; ++i)
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u32 i=0;
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// 32 bit or 16 bit transfer ?
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int sz = ((MMU.DMACrt[proc][num]>>26)&1)? 4 : 2;
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int dstinc,srcinc;
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int u=(MMU.DMACrt[proc][num]>>21);
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switch(u & 0x3) {
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case 0 : dstinc = sz; break;
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case 1 : dstinc = 0; break;
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case 2 : dstinc = -sz; break;
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case 3 : dstinc = sz; break; //reload
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}
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switch(u >> 2) {
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case 0 : srcinc = sz; break;
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case 1 : srcinc = 0; break;
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case 2 : srcinc = -sz; break;
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case 3 : // reserved
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return;
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}
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if ((MMU.DMACrt[proc][num]>>26)&1)
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for(; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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dst += 4;
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src += 4;
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dst += dstinc;
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src += srcinc;
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}
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break;
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case 1 : /* dst decrement, src increment */
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for(i = 0; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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dst -= 4;
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src += 4;
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}
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break;
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case 2 : /* dst fixed, src increment */
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for(i = 0; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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src += 4;
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}
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break;
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case 3 : /*dst increment/reload, src increment */
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for(i = 0; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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dst += 4;
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src += 4;
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}
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break;
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case 4 : /* dst increment, src decrement */
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for(i = 0; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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dst += 4;
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src -= 4;
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}
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break;
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case 5 : /* dst decrement, src decrement */
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for(i = 0; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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dst -= 4;
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src -= 4;
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}
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break;
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case 6 : /* dst fixed, src decrement */
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for(i = 0; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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src -= 4;
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}
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break;
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case 7 : /* dst increment/reload, src decrement */
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for(i = 0; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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dst += 4;
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src -= 4;
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}
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break;
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case 8 : /* dst increment, src fixed */
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for(i = 0; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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dst += 4;
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}
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break;
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case 9 : /* dst decrement, src fixed */
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for(i = 0; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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dst -= 4;
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}
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break;
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case 10 : /* dst fixed, src fixed */
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for(i = 0; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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}
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break;
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case 11 : /* dst increment/reload, src fixed */
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for(i = 0; i < taille; ++i)
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{
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MMU_writeWord(proc, dst, MMU_readWord(proc, src));
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dst += 4;
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}
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break;
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default : /* reserved */
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break;
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}
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break;
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case 0 : /* 16 bit transfers */
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switch(((MMU.DMACrt[proc][num]>>21)&0xF))
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{
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u32 i;
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case 0 :
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for(i = 0; i < taille; ++i)
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else
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for(; i < taille; ++i)
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{
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MMU_write16(proc, dst, MMU_readHWord(proc, src));
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dst += 2;
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src += 2;
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dst += dstinc;
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src += srcinc;
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}
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break;
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case 1 :
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for(i = 0; i < taille; ++i)
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{
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MMU_write16(proc, dst, MMU_readHWord(proc, src));
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dst -= 2;
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src += 2;
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}
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break;
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case 2 :
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for(i = 0; i < taille; ++i)
|
||||
{
|
||||
MMU_write16(proc, dst, MMU_readHWord(proc, src));
|
||||
src += 2;
|
||||
}
|
||||
break;
|
||||
case 3 :
|
||||
for(i = 0; i < taille; ++i)
|
||||
{
|
||||
MMU_write16(proc, dst, MMU_readHWord(proc, src));
|
||||
dst += 2;
|
||||
src += 2;
|
||||
}
|
||||
break;
|
||||
case 4 :
|
||||
for(i = 0; i < taille; ++i)
|
||||
{
|
||||
MMU_write16(proc, dst, MMU_readHWord(proc, src));
|
||||
dst += 2;
|
||||
src -= 2;
|
||||
}
|
||||
break;
|
||||
case 5 :
|
||||
for(i = 0; i < taille; ++i)
|
||||
{
|
||||
MMU_write16(proc, dst, MMU_readHWord(proc, src));
|
||||
dst -= 2;
|
||||
src -= 2;
|
||||
}
|
||||
break;
|
||||
case 6 :
|
||||
for(i = 0; i < taille; ++i)
|
||||
{
|
||||
MMU_write16(proc, dst, MMU_readHWord(proc, src));
|
||||
src -= 2;
|
||||
}
|
||||
break;
|
||||
case 7 :
|
||||
for(i = 0; i < taille; ++i)
|
||||
{
|
||||
MMU_write16(proc, dst, MMU_readHWord(proc, src));
|
||||
dst += 2;
|
||||
src -= 2;
|
||||
}
|
||||
break;
|
||||
case 8 :
|
||||
for(i = 0; i < taille; ++i)
|
||||
{
|
||||
MMU_write16(proc, dst, MMU_readHWord(proc, src));
|
||||
dst += 2;
|
||||
}
|
||||
break;
|
||||
case 9 :
|
||||
for(i = 0; i < taille; ++i)
|
||||
{
|
||||
MMU_write16(proc, dst, MMU_readHWord(proc, src));
|
||||
dst -= 2;
|
||||
}
|
||||
break;
|
||||
case 10 :
|
||||
for(i = 0; i < taille; ++i)
|
||||
{
|
||||
MMU_write16(proc, dst, MMU_readHWord(proc, src));
|
||||
}
|
||||
break;
|
||||
case 11 :
|
||||
for(i = 0; i < taille; ++i)
|
||||
{
|
||||
MMU_write16(proc, dst, MMU_readHWord(proc, src));
|
||||
dst += 2;
|
||||
}
|
||||
break;
|
||||
default :
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef MMU_ENABLE_ACL
|
||||
|
||||
INLINE void check_access(u32 adr, u32 access) {
|
||||
/* every other mode: sys */
|
||||
access |= 1;
|
||||
if ((NDS_ARM9.CPSR.val & 0x1F) == 0x10) {
|
||||
/* is user mode access */
|
||||
access ^= 1 ;
|
||||
}
|
||||
if (armcp15_isAccessAllowed((armcp15_t *)NDS_ARM9.coproc[15],adr,access)==FALSE) {
|
||||
execute = FALSE ;
|
||||
}
|
||||
}
|
||||
INLINE void check_access_write(u32 adr) {
|
||||
u32 access = CP15_ACCESS_WRITE;
|
||||
check_access(adr, access)
|
||||
}
|
||||
|
||||
u8 FASTCALL MMU_read8_acl(u32 proc, u32 adr, u32 access)
|
||||
{
|
||||
if (proc == ARMCPU_ARM9) /* on arm9 we need to check the MPU regions */
|
||||
{
|
||||
if ((NDS_ARM9.CPSR.val & 0x1F) == 0x10)
|
||||
{
|
||||
/* is user mode access */
|
||||
access &= ~1 ;
|
||||
} else {
|
||||
/* every other mode: sys */
|
||||
access |= 1 ;
|
||||
}
|
||||
if (armcp15_isAccessAllowed((armcp15_t *)NDS_ARM9.coproc[15],adr,access)==FALSE)
|
||||
{
|
||||
execute = FALSE ;
|
||||
}
|
||||
}
|
||||
/* on arm9 we need to check the MPU regions */
|
||||
if (proc == ARMCPU_ARM9)
|
||||
check_access(u32 adr, u32 access);
|
||||
return MMU_read8(proc,adr);
|
||||
}
|
||||
|
||||
u16 FASTCALL MMU_read16_acl(u32 proc, u32 adr, u32 access)
|
||||
{
|
||||
if (proc == ARMCPU_ARM9) /* on arm9 we need to check the MPU regions */
|
||||
{
|
||||
if ((NDS_ARM9.CPSR.val & 0x1F) == 0x10)
|
||||
{
|
||||
/* is user mode access */
|
||||
access &= ~1 ;
|
||||
} else {
|
||||
/* every other mode: sys */
|
||||
access |= 1 ;
|
||||
}
|
||||
if (armcp15_isAccessAllowed((armcp15_t *)NDS_ARM9.coproc[15],adr,access)==FALSE)
|
||||
{
|
||||
execute = FALSE ;
|
||||
}
|
||||
}
|
||||
/* on arm9 we need to check the MPU regions */
|
||||
if (proc == ARMCPU_ARM9)
|
||||
check_access(u32 adr, u32 access);
|
||||
return MMU_read16(proc,adr);
|
||||
}
|
||||
|
||||
u32 FASTCALL MMU_read32_acl(u32 proc, u32 adr, u32 access)
|
||||
{
|
||||
if (proc == ARMCPU_ARM9) /* on arm9 we need to check the MPU regions */
|
||||
{
|
||||
if ((NDS_ARM9.CPSR.val & 0x1F) == 0x10)
|
||||
{
|
||||
/* is user mode access */
|
||||
access &= ~1 ;
|
||||
} else {
|
||||
/* every other mode: sys */
|
||||
access |= 1 ;
|
||||
}
|
||||
if (armcp15_isAccessAllowed((armcp15_t *)NDS_ARM9.coproc[15],adr,access)==FALSE)
|
||||
{
|
||||
execute = FALSE ;
|
||||
}
|
||||
}
|
||||
/* on arm9 we need to check the MPU regions */
|
||||
if (proc == ARMCPU_ARM9)
|
||||
check_access(u32 adr, u32 access);
|
||||
return MMU_read32(proc,adr);
|
||||
}
|
||||
|
||||
void FASTCALL MMU_write8_acl(u32 proc, u32 adr, u8 val)
|
||||
{
|
||||
if (proc == ARMCPU_ARM9) /* on arm9 we need to check the MPU regions */
|
||||
{
|
||||
u32 access = CP15_ACCESS_WRITE ;
|
||||
if ((NDS_ARM9.CPSR.val & 0x1F) == 0x10)
|
||||
{
|
||||
/* is user mode access */
|
||||
access &= ~1 ;
|
||||
} else {
|
||||
/* every other mode: sys */
|
||||
access |= 1 ;
|
||||
}
|
||||
if (armcp15_isAccessAllowed((armcp15_t *)NDS_ARM9.coproc[15],adr,access)==FALSE)
|
||||
{
|
||||
execute = FALSE ;
|
||||
}
|
||||
}
|
||||
/* check MPU region on ARM9 */
|
||||
if (proc == ARMCPU_ARM9)
|
||||
check_access_write(adr);
|
||||
MMU_write8(proc,adr,val);
|
||||
}
|
||||
|
||||
void FASTCALL MMU_write16_acl(u32 proc, u32 adr, u16 val)
|
||||
{
|
||||
if (proc == ARMCPU_ARM9) /* on arm9 we need to check the MPU regions */
|
||||
{
|
||||
u32 access = CP15_ACCESS_WRITE ;
|
||||
if ((NDS_ARM9.CPSR.val & 0x1F) == 0x10)
|
||||
{
|
||||
/* is user mode access */
|
||||
access &= ~1 ;
|
||||
} else {
|
||||
/* every other mode: sys */
|
||||
access |= 1 ;
|
||||
}
|
||||
if (armcp15_isAccessAllowed((armcp15_t *)NDS_ARM9.coproc[15],adr,access)==FALSE)
|
||||
{
|
||||
execute = FALSE ;
|
||||
}
|
||||
}
|
||||
/* check MPU region on ARM9 */
|
||||
if (proc == ARMCPU_ARM9)
|
||||
check_access_write(adr);
|
||||
MMU_write16(proc,adr,val) ;
|
||||
}
|
||||
|
||||
void FASTCALL MMU_write32_acl(u32 proc, u32 adr, u32 val)
|
||||
{
|
||||
if (proc == ARMCPU_ARM9) /* on arm9 we need to check the MPU regions */
|
||||
{
|
||||
u32 access = CP15_ACCESS_WRITE ;
|
||||
if ((NDS_ARM9.CPSR.val & 0x1F) == 0x10)
|
||||
{
|
||||
/* is user mode access */
|
||||
access &= ~1 ;
|
||||
} else {
|
||||
/* every other mode: sys */
|
||||
access |= 1 ;
|
||||
}
|
||||
if (armcp15_isAccessAllowed((armcp15_t *)NDS_ARM9.coproc[15],adr,access)==FALSE)
|
||||
{
|
||||
execute = FALSE ;
|
||||
}
|
||||
}
|
||||
/* check MPU region on ARM9 */
|
||||
if (proc == ARMCPU_ARM9)
|
||||
check_access_write(adr);
|
||||
MMU_write32(proc,adr,val) ;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@ libdesmume_a_SOURCES = \
|
|||
Disassembler.c Disassembler.h \
|
||||
dscard.h fat.h FIFO.c FIFO.h \
|
||||
GPU.c GPU.h \
|
||||
gl_vertex.c gl_vertex.h \
|
||||
mem.h mc.c mc.h \
|
||||
wifi.c wifi.h \
|
||||
MMU.c MMU.h NDSSystem.c NDSSystem.h registers.h \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,118 @@
|
|||
/* gl_vertex.c - this file is part of DeSmuME
|
||||
*
|
||||
* Copyright (C) 2007 Damien Nozay (damdoum)
|
||||
* Author: damdoum at users.sourceforge.net
|
||||
*
|
||||
* based on http://nocash.emubase.de/gbatek.htm
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include "gl_vertex.h"
|
||||
|
||||
static u16 vx=0,vy=0,vz=0;
|
||||
|
||||
INLINE void gl_VTX_one() {
|
||||
float vfx,vfy,vfz;
|
||||
vfx = vx / 4096.;
|
||||
vfy = vy / 4096.;
|
||||
vfz = vz / 4096.;
|
||||
printf ("\tVTX (x=%.12f,y=%.12f,z=%.12f)\n",vfx,vfy,vfz);
|
||||
}
|
||||
|
||||
void gl_VTX_begin(u32 val) {
|
||||
//see 4000500h - Cmd 40h - BEGIN_VTXS - Start of Vertex List (W)
|
||||
vx=vy=vz=0;
|
||||
printf ("VTX_begin : ");
|
||||
switch(val) {
|
||||
case 0 : // separate triangles (3 vertices for each triangle)
|
||||
printf ("GL_TRIANGLES\n");
|
||||
break;
|
||||
case 1 : // separate quads (4 vertices for each triangle)
|
||||
printf ("GL_QUADS\n");
|
||||
break;
|
||||
// strips : 1st triangle or quad defined by all vertices
|
||||
// next ones share a segment (so 2 vertices less)
|
||||
case 2 : // triangle strips (1st : 3, next : 1)
|
||||
printf ("GL_TRIANGLE_STRIP\n");
|
||||
break;
|
||||
case 3 : // quad strips (1st : 4, next : 2)
|
||||
printf ("GL_QUAD_STRIP\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
void gl_VTX_end() {
|
||||
//see 4000504h - Cmd 41h - END_VTXS - End of Vertex List (W)
|
||||
printf ("VTX_end.\n");
|
||||
}
|
||||
|
||||
|
||||
void gl_VTX_16 (u32 xxyy, u32 zz__) {
|
||||
//see 400048Ch - Cmd 23h - VTX_16 - Set Vertex XYZ Coordinates (W)
|
||||
_VTX_16 xy, z_;
|
||||
xy.val = xxyy;
|
||||
z_.val = zz__;
|
||||
vx = xy.bits.low ;
|
||||
vy = xy.bits.high;
|
||||
vz = z_.bits.low ;
|
||||
gl_VTX_one();
|
||||
}
|
||||
void gl_VTX_10 (u32 xyz) {
|
||||
//see 4000490h - Cmd 24h - VTX_10 - Set Vertex XYZ Coordinates (W)
|
||||
_VTX_10 vt;
|
||||
vt.val = xyz;
|
||||
vx = vt.bits.low << 6;
|
||||
vy = vt.bits.mid << 6;
|
||||
vz = vt.bits.high << 6;
|
||||
gl_VTX_one();
|
||||
}
|
||||
|
||||
|
||||
void gl_VTX_XY (u32 xy) {
|
||||
//see 4000494h - Cmd 25h - VTX_XY - Set Vertex XY Coordinates (W)
|
||||
_VTX_16 vt;
|
||||
vt.val = xy;
|
||||
vx = vt.bits.low ;
|
||||
vy = vt.bits.high;
|
||||
gl_VTX_one();
|
||||
}
|
||||
void gl_VTX_XZ (u32 xz) {
|
||||
//see 4000498h - Cmd 26h - VTX_XZ - Set Vertex XZ Coordinates (W)
|
||||
_VTX_16 vt;
|
||||
vt.val = xz;
|
||||
vx = vt.bits.low ;
|
||||
vz = vt.bits.high;
|
||||
gl_VTX_one();
|
||||
}
|
||||
void gl_VTX_YZ (u32 yz) {
|
||||
//see 400049Ch - Cmd 27h - VTX_YZ - Set Vertex YZ Coordinates (W)
|
||||
_VTX_16 vt;
|
||||
vt.val = yz;
|
||||
vy = vt.bits.low ;
|
||||
vz = vt.bits.high;
|
||||
gl_VTX_one();
|
||||
}
|
||||
|
||||
|
||||
void gl_VTX_DIFF (u32 diff) {
|
||||
//see 40004A0h - Cmd 28h - VTX_DIFF - Set Relative Vertex Coordinates (W)
|
||||
_VTX_10 vt;
|
||||
vt.val = diff;
|
||||
vx += vt.bits.low << 3;
|
||||
vy += vt.bits.mid << 3;
|
||||
vz += vt.bits.high << 3;
|
||||
gl_VTX_one();
|
||||
}
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
/* gl_vertex.h - this file is part of DeSmuME
|
||||
*
|
||||
* Copyright (C) 2007 Damien Nozay (damdoum)
|
||||
* Author: damdoum at users.sourceforge.net
|
||||
*
|
||||
* based on http://nocash.emubase.de/gbatek.htm
|
||||
*
|
||||
* This file is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; see the file COPYING. If not, write to
|
||||
* the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
|
||||
* Boston, MA 02111-1307, USA.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "types.h"
|
||||
|
||||
typedef union {
|
||||
u32 val;
|
||||
struct {
|
||||
unsigned primitive:2;
|
||||
unsigned :30;
|
||||
} bits;
|
||||
} _VTX_BEGIN_cmd ;
|
||||
typedef union {
|
||||
u32 val;
|
||||
struct { // 12 bit fractionnal
|
||||
signed low:16;
|
||||
signed high:16;
|
||||
} bits;
|
||||
} _VTX_16 ;
|
||||
typedef union {
|
||||
u32 val;
|
||||
struct { // 6 bit fractionnal
|
||||
signed low:10;
|
||||
signed mid:10;
|
||||
signed high:10;
|
||||
signed :2;
|
||||
} bits;
|
||||
} _VTX_10 ;
|
||||
|
||||
void gl_VTX_begin(u32 val);
|
||||
//see 4000500h - Cmd 40h - BEGIN_VTXS - Start of Vertex List (W)
|
||||
void gl_VTX_end();
|
||||
//see 4000504h - Cmd 41h - END_VTXS - End of Vertex List (W)
|
||||
|
||||
void gl_VTX_16 (u32 xxyy, u32 zz__);
|
||||
//see 400048Ch - Cmd 23h - VTX_16 - Set Vertex XYZ Coordinates (W)
|
||||
void gl_VTX_10 (u32 xyz);
|
||||
//see 4000490h - Cmd 24h - VTX_10 - Set Vertex XYZ Coordinates (W)
|
||||
|
||||
void gl_VTX_XY (u32 xy);
|
||||
//see 4000494h - Cmd 25h - VTX_XY - Set Vertex XY Coordinates (W)
|
||||
void gl_VTX_XZ (u32 xz);
|
||||
//see 4000498h - Cmd 26h - VTX_XZ - Set Vertex XZ Coordinates (W)
|
||||
void gl_VTX_YZ (u32 yz);
|
||||
//see 400049Ch - Cmd 27h - VTX_YZ - Set Vertex YZ Coordinates (W)
|
||||
|
||||
void gl_VTX_DIFF (u32 diff);
|
||||
//see 40004A0h - Cmd 28h - VTX_DIFF - Set Relative Vertex Coordinates (W)
|
||||
Loading…
Reference in New Issue