mirror of https://github.com/bsnes-emu/bsnes.git
134 lines
3.3 KiB
C++
Executable File
134 lines
3.3 KiB
C++
Executable File
struct GPR {
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uint32 data;
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function<void ()> modify;
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inline operator uint32() const { return data; }
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inline GPR& operator=(uint32 n) { data = n; if(modify) modify(); return *this; }
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inline GPR& operator=(const GPR& source) { return operator=(source.data); }
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inline GPR& operator &=(uint32 n) { return operator=(data & n); }
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inline GPR& operator |=(uint32 n) { return operator=(data | n); }
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inline GPR& operator ^=(uint32 n) { return operator=(data ^ n); }
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inline GPR& operator +=(uint32 n) { return operator=(data + n); }
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inline GPR& operator -=(uint32 n) { return operator=(data - n); }
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inline GPR& operator *=(uint32 n) { return operator=(data * n); }
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inline GPR& operator /=(uint32 n) { return operator=(data / n); }
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inline GPR& operator %=(uint32 n) { return operator=(data % n); }
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inline GPR& operator<<=(uint32 n) { return operator=(data << n); }
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inline GPR& operator>>=(uint32 n) { return operator=(data >> n); }
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};
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struct PSR {
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bool n; //negative
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bool z; //zero
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bool c; //carry
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bool v; //overflow
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bool i; //irq
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bool f; //fiq
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bool t; //thumb
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unsigned m; //mode
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inline operator uint32() const {
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return (n << 31) + (z << 30) + (c << 29) + (v << 28)
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+ (i << 7) + (f << 6) + (t << 5) + (m << 0);
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}
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inline PSR& operator=(uint32 d) {
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n = d & (1 << 31);
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z = d & (1 << 30);
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c = d & (1 << 29);
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v = d & (1 << 28);
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i = d & (1 << 7);
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f = d & (1 << 6);
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t = d & (1 << 5);
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m = d & 31;
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return *this;
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}
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void serialize(serializer&);
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};
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struct Pipeline {
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bool reload;
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struct Instruction {
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uint32 address;
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uint32 instruction;
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};
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Instruction execute;
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Instruction decode;
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Instruction fetch;
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};
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struct Processor {
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enum class Mode : unsigned {
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USR = 0x10, //user
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FIQ = 0x11, //fast interrupt request
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IRQ = 0x12, //interrupt request
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SVC = 0x13, //supervisor (software interrupt)
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ABT = 0x17, //abort
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UND = 0x1b, //undefined
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SYS = 0x1f, //system
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};
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GPR r0, r1, r2, r3, r4, r5, r6, r7;
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struct USR {
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GPR r8, r9, r10, r11, r12, sp, lr;
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} usr;
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struct FIQ {
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GPR r8, r9, r10, r11, r12, sp, lr;
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PSR spsr;
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} fiq;
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struct IRQ {
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GPR sp, lr;
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PSR spsr;
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} irq;
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struct SVC {
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GPR sp, lr;
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PSR spsr;
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} svc;
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struct ABT {
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GPR sp, lr;
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PSR spsr;
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} abt;
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struct UND {
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GPR sp, lr;
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PSR spsr;
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} und;
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GPR pc;
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PSR cpsr;
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bool carryout;
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bool sequential;
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bool irqline;
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GPR *r[16];
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PSR *spsr;
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void power();
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void setMode(Mode);
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};
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Processor processor;
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Pipeline pipeline;
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bool crash;
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void pipeline_step();
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alwaysinline GPR& r(unsigned n) { return *processor.r[n]; }
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alwaysinline PSR& cpsr() { return processor.cpsr; }
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alwaysinline PSR& spsr() { return *processor.spsr; }
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alwaysinline bool& carryout() { return processor.carryout; }
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alwaysinline bool& sequential() { return processor.sequential; }
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alwaysinline uint32 instruction() { return pipeline.execute.instruction; }
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alwaysinline Processor::Mode mode() { return (Processor::Mode)processor.cpsr.m; }
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alwaysinline bool privilegedmode() const { return (Processor::Mode)processor.cpsr.m != Processor::Mode::USR; }
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alwaysinline bool exceptionmode() const { return privilegedmode() && (Processor::Mode)processor.cpsr.m != Processor::Mode::SYS; }
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