mirror of https://github.com/bsnes-emu/bsnes.git
490 lines
12 KiB
C++
490 lines
12 KiB
C++
auto SA1::readIO(uint24 addr, uint8) -> uint8 {
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scheduler.active(cpu) ? cpu.synchronize(sa1) : synchronize(cpu);
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switch(0x2300 | addr.bits(0,7)) {
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//(SFR) S-CPU flag read
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case 0x2300: {
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uint8 data;
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data = mmio.cpu_irqfl << 7;
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data |= mmio.cpu_ivsw << 6;
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data |= mmio.chdma_irqfl << 5;
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data |= mmio.cpu_nvsw << 4;
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data |= mmio.cmeg;
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return data;
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}
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//(CFR) SA-1 flag read
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case 0x2301: {
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uint8 data;
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data = mmio.sa1_irqfl << 7;
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data |= mmio.timer_irqfl << 6;
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data |= mmio.dma_irqfl << 5;
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data |= mmio.sa1_nmifl << 4;
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data |= mmio.smeg;
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return data;
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}
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//(HCR) hcounter read
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case 0x2302: {
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//latch counters
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mmio.hcr = status.hcounter >> 2;
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mmio.vcr = status.vcounter;
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return mmio.hcr >> 0;
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}
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case 0x2303: {
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return mmio.hcr >> 8;
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}
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//(VCR) vcounter read
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case 0x2304: return mmio.vcr >> 0;
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case 0x2305: return mmio.vcr >> 8;
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//(MR) arithmetic result
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case 0x2306: return mmio.mr >> 0;
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case 0x2307: return mmio.mr >> 8;
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case 0x2308: return mmio.mr >> 16;
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case 0x2309: return mmio.mr >> 24;
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case 0x230a: return mmio.mr >> 32;
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//(OF) arithmetic overflow flag
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case 0x230b: return mmio.overflow << 7;
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//(VDPL) variable-length data read port low
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case 0x230c: {
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uint24 data;
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data.byte(0) = vbrRead(mmio.va + 0);
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data.byte(1) = vbrRead(mmio.va + 1);
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data.byte(2) = vbrRead(mmio.va + 2);
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data >>= mmio.vbit;
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return data >> 0;
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}
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//(VDPH) variable-length data read port high
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case 0x230d: {
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uint24 data;
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data.byte(0) = vbrRead(mmio.va + 0);
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data.byte(1) = vbrRead(mmio.va + 1);
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data.byte(2) = vbrRead(mmio.va + 2);
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data >>= mmio.vbit;
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if(mmio.hl == 1) {
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//auto-increment mode
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mmio.vbit += mmio.vb;
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mmio.va += (mmio.vbit >> 3);
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mmio.vbit &= 7;
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}
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return data >> 8;
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}
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//(VC) version code register
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case 0x230e: {
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return 0x01; //true value unknown
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}
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}
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return 0x00;
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}
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auto SA1::writeIO(uint24 addr, uint8 data) -> void {
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scheduler.active(cpu) ? cpu.synchronize(sa1) : synchronize(cpu);
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switch(0x2200 | addr.bits(0,7)) {
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//(CCNT) SA-1 control
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case 0x2200: {
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if(mmio.sa1_resb && !(data & 0x80)) {
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//reset SA-1 CPU
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r.pc.w = mmio.crv;
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r.pc.b = 0x00;
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}
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mmio.sa1_irq = (data & 0x80);
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mmio.sa1_rdyb = (data & 0x40);
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mmio.sa1_resb = (data & 0x20);
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mmio.sa1_nmi = (data & 0x10);
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mmio.smeg = (data & 0x0f);
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if(mmio.sa1_irq) {
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mmio.sa1_irqfl = true;
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if(mmio.sa1_irqen) mmio.sa1_irqcl = 0;
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}
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if(mmio.sa1_nmi) {
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mmio.sa1_nmifl = true;
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if(mmio.sa1_nmien) mmio.sa1_nmicl = 0;
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}
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return;
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}
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//(SIE) S-CPU interrupt enable
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case 0x2201: {
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if(!mmio.cpu_irqen && (data & 0x80)) {
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if(mmio.cpu_irqfl) {
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mmio.cpu_irqcl = 0;
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cpu.r.irq = 1;
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}
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}
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if(!mmio.chdma_irqen && (data & 0x20)) {
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if(mmio.chdma_irqfl) {
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mmio.chdma_irqcl = 0;
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cpu.r.irq = 1;
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}
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}
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mmio.cpu_irqen = (data & 0x80);
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mmio.chdma_irqen = (data & 0x20);
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return;
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}
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//(SIC) S-CPU interrupt clear
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case 0x2202: {
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mmio.cpu_irqcl = (data & 0x80);
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mmio.chdma_irqcl = (data & 0x20);
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if(mmio.cpu_irqcl ) mmio.cpu_irqfl = false;
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if(mmio.chdma_irqcl) mmio.chdma_irqfl = false;
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if(!mmio.cpu_irqfl && !mmio.chdma_irqfl) cpu.r.irq = 0;
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return;
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}
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//(CRV) SA-1 reset vector
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case 0x2203: { mmio.crv = (mmio.crv & 0xff00) | data; return; }
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case 0x2204: { mmio.crv = (data << 8) | (mmio.crv & 0xff); return; }
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//(CNV) SA-1 NMI vector
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case 0x2205: { mmio.cnv = (mmio.cnv & 0xff00) | data; return; }
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case 0x2206: { mmio.cnv = (data << 8) | (mmio.cnv & 0xff); return; }
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//(CIV) SA-1 IRQ vector
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case 0x2207: { mmio.civ = (mmio.civ & 0xff00) | data; return; }
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case 0x2208: { mmio.civ = (data << 8) | (mmio.civ & 0xff); return; }
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//(SCNT) S-CPU control
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case 0x2209: {
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mmio.cpu_irq = (data & 0x80);
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mmio.cpu_ivsw = (data & 0x40);
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mmio.cpu_nvsw = (data & 0x10);
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mmio.cmeg = (data & 0x0f);
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if(mmio.cpu_irq) {
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mmio.cpu_irqfl = true;
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if(mmio.cpu_irqen) {
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mmio.cpu_irqcl = 0;
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cpu.r.irq = 1;
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}
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}
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return;
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}
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//(CIE) SA-1 interrupt enable
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case 0x220a: {
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if(!mmio.sa1_irqen && (data & 0x80) && mmio.sa1_irqfl ) mmio.sa1_irqcl = 0;
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if(!mmio.timer_irqen && (data & 0x40) && mmio.timer_irqfl) mmio.timer_irqcl = 0;
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if(!mmio.dma_irqen && (data & 0x20) && mmio.dma_irqfl ) mmio.dma_irqcl = 0;
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if(!mmio.sa1_nmien && (data & 0x10) && mmio.sa1_nmifl ) mmio.sa1_nmicl = 0;
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mmio.sa1_irqen = (data & 0x80);
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mmio.timer_irqen = (data & 0x40);
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mmio.dma_irqen = (data & 0x20);
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mmio.sa1_nmien = (data & 0x10);
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return;
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}
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//(CIC) SA-1 interrupt clear
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case 0x220b: {
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mmio.sa1_irqcl = (data & 0x80);
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mmio.timer_irqcl = (data & 0x40);
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mmio.dma_irqcl = (data & 0x20);
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mmio.sa1_nmicl = (data & 0x10);
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if(mmio.sa1_irqcl) mmio.sa1_irqfl = false;
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if(mmio.timer_irqcl) mmio.timer_irqfl = false;
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if(mmio.dma_irqcl) mmio.dma_irqfl = false;
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if(mmio.sa1_nmicl) mmio.sa1_nmifl = false;
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return;
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}
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//(SNV) S-CPU NMI vector
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case 0x220c: { mmio.snv = (mmio.snv & 0xff00) | data; return; }
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case 0x220d: { mmio.snv = (data << 8) | (mmio.snv & 0xff); return; }
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//(SIV) S-CPU IRQ vector
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case 0x220e: { mmio.siv = (mmio.siv & 0xff00) | data; return; }
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case 0x220f: { mmio.siv = (data << 8) | (mmio.siv & 0xff); return; }
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//(TMC) H/V timer control
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case 0x2210: {
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mmio.hvselb = (data & 0x80);
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mmio.ven = (data & 0x02);
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mmio.hen = (data & 0x01);
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return;
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}
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//(CTR) SA-1 timer restart
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case 0x2211: {
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status.vcounter = 0;
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status.hcounter = 0;
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return;
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}
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//(HCNT) H-count
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case 0x2212: { mmio.hcnt = (mmio.hcnt & 0xff00) | (data << 0); return; }
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case 0x2213: { mmio.hcnt = (mmio.hcnt & 0x00ff) | (data << 8); return; }
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//(VCNT) V-count
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case 0x2214: { mmio.vcnt = (mmio.vcnt & 0xff00) | (data << 0); return; }
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case 0x2215: { mmio.vcnt = (mmio.vcnt & 0x00ff) | (data << 8); return; }
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//(CXB) Super MMC bank C
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case 0x2220: {
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mmio.cbmode = (data & 0x80);
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mmio.cb = (data & 0x07);
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return;
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}
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//(DXB) Super MMC bank D
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case 0x2221: {
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mmio.dbmode = (data & 0x80);
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mmio.db = (data & 0x07);
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return;
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}
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//(EXB) Super MMC bank E
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case 0x2222: {
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mmio.ebmode = (data & 0x80);
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mmio.eb = (data & 0x07);
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return;
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}
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//(FXB) Super MMC bank F
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case 0x2223: {
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mmio.fbmode = (data & 0x80);
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mmio.fb = (data & 0x07);
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return;
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}
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//(BMAPS) S-CPU BW-RAM address mapping
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case 0x2224: {
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mmio.sbm = (data & 0x1f);
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return;
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}
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//(BMAP) SA-1 BW-RAM address mapping
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case 0x2225: {
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mmio.sw46 = (data & 0x80);
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mmio.cbm = (data & 0x7f);
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return;
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}
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//(SWBE) S-CPU BW-RAM write enable
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case 0x2226: {
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mmio.swen = (data & 0x80);
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return;
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}
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//(CWBE) SA-1 BW-RAM write enable
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case 0x2227: {
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mmio.cwen = (data & 0x80);
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return;
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}
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//(BWPA) BW-RAM write-protected area
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case 0x2228: {
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mmio.bwp = (data & 0x0f);
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return;
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}
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//(SIWP) S-CPU I-RAM write protection
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case 0x2229: {
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mmio.siwp = data;
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return;
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}
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//(CIWP) SA-1 I-RAM write protection
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case 0x222a: {
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mmio.ciwp = data;
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return;
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}
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//(DCNT) DMA control
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case 0x2230: {
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mmio.dmaen = (data & 0x80);
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mmio.dprio = (data & 0x40);
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mmio.cden = (data & 0x20);
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mmio.cdsel = (data & 0x10);
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mmio.dd = (data & 0x04);
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mmio.sd = (data & 0x03);
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if(mmio.dmaen == 0) dma.line = 0;
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return;
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}
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//(CDMA) character conversion DMA parameters
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case 0x2231: {
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mmio.chdend = (data & 0x80);
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mmio.dmasize = (data >> 2) & 7;
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mmio.dmacb = (data & 0x03);
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if(mmio.chdend) cpubwram.dma = false;
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if(mmio.dmasize > 5) mmio.dmasize = 5;
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if(mmio.dmacb > 2) mmio.dmacb = 2;
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return;
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}
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//(SDA) DMA source device start address
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case 0x2232: { mmio.dsa = (mmio.dsa & 0xffff00) | (data << 0); return; }
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case 0x2233: { mmio.dsa = (mmio.dsa & 0xff00ff) | (data << 8); return; }
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case 0x2234: { mmio.dsa = (mmio.dsa & 0x00ffff) | (data << 16); return; }
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//(DDA) DMA destination start address
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case 0x2235: { mmio.dda = (mmio.dda & 0xffff00) | (data << 0); return; }
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case 0x2236: { mmio.dda = (mmio.dda & 0xff00ff) | (data << 8);
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if(mmio.dmaen) {
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if(mmio.cden == 0 && mmio.dd == DMA::DestIRAM) {
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dmaNormal();
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} else if(mmio.cden == 1 && mmio.cdsel == 1) {
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dmaCC1();
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}
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}
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return;
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}
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case 0x2237: { mmio.dda = (mmio.dda & 0x00ffff) | (data << 16);
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if(mmio.dmaen) {
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if(mmio.cden == 0 && mmio.dd == DMA::DestBWRAM) {
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dmaNormal();
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}
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}
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return;
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}
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//(DTC) DMA terminal counter
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case 0x2238: { mmio.dtc = (mmio.dtc & 0xff00) | (data << 0); return; }
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case 0x2239: { mmio.dtc = (mmio.dtc & 0x00ff) | (data << 8); return; }
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//(BBF) BW-RAM bitmap format
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case 0x223f: { mmio.bbf = (data & 0x80); return; }
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//(BRF) bitmap register files
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case 0x2240: { mmio.brf[ 0] = data; return; }
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case 0x2241: { mmio.brf[ 1] = data; return; }
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case 0x2242: { mmio.brf[ 2] = data; return; }
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case 0x2243: { mmio.brf[ 3] = data; return; }
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case 0x2244: { mmio.brf[ 4] = data; return; }
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case 0x2245: { mmio.brf[ 5] = data; return; }
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case 0x2246: { mmio.brf[ 6] = data; return; }
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case 0x2247: { mmio.brf[ 7] = data;
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if(mmio.dmaen) {
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if(mmio.cden == 1 && mmio.cdsel == 0) {
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dmaCC2();
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}
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}
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return;
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}
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case 0x2248: { mmio.brf[ 8] = data; return; }
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case 0x2249: { mmio.brf[ 9] = data; return; }
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case 0x224a: { mmio.brf[10] = data; return; }
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case 0x224b: { mmio.brf[11] = data; return; }
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case 0x224c: { mmio.brf[12] = data; return; }
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case 0x224d: { mmio.brf[13] = data; return; }
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case 0x224e: { mmio.brf[14] = data; return; }
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case 0x224f: { mmio.brf[15] = data;
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if(mmio.dmaen) {
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if(mmio.cden == 1 && mmio.cdsel == 0) {
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dmaCC2();
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}
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}
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return;
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}
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//(MCNT) arithmetic control
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case 0x2250: {
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mmio.acm = (data & 0x02);
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mmio.md = (data & 0x01);
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if(mmio.acm) mmio.mr = 0;
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return;
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}
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//(MAL) multiplicand / dividend low
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case 0x2251: {
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mmio.ma = (mmio.ma & 0xff00) | data;
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return;
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}
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//(MAH) multiplicand / dividend high
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case 0x2252: {
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mmio.ma = (data << 8) | (mmio.ma & 0x00ff);
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return;
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}
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//(MBL) multiplier / divisor low
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case 0x2253: {
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mmio.mb = (mmio.mb & 0xff00) | data;
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return;
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}
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//(MBH) multiplier / divisor high
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//multiplication / cumulative sum only resets MB
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//division resets both MA and MB
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case 0x2254: {
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mmio.mb = (data << 8) | (mmio.mb & 0x00ff);
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if(mmio.acm == 0) {
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if(mmio.md == 0) {
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//signed multiplication
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mmio.mr = (int16)mmio.ma * (int16)mmio.mb;
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mmio.mb = 0;
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} else {
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//unsigned division
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if(mmio.mb == 0) {
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mmio.mr = 0;
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} else {
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int16 quotient = (int16)mmio.ma / (uint16)mmio.mb;
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uint16 remainder = (int16)mmio.ma % (uint16)mmio.mb;
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mmio.mr = (remainder << 16) | quotient;
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}
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mmio.ma = 0;
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mmio.mb = 0;
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}
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} else {
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//sigma (accumulative multiplication)
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mmio.mr += (int16)mmio.ma * (int16)mmio.mb;
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mmio.overflow = (mmio.mr >= (1ULL << 40));
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mmio.mr &= (1ULL << 40) - 1;
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mmio.mb = 0;
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}
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return;
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}
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//(VBD) variable-length bit processing
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case 0x2258: {
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mmio.hl = (data & 0x80);
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mmio.vb = (data & 0x0f);
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if(mmio.vb == 0) mmio.vb = 16;
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if(mmio.hl == 0) {
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//fixed mode
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mmio.vbit += mmio.vb;
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mmio.va += (mmio.vbit >> 3);
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mmio.vbit &= 7;
|
|
}
|
|
return;
|
|
}
|
|
|
|
//(VDA) variable-length bit game pak ROM start address
|
|
case 0x2259: { mmio.va = (mmio.va & 0xffff00) | (data << 0); return; }
|
|
case 0x225a: { mmio.va = (mmio.va & 0xff00ff) | (data << 8); return; }
|
|
case 0x225b: { mmio.va = (mmio.va & 0x00ffff) | (data << 16); mmio.vbit = 0; return; }
|
|
|
|
}
|
|
}
|