mirror of https://github.com/bsnes-emu/bsnes.git
542 lines
12 KiB
C++
Executable File
542 lines
12 KiB
C++
Executable File
#ifdef CPU_CPP
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uint8 CPU::pio() { return status.pio; }
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bool CPU::joylatch() { return status.joypad_strobe_latch; }
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//WMDATA
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uint8 CPU::mmio_r2180() {
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uint8 r = bus.read(0x7e0000 | status.wram_addr);
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status.wram_addr = (status.wram_addr + 1) & 0x01ffff;
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return r;
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}
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//WMDATA
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void CPU::mmio_w2180(uint8 data) {
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bus.write(0x7e0000 | status.wram_addr, data);
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status.wram_addr = (status.wram_addr + 1) & 0x01ffff;
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}
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//WMADDL
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void CPU::mmio_w2181(uint8 data) {
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status.wram_addr = (status.wram_addr & 0xffff00) | (data);
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status.wram_addr &= 0x01ffff;
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}
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//WMADDM
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void CPU::mmio_w2182(uint8 data) {
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status.wram_addr = (status.wram_addr & 0xff00ff) | (data << 8);
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status.wram_addr &= 0x01ffff;
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}
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//WMADDH
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void CPU::mmio_w2183(uint8 data) {
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status.wram_addr = (status.wram_addr & 0x00ffff) | (data << 16);
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status.wram_addr &= 0x01ffff;
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}
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//JOYSER0
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//bit 0 is shared between JOYSER0 and JOYSER1, therefore
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//strobing $4016.d0 affects both controller port latches.
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//$4017 bit 0 writes are ignored.
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void CPU::mmio_w4016(uint8 data) {
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bool old_latch = status.joypad_strobe_latch;
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bool new_latch = data & 1;
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status.joypad_strobe_latch = new_latch;
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if(old_latch != new_latch) {
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input.poll();
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}
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}
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//JOYSER0
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//7-2 = MDR
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//1-0 = Joypad serial data
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uint8 CPU::mmio_r4016() {
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uint8 r = regs.mdr & 0xfc;
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r |= input.port_read(0) & 3;
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return r;
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}
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//JOYSER1
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//7-5 = MDR
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//4-2 = Always 1 (pins are connected to GND)
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//1-0 = Joypad serial data
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uint8 CPU::mmio_r4017() {
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uint8 r = (regs.mdr & 0xe0) | 0x1c;
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r |= input.port_read(1) & 3;
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return r;
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}
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//NMITIMEN
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void CPU::mmio_w4200(uint8 data) {
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status.auto_joypad_poll = !!(data & 0x01);
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nmitimen_update(data);
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}
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//WRIO
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void CPU::mmio_w4201(uint8 data) {
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if((status.pio & 0x80) && !(data & 0x80)) {
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ppu.latch_counters();
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}
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status.pio = data;
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}
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//WRMPYA
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void CPU::mmio_w4202(uint8 data) {
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status.wrmpya = data;
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}
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//WRMPYB
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void CPU::mmio_w4203(uint8 data) {
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status.rdmpy = 0;
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if(alu.mpyctr || alu.divctr) return;
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status.wrmpyb = data;
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status.rddiv = (status.wrmpyb << 8) | status.wrmpya;
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alu.mpyctr = 8; //perform multiplication over the next eight cycles
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alu.shift = status.wrmpyb;
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}
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//WRDIVL
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void CPU::mmio_w4204(uint8 data) {
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status.wrdiva = (status.wrdiva & 0xff00) | (data);
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}
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//WRDIVH
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void CPU::mmio_w4205(uint8 data) {
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status.wrdiva = (status.wrdiva & 0x00ff) | (data << 8);
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}
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//WRDIVB
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void CPU::mmio_w4206(uint8 data) {
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status.rdmpy = status.wrdiva;
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if(alu.mpyctr || alu.divctr) return;
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status.wrdivb = data;
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alu.divctr = 16; //perform division over the next sixteen cycles
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alu.shift = status.wrdivb << 16;
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}
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//HTIMEL
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void CPU::mmio_w4207(uint8 data) {
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status.hirq_pos = (status.hirq_pos & ~0xff) | (data);
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status.hirq_pos &= 0x01ff;
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}
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//HTIMEH
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void CPU::mmio_w4208(uint8 data) {
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status.hirq_pos = (status.hirq_pos & 0xff) | (data << 8);
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status.hirq_pos &= 0x01ff;
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}
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//VTIMEL
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void CPU::mmio_w4209(uint8 data) {
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status.virq_pos = (status.virq_pos & ~0xff) | (data);
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status.virq_pos &= 0x01ff;
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}
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//VTIMEH
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void CPU::mmio_w420a(uint8 data) {
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status.virq_pos = (status.virq_pos & 0xff) | (data << 8);
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status.virq_pos &= 0x01ff;
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}
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//DMAEN
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void CPU::mmio_w420b(uint8 data) {
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for(unsigned i = 0; i < 8; i++) {
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channel[i].dma_enabled = data & (1 << i);
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}
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if(data) status.dma_pending = true;
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}
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//HDMAEN
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void CPU::mmio_w420c(uint8 data) {
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for(unsigned i = 0; i < 8; i++) {
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channel[i].hdma_enabled = data & (1 << i);
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}
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}
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//MEMSEL
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void CPU::mmio_w420d(uint8 data) {
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status.rom_speed = (data & 1 ? 6 : 8);
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}
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//RDNMI
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//7 = NMI acknowledge
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//6-4 = MDR
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//3-0 = CPU (5a22) version
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uint8 CPU::mmio_r4210() {
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uint8 r = (regs.mdr & 0x70);
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r |= (uint8)(rdnmi()) << 7;
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r |= (cpu_version & 0x0f);
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return r;
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}
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//TIMEUP
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//7 = IRQ acknowledge
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//6-0 = MDR
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uint8 CPU::mmio_r4211() {
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uint8 r = (regs.mdr & 0x7f);
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r |= (uint8)(timeup()) << 7;
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return r;
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}
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//HVBJOY
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//7 = VBLANK acknowledge
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//6 = HBLANK acknowledge
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//5-1 = MDR
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//0 = JOYPAD acknowledge
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uint8 CPU::mmio_r4212() {
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uint8 r = (regs.mdr & 0x3e);
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uint16 vs = ppu.overscan() == false ? 225 : 240;
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//auto joypad polling
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if(vcounter() >= vs && vcounter() <= (vs + 2))r |= 0x01;
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//hblank
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if(hcounter() <= 2 || hcounter() >= 1096)r |= 0x40;
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//vblank
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if(vcounter() >= vs)r |= 0x80;
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return r;
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}
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//RDIO
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uint8 CPU::mmio_r4213() {
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return status.pio;
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}
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//RDDIVL
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uint8 CPU::mmio_r4214() {
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return status.rddiv;
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}
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//RDDIVH
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uint8 CPU::mmio_r4215() {
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return status.rddiv >> 8;
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}
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//RDMPYL
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uint8 CPU::mmio_r4216() {
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return status.rdmpy;
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}
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//RDMPYH
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uint8 CPU::mmio_r4217() {
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return status.rdmpy >> 8;
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}
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//TODO: handle reads during joypad polling (v=225-227)
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uint8 CPU::mmio_r4218() { return status.joy1l; } //JOY1L
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uint8 CPU::mmio_r4219() { return status.joy1h; } //JOY1H
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uint8 CPU::mmio_r421a() { return status.joy2l; } //JOY2L
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uint8 CPU::mmio_r421b() { return status.joy2h; } //JOY2H
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uint8 CPU::mmio_r421c() { return status.joy3l; } //JOY3L
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uint8 CPU::mmio_r421d() { return status.joy3h; } //JOY3H
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uint8 CPU::mmio_r421e() { return status.joy4l; } //JOY4L
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uint8 CPU::mmio_r421f() { return status.joy4h; } //JOY4H
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//DMAPx
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uint8 CPU::mmio_r43x0(uint8 i) {
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return channel[i].dmap;
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}
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//BBADx
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uint8 CPU::mmio_r43x1(uint8 i) {
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return channel[i].destaddr;
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}
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//A1TxL
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uint8 CPU::mmio_r43x2(uint8 i) {
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return channel[i].srcaddr;
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}
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//A1TxH
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uint8 CPU::mmio_r43x3(uint8 i) {
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return channel[i].srcaddr >> 8;
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}
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//A1Bx
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uint8 CPU::mmio_r43x4(uint8 i) {
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return channel[i].srcbank;
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}
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//DASxL
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//union { uint16 xfersize; uint16 hdma_iaddr; };
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uint8 CPU::mmio_r43x5(uint8 i) {
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return channel[i].xfersize;
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}
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//DASxH
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//union { uint16 xfersize; uint16 hdma_iaddr; };
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uint8 CPU::mmio_r43x6(uint8 i) {
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return channel[i].xfersize >> 8;
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}
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//DASBx
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uint8 CPU::mmio_r43x7(uint8 i) {
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return channel[i].hdma_ibank;
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}
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//A2AxL
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uint8 CPU::mmio_r43x8(uint8 i) {
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return channel[i].hdma_addr;
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}
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//A2AxH
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uint8 CPU::mmio_r43x9(uint8 i) {
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return channel[i].hdma_addr >> 8;
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}
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//NTRLx
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uint8 CPU::mmio_r43xa(uint8 i) {
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return channel[i].hdma_line_counter;
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}
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//???
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uint8 CPU::mmio_r43xb(uint8 i) {
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return channel[i].unknown;
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}
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//DMAPx
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void CPU::mmio_w43x0(uint8 i, uint8 data) {
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channel[i].dmap = data;
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channel[i].direction = data & 0x80;
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channel[i].hdma_indirect = data & 0x40;
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channel[i].reversexfer = data & 0x10;
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channel[i].fixedxfer = data & 0x08;
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channel[i].xfermode = data & 7;
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}
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//DDBADx
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void CPU::mmio_w43x1(uint8 i, uint8 data) {
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channel[i].destaddr = data;
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}
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//A1TxL
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void CPU::mmio_w43x2(uint8 i, uint8 data) {
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channel[i].srcaddr = (channel[i].srcaddr & 0xff00) | (data);
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}
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//A1TxH
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void CPU::mmio_w43x3(uint8 i, uint8 data) {
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channel[i].srcaddr = (channel[i].srcaddr & 0x00ff) | (data << 8);
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}
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//A1Bx
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void CPU::mmio_w43x4(uint8 i, uint8 data) {
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channel[i].srcbank = data;
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}
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//DASxL
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//union { uint16 xfersize; uint16 hdma_iaddr; };
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void CPU::mmio_w43x5(uint8 i, uint8 data) {
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channel[i].xfersize = (channel[i].xfersize & 0xff00) | (data);
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}
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//DASxH
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//union { uint16 xfersize; uint16 hdma_iaddr; };
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void CPU::mmio_w43x6(uint8 i, uint8 data) {
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channel[i].xfersize = (channel[i].xfersize & 0x00ff) | (data << 8);
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}
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//DASBx
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void CPU::mmio_w43x7(uint8 i, uint8 data) {
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channel[i].hdma_ibank = data;
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}
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//A2AxL
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void CPU::mmio_w43x8(uint8 i, uint8 data) {
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channel[i].hdma_addr = (channel[i].hdma_addr & 0xff00) | (data);
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}
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//A2AxH
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void CPU::mmio_w43x9(uint8 i, uint8 data) {
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channel[i].hdma_addr = (channel[i].hdma_addr & 0x00ff) | (data << 8);
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}
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//NTRLx
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void CPU::mmio_w43xa(uint8 i, uint8 data) {
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channel[i].hdma_line_counter = data;
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}
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//???
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void CPU::mmio_w43xb(uint8 i, uint8 data) {
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channel[i].unknown = data;
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}
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void CPU::mmio_power() {
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}
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void CPU::mmio_reset() {
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//$2181-$2183
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status.wram_addr = 0x000000;
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//$4016-$4017
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status.joypad_strobe_latch = 0;
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status.joypad1_bits = ~0;
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status.joypad2_bits = ~0;
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//$4200
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status.nmi_enabled = false;
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status.hirq_enabled = false;
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status.virq_enabled = false;
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status.auto_joypad_poll = false;
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//$4201
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status.pio = 0xff;
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//$4202-$4203
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status.wrmpya = 0xff;
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status.wrmpyb = 0xff;
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//$4204-$4206
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status.wrdiva = 0xffff;
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status.wrdivb = 0xff;
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//$4207-$420a
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status.hirq_pos = 0x01ff;
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status.virq_pos = 0x01ff;
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//$420d
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status.rom_speed = 8;
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//$4214-$4217
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status.rddiv = 0x0000;
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status.rdmpy = 0x0000;
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//$4218-$421f
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status.joy1l = 0x00;
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status.joy1h = 0x00;
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status.joy2l = 0x00;
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status.joy2h = 0x00;
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status.joy3l = 0x00;
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status.joy3h = 0x00;
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status.joy4l = 0x00;
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status.joy4h = 0x00;
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//ALU
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alu.mpyctr = 0;
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alu.divctr = 0;
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alu.shift = 0;
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}
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uint8 CPU::mmio_read(unsigned addr) {
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addr &= 0xffff;
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//APU
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if((addr & 0xffc0) == 0x2140) { //$2140-$217f
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synchronize_smp();
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return smp.port_read(addr & 3);
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}
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//DMA
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if((addr & 0xff80) == 0x4300) { //$4300-$437f
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unsigned i = (addr >> 4) & 7;
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switch(addr & 0xf) {
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case 0x0: return mmio_r43x0(i);
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case 0x1: return mmio_r43x1(i);
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case 0x2: return mmio_r43x2(i);
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case 0x3: return mmio_r43x3(i);
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case 0x4: return mmio_r43x4(i);
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case 0x5: return mmio_r43x5(i);
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case 0x6: return mmio_r43x6(i);
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case 0x7: return mmio_r43x7(i);
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case 0x8: return mmio_r43x8(i);
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case 0x9: return mmio_r43x9(i);
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case 0xa: return mmio_r43xa(i);
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case 0xb: return mmio_r43xb(i);
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case 0xc: return regs.mdr; //unmapped
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case 0xd: return regs.mdr; //unmapped
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case 0xe: return regs.mdr; //unmapped
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case 0xf: return mmio_r43xb(i); //mirror of $43xb
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}
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}
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switch(addr) {
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case 0x2180: return mmio_r2180();
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case 0x4016: return mmio_r4016();
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case 0x4017: return mmio_r4017();
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case 0x4210: return mmio_r4210();
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case 0x4211: return mmio_r4211();
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case 0x4212: return mmio_r4212();
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case 0x4213: return mmio_r4213();
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case 0x4214: return mmio_r4214();
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case 0x4215: return mmio_r4215();
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case 0x4216: return mmio_r4216();
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case 0x4217: return mmio_r4217();
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case 0x4218: return mmio_r4218();
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case 0x4219: return mmio_r4219();
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case 0x421a: return mmio_r421a();
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case 0x421b: return mmio_r421b();
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case 0x421c: return mmio_r421c();
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case 0x421d: return mmio_r421d();
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case 0x421e: return mmio_r421e();
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case 0x421f: return mmio_r421f();
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}
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return regs.mdr;
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}
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void CPU::mmio_write(unsigned addr, uint8 data) {
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addr &= 0xffff;
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//APU
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if((addr & 0xffc0) == 0x2140) { //$2140-$217f
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synchronize_smp();
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port_write(addr & 3, data);
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return;
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}
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//DMA
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if((addr & 0xff80) == 0x4300) { //$4300-$437f
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unsigned i = (addr >> 4) & 7;
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switch(addr & 0xf) {
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case 0x0: mmio_w43x0(i, data); return;
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case 0x1: mmio_w43x1(i, data); return;
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case 0x2: mmio_w43x2(i, data); return;
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case 0x3: mmio_w43x3(i, data); return;
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case 0x4: mmio_w43x4(i, data); return;
|
|
case 0x5: mmio_w43x5(i, data); return;
|
|
case 0x6: mmio_w43x6(i, data); return;
|
|
case 0x7: mmio_w43x7(i, data); return;
|
|
case 0x8: mmio_w43x8(i, data); return;
|
|
case 0x9: mmio_w43x9(i, data); return;
|
|
case 0xa: mmio_w43xa(i, data); return;
|
|
case 0xb: mmio_w43xb(i, data); return;
|
|
case 0xc: return; //unmapped
|
|
case 0xd: return; //unmapped
|
|
case 0xe: return; //unmapped
|
|
case 0xf: mmio_w43xb(i, data); return; //mirror of $43xb
|
|
}
|
|
}
|
|
|
|
switch(addr) {
|
|
case 0x2180: mmio_w2180(data); return;
|
|
case 0x2181: mmio_w2181(data); return;
|
|
case 0x2182: mmio_w2182(data); return;
|
|
case 0x2183: mmio_w2183(data); return;
|
|
case 0x4016: mmio_w4016(data); return;
|
|
case 0x4017: return; //unmapped
|
|
case 0x4200: mmio_w4200(data); return;
|
|
case 0x4201: mmio_w4201(data); return;
|
|
case 0x4202: mmio_w4202(data); return;
|
|
case 0x4203: mmio_w4203(data); return;
|
|
case 0x4204: mmio_w4204(data); return;
|
|
case 0x4205: mmio_w4205(data); return;
|
|
case 0x4206: mmio_w4206(data); return;
|
|
case 0x4207: mmio_w4207(data); return;
|
|
case 0x4208: mmio_w4208(data); return;
|
|
case 0x4209: mmio_w4209(data); return;
|
|
case 0x420a: mmio_w420a(data); return;
|
|
case 0x420b: mmio_w420b(data); return;
|
|
case 0x420c: mmio_w420c(data); return;
|
|
case 0x420d: mmio_w420d(data); return;
|
|
}
|
|
}
|
|
|
|
#endif
|