mirror of https://github.com/bsnes-emu/bsnes.git
264 lines
6.4 KiB
C++
264 lines
6.4 KiB
C++
auto APU::readIO(uint32 addr) -> uint8 {
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switch(addr) {
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//NR10
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case 0x0400'0060: return square1.read(0);
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case 0x0400'0061: return 0x00;
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//NR11, NR12
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case 0x0400'0062: return square1.read(1);
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case 0x0400'0063: return square1.read(2);
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//NR13, NR14
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case 0x0400'0064: return square1.read(3);
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case 0x0400'0065: return square1.read(4);
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//zero
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case 0x0400'0066: return 0x00;
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case 0x0400'0067: return 0x00;
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//NR21, NR22
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case 0x0400'0068: return square2.read(1);
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case 0x0400'0069: return square2.read(2);
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//NR23, NR24
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case 0x0400'006c: return square2.read(3);
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case 0x0400'006d: return square2.read(4);
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//zero
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case 0x0400'006e: return 0x00;
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case 0x0400'006f: return 0x00;
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//NR30
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case 0x0400'0070: return wave.read(0);
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case 0x0400'0071: return 0x00;
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//NR31, NR32
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case 0x0400'0072: return wave.read(1);
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case 0x0400'0073: return wave.read(2);
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//NR33, NR34
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case 0x0400'0074: return wave.read(3);
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case 0x0400'0075: return wave.read(4);
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//zero
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case 0x0400'0076: return 0x00;
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case 0x0400'0077: return 0x00;
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//NR41, NR42
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case 0x0400'0078: return noise.read(1);
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case 0x0400'0079: return noise.read(2);
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//zero
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case 0x0400'007a: return 0x00;
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case 0x0400'007b: return 0x00;
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//NR43, NR44
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case 0x0400'007c: return noise.read(3);
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case 0x0400'007d: return noise.read(4);
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//zero
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case 0x0400'007e: return 0x00;
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case 0x0400'007f: return 0x00;
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//NR50, NR51
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case 0x0400'0080: return sequencer.read(0);
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case 0x0400'0081: return sequencer.read(1);
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//SOUND_CNT_H
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case 0x0400'0082: return (
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sequencer.volume << 0
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| fifo[0].volume << 2
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| fifo[1].volume << 3
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);
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case 0x0400'0083: return (
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fifo[0].renable << 0
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| fifo[0].lenable << 1
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| fifo[0].timer << 2
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| fifo[1].renable << 4
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| fifo[1].lenable << 5
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| fifo[1].timer << 6
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);
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//NR52
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case 0x0400'0084: return sequencer.read(2);
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case 0x0400'0085: return 0x00;
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//zero
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case 0x0400'0086: return 0x00;
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case 0x0400'0087: return 0x00;
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//SOUNDBIAS
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case 0x0400'0088: return (
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regs.bias.level.bits(0,7)
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);
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case 0x0400'0089: return (
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regs.bias.level.bits(8,9) << 0
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| regs.bias.amplitude << 6
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);
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//zero
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case 0x0400'008a: return 0x00;
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case 0x0400'008b: return 0x00;
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//WAVE_RAM0_L
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case 0x0400'0090: return wave.readram( 0);
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case 0x0400'0091: return wave.readram( 1);
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//WAVE_RAM0_H
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case 0x0400'0092: return wave.readram( 2);
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case 0x0400'0093: return wave.readram( 3);
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//WAVE_RAM1_L
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case 0x0400'0094: return wave.readram( 4);
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case 0x0400'0095: return wave.readram( 5);
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//WAVE_RAM1_H
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case 0x0400'0096: return wave.readram( 6);
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case 0x0400'0097: return wave.readram( 7);
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//WAVE_RAM2_L
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case 0x0400'0098: return wave.readram( 8);
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case 0x0400'0099: return wave.readram( 9);
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//WAVE_RAM2_H
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case 0x0400'009a: return wave.readram(10);
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case 0x0400'009b: return wave.readram(11);
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//WAVE_RAM3_L
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case 0x0400'009c: return wave.readram(12);
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case 0x0400'009d: return wave.readram(13);
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//WAVE_RAM3_H
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case 0x0400'009e: return wave.readram(14);
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case 0x0400'009f: return wave.readram(15);
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}
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return cpu.pipeline.fetch.instruction.byte(addr & 1);
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}
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auto APU::writeIO(uint32 addr, uint8 data) -> void {
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switch(addr) {
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//NR10
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case 0x0400'0060: return square1.write(0, data);
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case 0x0400'0061: return;
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//NR11, NR12
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case 0x0400'0062: return square1.write(1, data);
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case 0x0400'0063: return square1.write(2, data);
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//NR13, NR14
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case 0x0400'0064: return square1.write(3, data);
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case 0x0400'0065: return square1.write(4, data);
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//NR21, NR22
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case 0x0400'0068: return square2.write(1, data);
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case 0x0400'0069: return square2.write(2, data);
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//NR23, NR24
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case 0x0400'006c: return square2.write(3, data);
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case 0x0400'006d: return square2.write(4, data);
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//NR30
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case 0x0400'0070: return wave.write(0, data);
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case 0x0400'0071: return;
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//NR31, NR32
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case 0x0400'0072: return wave.write(1, data);
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case 0x0400'0073: return wave.write(2, data);
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//NR33, NR34
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case 0x0400'0074: return wave.write(3, data);
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case 0x0400'0075: return wave.write(4, data);
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//NR41, NR42
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case 0x0400'0078: return noise.write(1, data);
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case 0x0400'0079: return noise.write(2, data);
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//NR43, NR44
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case 0x0400'007c: return noise.write(3, data);
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case 0x0400'007d: return noise.write(4, data);
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//NR50, NR51
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case 0x0400'0080: return sequencer.write(0, data);
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case 0x0400'0081: return sequencer.write(1, data);
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//SOUND_CNT_H
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case 0x0400'0082:
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sequencer.volume = data.bits(0,1);
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fifo[0].volume = data.bit (2);
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fifo[1].volume = data.bit (3);
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return;
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case 0x0400'0083:
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fifo[0].renable = data.bit(0);
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fifo[0].lenable = data.bit(1);
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fifo[0].timer = data.bit(2);
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if(data.bit(3)) fifo[0].reset();
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fifo[1].renable = data.bit(4);
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fifo[1].lenable = data.bit(5);
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fifo[1].timer = data.bit(6);
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if(data.bit(7)) fifo[1].reset();
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return;
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//NR52
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case 0x0400'0084: return sequencer.write(2, data);
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case 0x0400'0085: return;
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//SOUNDBIAS
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case 0x0400'0088:
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regs.bias.level.bits(0,7) = data;
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return;
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case 0x0400'0089:
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regs.bias.level.bits(8,9) = data.bits(0,1);
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regs.bias.amplitude = data.bits(6,7);
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return;
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//WAVE_RAM0_L
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case 0x0400'0090: return wave.writeram( 0, data);
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case 0x0400'0091: return wave.writeram( 1, data);
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//WAVE_RAM0_H
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case 0x0400'0092: return wave.writeram( 2, data);
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case 0x0400'0093: return wave.writeram( 3, data);
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//WAVE_RAM1_L
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case 0x0400'0094: return wave.writeram( 4, data);
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case 0x0400'0095: return wave.writeram( 5, data);
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//WAVE_RAM1_H
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case 0x0400'0096: return wave.writeram( 6, data);
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case 0x0400'0097: return wave.writeram( 7, data);
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//WAVE_RAM2_L
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case 0x0400'0098: return wave.writeram( 8, data);
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case 0x0400'0099: return wave.writeram( 9, data);
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//WAVE_RAM2_H
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case 0x0400'009a: return wave.writeram(10, data);
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case 0x0400'009b: return wave.writeram(11, data);
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//WAVE_RAM3_L
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case 0x0400'009c: return wave.writeram(12, data);
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case 0x0400'009d: return wave.writeram(13, data);
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//WAVE_RAM3_H
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case 0x0400'009e: return wave.writeram(14, data);
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case 0x0400'009f: return wave.writeram(15, data);
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//FIFO_A_L
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//FIFO_A_H
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case 0x0400'00a0: case 0x0400'00a1:
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case 0x0400'00a2: case 0x0400'00a3:
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return fifo[0].write(data);
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//FIFO_B_L
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//FIFO_B_H
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case 0x0400'00a4: case 0x0400'00a5:
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case 0x0400'00a6: case 0x0400'00a7:
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return fifo[1].write(data);
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}
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}
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