mirror of https://github.com/bsnes-emu/bsnes.git
150 lines
4.0 KiB
C++
150 lines
4.0 KiB
C++
#include <sfc/sfc.hpp>
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namespace SuperFamicom {
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SDD1 sdd1;
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#include "decompressor.cpp"
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#include "serialization.cpp"
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auto SDD1::init() -> void {
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}
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void SDD1::load() {
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}
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auto SDD1::unload() -> void {
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rom.reset();
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ram.reset();
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}
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auto SDD1::power() -> void {
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//hook S-CPU DMA MMIO registers to gather information for struct dma[];
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//buffer address and transfer size information for use in SDD1::mcu_read()
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bus.map({&SDD1::dmaRead, &sdd1}, {&SDD1::dmaWrite, &sdd1}, "00-3f,80-bf:4300-437f");
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r4800 = 0x00;
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r4801 = 0x00;
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r4804 = 0x00;
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r4805 = 0x01;
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r4806 = 0x02;
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r4807 = 0x03;
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for(auto n : range(8)) {
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dma[n].addr = 0;
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dma[n].size = 0;
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}
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dmaReady = false;
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}
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auto SDD1::read(uint24 addr, uint8 data) -> uint8 {
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addr = 0x4800 | addr.bits(0,3);
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switch(addr) {
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case 0x4800: return r4800;
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case 0x4801: return r4801;
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case 0x4804: return r4804;
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case 0x4805: return r4805;
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case 0x4806: return r4806;
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case 0x4807: return r4807;
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}
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//00-3f,80-bf:4802-4803,4808-480f falls through to ROM
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return rom.read(addr);
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}
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auto SDD1::write(uint24 addr, uint8 data) -> void {
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addr = 0x4800 | addr.bits(0,3);
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switch(addr) {
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case 0x4800: r4800 = data; break;
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case 0x4801: r4801 = data; break;
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case 0x4804: r4804 = data & 0x8f; break;
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case 0x4805: r4805 = data & 0x8f; break;
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case 0x4806: r4806 = data & 0x8f; break;
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case 0x4807: r4807 = data & 0x8f; break;
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}
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}
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auto SDD1::dmaRead(uint24 addr, uint8 data) -> uint8 {
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return cpu.readDMA(addr, data);
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}
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auto SDD1::dmaWrite(uint24 addr, uint8 data) -> void {
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uint channel = addr.bits(4,6);
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switch(addr.bits(0,3)) {
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case 2: dma[channel].addr.byte(0) = data; break;
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case 3: dma[channel].addr.byte(1) = data; break;
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case 4: dma[channel].addr.byte(2) = data; break;
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case 5: dma[channel].size.byte(0) = data; break;
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case 6: dma[channel].size.byte(1) = data; break;
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}
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return cpu.writeDMA(addr, data);
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}
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auto SDD1::mmcRead(uint24 addr) -> uint8 {
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switch(addr.bits(20,21)) {
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case 0: return rom.read(r4804.bits(0,3) << 20 | addr.bits(0,19)); //c0-cf:0000-ffff
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case 1: return rom.read(r4805.bits(0,3) << 20 | addr.bits(0,19)); //d0-df:0000-ffff
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case 2: return rom.read(r4806.bits(0,3) << 20 | addr.bits(0,19)); //e0-ef:0000-ffff
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case 3: return rom.read(r4807.bits(0,3) << 20 | addr.bits(0,19)); //f0-ff:0000-ffff
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}
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unreachable;
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}
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//map address=00-3f,80-bf:8000-ffff
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//map address=c0-ff:0000-ffff
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auto SDD1::mcuromRead(uint24 addr, uint8 data) -> uint8 {
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//map address=00-3f,80-bf:8000-ffff
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if(!addr.bit(22)) {
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if(!addr.bit(23) && addr.bit(21) && r4805.bit(7)) addr.bit(21) = 0; //20-3f:8000-ffff
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if( addr.bit(23) && addr.bit(21) && r4807.bit(7)) addr.bit(21) = 0; //a0-bf:8000-ffff
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addr = addr.bits(16,21) << 15 | addr.bits(0,14);
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return rom.read(addr);
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}
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//map address=c0-ff:0000-ffff
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if(r4800 & r4801) {
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//at least one channel has S-DD1 decompression enabled ...
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for(auto n : range(8)) {
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if(r4800.bit(n) && r4801.bit(n)) {
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//S-DD1 always uses fixed transfer mode, so address will not change during transfer
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if(addr == dma[n].addr) {
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if(!dmaReady) {
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//prepare streaming decompression
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decompressor.init(addr);
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dmaReady = true;
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}
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//fetch a decompressed byte; once finished, disable channel and invalidate buffer
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data = decompressor.read();
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if(--dma[n].size == 0) {
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dmaReady = false;
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r4801.bit(n) = 0;
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}
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return data;
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} //address matched
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} //channel enabled
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} //channel loop
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} //S-DD1 decompressor enabled
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//S-DD1 decompression mode inactive; return ROM data
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return mmcRead(addr);
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}
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auto SDD1::mcuromWrite(uint24 addr, uint8 data) -> void {
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}
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//map address=00-3f,80-bf:6000-7fff mask=0xe000
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//map address=70-73:0000-ffff mask=0x8000
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auto SDD1::mcuramRead(uint24 addr, uint8 data) -> uint8 {
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return ram.read(addr.bits(0,12), data);
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}
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auto SDD1::mcuramWrite(uint24 addr, uint8 data) -> void {
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return ram.write(addr.bits(0,12), data);
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}
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}
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