mirror of https://github.com/bsnes-emu/bsnes.git
Update to v101r28 release.
byuu says:
Changelog:
- SMS: emulated the remaining 240 instructions in the (0xfd, 0xdd)
0xcb (displacement) (opcode) set
- 1/8th of these were "legal" instructions, and apparently games
use them a lot
- SMS: emulated the standard gamepad controllers
- reset button not emulated yet
The reset button is tricky. In every other case, reset is a hardware
thing that instantly reboots the entire machine.
But on the SMS, it's more like a gamepad button that's attached to the
front of the device. When you press it, it fires off a reset vector
interrupt and the gamepad polling routine lets you query the status of
the button.
Just having a reset option in the "Master System" hardware menu is not
sufficient to fully emulate the behavior. Even more annoying is that the
Game Gear doesn't have such a button, yet the core information structs
aren't flexible enough for the Master System to have it, and the Game
Gear to not have it, in the main menu. But that doesn't matter anyway,
since it won't work having it in the menu for the Master System.
So as a result, I'm going to have to have a new "input device" called
"Hardware" that has the "Reset" button listed under there. And for the
sake of consistency, I'm not sure if we should treat the other systems
the same way or not :/
This commit is contained in:
Tim Allen
parent
569f5abc28
commit
a3aea95e6b
|
|
@ -12,7 +12,7 @@ using namespace nall;
|
|||
|
||||
namespace Emulator {
|
||||
static const string Name = "higan";
|
||||
static const string Version = "101.27";
|
||||
static const string Version = "101.28";
|
||||
static const string Author = "byuu";
|
||||
static const string License = "GPLv3";
|
||||
static const string Website = "http://byuu.org/";
|
||||
|
|
|
|||
|
|
@ -3,11 +3,13 @@ processors += z80
|
|||
objects += ms-interface
|
||||
objects += ms-cpu ms-vdp ms-psg
|
||||
objects += ms-system ms-cartridge ms-bus
|
||||
objects += ms-controller
|
||||
|
||||
obj/ms-interface.o: ms/interface/interface.cpp $(call rwildcard,ms/interface)
|
||||
obj/ms-cpu.o: ms/cpu/cpu.cpp $(call rwildcard,ms/cpu)
|
||||
obj/ms-vdp.o: ms/vdp/vdp.cpp $(call rwildcard,ms/vdp)
|
||||
obj/ms-psg.o: ms/psg/psg.cpp $(call rwildcard,ms/psg)
|
||||
obj/ms-system.o: ms/system/system.cpp $(call rwildcard,ms/system)
|
||||
obj/ms-cartridge.o: ms/cartridge/cartridge.cpp $(call rwildcard,ms/cartridge)
|
||||
obj/ms-bus.o: ms/bus/bus.cpp $(call rwildcard,ms/bus)
|
||||
obj/ms-interface.o: ms/interface/interface.cpp $(call rwildcard,ms/interface)
|
||||
obj/ms-cpu.o: ms/cpu/cpu.cpp $(call rwildcard,ms/cpu)
|
||||
obj/ms-vdp.o: ms/vdp/vdp.cpp $(call rwildcard,ms/vdp)
|
||||
obj/ms-psg.o: ms/psg/psg.cpp $(call rwildcard,ms/psg)
|
||||
obj/ms-system.o: ms/system/system.cpp $(call rwildcard,ms/system)
|
||||
obj/ms-cartridge.o: ms/cartridge/cartridge.cpp $(call rwildcard,ms/cartridge)
|
||||
obj/ms-bus.o: ms/bus/bus.cpp $(call rwildcard,ms/bus)
|
||||
obj/ms-controller.o: ms/controller/controller.cpp $(call rwildcard,ms/controller)
|
||||
|
|
|
|||
|
|
@ -30,6 +30,18 @@ auto Bus::in(uint8 addr) -> uint8 {
|
|||
return !addr.bit(0) ? vdp.data() : vdp.status();
|
||||
}
|
||||
|
||||
case 3: {
|
||||
auto A = peripherals.controllerPort1->readData();
|
||||
auto B = peripherals.controllerPort2->readData();
|
||||
if(addr.bit(0) == 0) {
|
||||
return A.bits(0,5) << 0 | B.bits(0,1) << 6;
|
||||
} else {
|
||||
//d4 = reset button
|
||||
//d5 = cartridge CONT pin
|
||||
return B.bits(2,5) << 0 | 1 << 4 | 1 << 5 | A.bit(6) << 6 | B.bit(6) << 7;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return 0xff;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
#include <ms/ms.hpp>
|
||||
|
||||
namespace MasterSystem {
|
||||
|
||||
#include "gamepad/gamepad.cpp"
|
||||
|
||||
Controller::Controller(uint port) : port(port) {
|
||||
if(!handle()) create(Controller::Enter, 100);
|
||||
}
|
||||
|
||||
Controller::~Controller() {
|
||||
}
|
||||
|
||||
auto Controller::Enter() -> void {
|
||||
while(true) {
|
||||
scheduler.synchronize();
|
||||
if(peripherals.controllerPort1->active()) peripherals.controllerPort1->main();
|
||||
if(peripherals.controllerPort2->active()) peripherals.controllerPort2->main();
|
||||
}
|
||||
}
|
||||
|
||||
auto Controller::main() -> void {
|
||||
step(1);
|
||||
synchronize(cpu);
|
||||
}
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
struct Controller : Thread {
|
||||
Controller(uint port);
|
||||
virtual ~Controller();
|
||||
|
||||
static auto Enter() -> void;
|
||||
auto main() -> void;
|
||||
|
||||
virtual auto readData() -> uint7 { return 0x7f; }
|
||||
|
||||
const uint port;
|
||||
};
|
||||
|
||||
#include "gamepad/gamepad.hpp"
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
Gamepad::Gamepad(uint port) : Controller(port) {
|
||||
}
|
||||
|
||||
auto Gamepad::readData() -> uint7 {
|
||||
uint7 data;
|
||||
|
||||
data.bit(0) = !interface->inputPoll(port, ID::Device::Gamepad, Up);
|
||||
data.bit(1) = !interface->inputPoll(port, ID::Device::Gamepad, Down);
|
||||
data.bit(2) = !interface->inputPoll(port, ID::Device::Gamepad, Left);
|
||||
data.bit(3) = !interface->inputPoll(port, ID::Device::Gamepad, Right);
|
||||
data.bit(4) = !interface->inputPoll(port, ID::Device::Gamepad, One);
|
||||
data.bit(5) = !interface->inputPoll(port, ID::Device::Gamepad, Two);
|
||||
data.bit(6) = 1;
|
||||
|
||||
return data;
|
||||
}
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
struct Gamepad : Controller {
|
||||
enum : uint {
|
||||
Up, Down, Left, Right, One, Two,
|
||||
};
|
||||
|
||||
Gamepad(uint port);
|
||||
|
||||
auto readData() -> uint7 override;
|
||||
};
|
||||
|
|
@ -9,7 +9,7 @@ auto CPU::Enter() -> void {
|
|||
}
|
||||
|
||||
auto CPU::main() -> void {
|
||||
#if 1
|
||||
#if 0
|
||||
static uint64 instructionsExecuted = 0;
|
||||
if(instructionsExecuted < 20)
|
||||
print(disassemble(r.pc), "\n");
|
||||
|
|
@ -35,6 +35,7 @@ auto CPU::step(uint clocks) -> void {
|
|||
Thread::step(clocks);
|
||||
synchronize(vdp);
|
||||
synchronize(psg);
|
||||
for(auto peripheral : peripherals) synchronize(*peripheral);
|
||||
}
|
||||
|
||||
auto CPU::setNMI(bool value) -> void {
|
||||
|
|
|
|||
|
|
@ -11,6 +11,8 @@ struct CPU : Processor::Z80, Thread {
|
|||
auto power() -> void;
|
||||
auto reset() -> void;
|
||||
|
||||
vector<Thread*> peripherals;
|
||||
|
||||
private:
|
||||
struct State {
|
||||
boolean nmiLine;
|
||||
|
|
|
|||
|
|
@ -22,6 +22,11 @@ Interface::Interface() {
|
|||
Port controllerPort1{ID::Port::Controller1, "Controller Port 1"};
|
||||
Port controllerPort2{ID::Port::Controller2, "Controller Port 2"};
|
||||
|
||||
{ Device device{ID::Device::None, "None"};
|
||||
controllerPort1.devices.append(device);
|
||||
controllerPort2.devices.append(device);
|
||||
}
|
||||
|
||||
{ Device device{ID::Device::Gamepad, "Gamepad"};
|
||||
device.inputs.append({0, "Up"});
|
||||
device.inputs.append({0, "Down"});
|
||||
|
|
@ -99,6 +104,10 @@ auto Interface::unload() -> void {
|
|||
system.unload();
|
||||
}
|
||||
|
||||
auto Interface::connect(uint port, uint device) -> void {
|
||||
MasterSystem::peripherals.connect(port, device);
|
||||
}
|
||||
|
||||
auto Interface::power() -> void {
|
||||
system.power();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@ struct ID {
|
|||
};};
|
||||
|
||||
struct Device { enum : uint {
|
||||
None,
|
||||
Gamepad,
|
||||
};};
|
||||
};
|
||||
|
|
@ -38,6 +39,7 @@ struct Interface : Emulator::Interface {
|
|||
auto save() -> void override;
|
||||
auto unload() -> void override;
|
||||
|
||||
auto connect(uint port, uint device) -> void override;
|
||||
auto power() -> void override;
|
||||
auto reset() -> void override;
|
||||
auto run() -> void override;
|
||||
|
|
@ -51,6 +53,8 @@ struct Interface : Emulator::Interface {
|
|||
};
|
||||
|
||||
struct Settings {
|
||||
uint controllerPort1 = 0;
|
||||
uint controllerPort2 = 0;
|
||||
};
|
||||
|
||||
extern Interface* interface;
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ namespace MasterSystem {
|
|||
}
|
||||
};
|
||||
|
||||
#include <ms/controller/controller.hpp>
|
||||
|
||||
#include <ms/cpu/cpu.hpp>
|
||||
#include <ms/vdp/vdp.hpp>
|
||||
#include <ms/psg/psg.hpp>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,41 @@
|
|||
Peripherals peripherals;
|
||||
|
||||
auto Peripherals::unload() -> void {
|
||||
delete controllerPort1;
|
||||
delete controllerPort2;
|
||||
controllerPort1 = nullptr;
|
||||
controllerPort2 = nullptr;
|
||||
}
|
||||
|
||||
auto Peripherals::reset() -> void {
|
||||
connect(ID::Port::Controller1, settings.controllerPort1);
|
||||
connect(ID::Port::Controller2, settings.controllerPort2);
|
||||
}
|
||||
|
||||
auto Peripherals::connect(uint port, uint device) -> void {
|
||||
if(port == ID::Port::Controller1) {
|
||||
settings.controllerPort1 = device;
|
||||
if(!system.loaded()) return;
|
||||
|
||||
delete controllerPort1;
|
||||
switch(device) { default:
|
||||
case ID::Device::None: controllerPort1 = new Controller(0); break;
|
||||
case ID::Device::Gamepad: controllerPort1 = new Gamepad(0); break;
|
||||
}
|
||||
}
|
||||
|
||||
if(port == ID::Port::Controller2) {
|
||||
settings.controllerPort2 = device;
|
||||
if(!system.loaded()) return;
|
||||
|
||||
delete controllerPort2;
|
||||
switch(device) { default:
|
||||
case ID::Device::None: controllerPort2 = new Controller(1); break;
|
||||
case ID::Device::Gamepad: controllerPort2 = new Gamepad(1); break;
|
||||
}
|
||||
}
|
||||
|
||||
cpu.peripherals.reset();
|
||||
cpu.peripherals.append(controllerPort1);
|
||||
cpu.peripherals.append(controllerPort2);
|
||||
}
|
||||
|
|
@ -2,6 +2,7 @@
|
|||
|
||||
namespace MasterSystem {
|
||||
|
||||
#include "peripherals.cpp"
|
||||
System system;
|
||||
Scheduler scheduler;
|
||||
|
||||
|
|
@ -29,6 +30,7 @@ auto System::save() -> void {
|
|||
}
|
||||
|
||||
auto System::unload() -> void {
|
||||
peripherals.unload();
|
||||
cartridge.unload();
|
||||
}
|
||||
|
||||
|
|
@ -54,6 +56,8 @@ auto System::reset() -> void {
|
|||
vdp.reset();
|
||||
psg.reset();
|
||||
scheduler.primary(cpu);
|
||||
|
||||
peripherals.reset();
|
||||
}
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,4 +21,14 @@ private:
|
|||
} information;
|
||||
};
|
||||
|
||||
struct Peripherals {
|
||||
auto unload() -> void;
|
||||
auto reset() -> void;
|
||||
auto connect(uint port, uint device) -> void;
|
||||
|
||||
Controller* controllerPort1 = nullptr;
|
||||
Controller* controllerPort2 = nullptr;
|
||||
};
|
||||
|
||||
extern System system;
|
||||
extern Peripherals peripherals;
|
||||
|
|
|
|||
|
|
@ -464,198 +464,198 @@ auto Z80::disassembleCB(uint16 pc, uint8 prefix, uint8 code) -> string {
|
|||
op(0x3d, "srl ", L)
|
||||
op(0x3e, "srl ", IHL)
|
||||
op(0x3f, "srl ", A)
|
||||
op(0x40, "bit ", "0,", B)
|
||||
op(0x41, "bit ", "0,", C)
|
||||
op(0x42, "bit ", "0,", D)
|
||||
op(0x43, "bit ", "0,", E)
|
||||
op(0x44, "bit ", "0,", H)
|
||||
op(0x45, "bit ", "0,", L)
|
||||
op(0x46, "bit ", "0,", IHL)
|
||||
op(0x47, "bit ", "0,", A)
|
||||
op(0x48, "bit ", "1,", B)
|
||||
op(0x49, "bit ", "1,", C)
|
||||
op(0x4a, "bit ", "1,", D)
|
||||
op(0x4b, "bit ", "1,", E)
|
||||
op(0x4c, "bit ", "1,", H)
|
||||
op(0x4d, "bit ", "1,", L)
|
||||
op(0x4e, "bit ", "1,", IHL)
|
||||
op(0x4f, "bit ", "1,", A)
|
||||
op(0x50, "bit ", "2,", B)
|
||||
op(0x51, "bit ", "2,", C)
|
||||
op(0x52, "bit ", "2,", D)
|
||||
op(0x53, "bit ", "2,", E)
|
||||
op(0x54, "bit ", "2,", H)
|
||||
op(0x55, "bit ", "2,", L)
|
||||
op(0x56, "bit ", "2,", IHL)
|
||||
op(0x57, "bit ", "2,", A)
|
||||
op(0x58, "bit ", "3,", B)
|
||||
op(0x59, "bit ", "3,", C)
|
||||
op(0x5a, "bit ", "3,", D)
|
||||
op(0x5b, "bit ", "3,", E)
|
||||
op(0x5c, "bit ", "3,", H)
|
||||
op(0x5d, "bit ", "3,", L)
|
||||
op(0x5e, "bit ", "3,", IHL)
|
||||
op(0x5f, "bit ", "3,", A)
|
||||
op(0x60, "bit ", "4,", B)
|
||||
op(0x61, "bit ", "4,", C)
|
||||
op(0x62, "bit ", "4,", D)
|
||||
op(0x63, "bit ", "4,", E)
|
||||
op(0x64, "bit ", "4,", H)
|
||||
op(0x65, "bit ", "4,", L)
|
||||
op(0x66, "bit ", "4,", IHL)
|
||||
op(0x67, "bit ", "4,", A)
|
||||
op(0x68, "bit ", "5,", B)
|
||||
op(0x69, "bit ", "5,", C)
|
||||
op(0x6a, "bit ", "5,", D)
|
||||
op(0x6b, "bit ", "5,", E)
|
||||
op(0x6c, "bit ", "5,", H)
|
||||
op(0x6d, "bit ", "5,", L)
|
||||
op(0x6e, "bit ", "5,", IHL)
|
||||
op(0x6f, "bit ", "5,", A)
|
||||
op(0x70, "bit ", "6,", B)
|
||||
op(0x71, "bit ", "6,", C)
|
||||
op(0x72, "bit ", "6,", D)
|
||||
op(0x73, "bit ", "6,", E)
|
||||
op(0x74, "bit ", "6,", H)
|
||||
op(0x75, "bit ", "6,", L)
|
||||
op(0x76, "bit ", "6,", IHL)
|
||||
op(0x77, "bit ", "6,", A)
|
||||
op(0x78, "bit ", "7,", B)
|
||||
op(0x79, "bit ", "7,", C)
|
||||
op(0x7a, "bit ", "7,", D)
|
||||
op(0x7b, "bit ", "7,", E)
|
||||
op(0x7c, "bit ", "7,", H)
|
||||
op(0x7d, "bit ", "7,", L)
|
||||
op(0x7e, "bit ", "7,", IHL)
|
||||
op(0x7f, "bit ", "7,", A)
|
||||
op(0x80, "res ", "0,", B)
|
||||
op(0x81, "res ", "0,", C)
|
||||
op(0x82, "res ", "0,", D)
|
||||
op(0x83, "res ", "0,", E)
|
||||
op(0x84, "res ", "0,", H)
|
||||
op(0x85, "res ", "0,", L)
|
||||
op(0x86, "res ", "0,", IHL)
|
||||
op(0x87, "res ", "0,", A)
|
||||
op(0x88, "res ", "1,", B)
|
||||
op(0x89, "res ", "1,", C)
|
||||
op(0x8a, "res ", "1,", D)
|
||||
op(0x8b, "res ", "1,", E)
|
||||
op(0x8c, "res ", "1,", H)
|
||||
op(0x8d, "res ", "1,", L)
|
||||
op(0x8e, "res ", "1,", IHL)
|
||||
op(0x8f, "res ", "1,", A)
|
||||
op(0x90, "res ", "2,", B)
|
||||
op(0x91, "res ", "2,", C)
|
||||
op(0x92, "res ", "2,", D)
|
||||
op(0x93, "res ", "2,", E)
|
||||
op(0x94, "res ", "2,", H)
|
||||
op(0x95, "res ", "2,", L)
|
||||
op(0x96, "res ", "2,", IHL)
|
||||
op(0x97, "res ", "2,", A)
|
||||
op(0x98, "res ", "3,", B)
|
||||
op(0x99, "res ", "3,", C)
|
||||
op(0x9a, "res ", "3,", D)
|
||||
op(0x9b, "res ", "3,", E)
|
||||
op(0x9c, "res ", "3,", H)
|
||||
op(0x9d, "res ", "3,", L)
|
||||
op(0x9e, "res ", "3,", IHL)
|
||||
op(0x9f, "res ", "3,", A)
|
||||
op(0xa0, "res ", "4,", B)
|
||||
op(0xa1, "res ", "4,", C)
|
||||
op(0xa2, "res ", "4,", D)
|
||||
op(0xa3, "res ", "4,", E)
|
||||
op(0xa4, "res ", "4,", H)
|
||||
op(0xa5, "res ", "4,", L)
|
||||
op(0xa6, "res ", "4,", IHL)
|
||||
op(0xa7, "res ", "4,", A)
|
||||
op(0xa8, "res ", "5,", B)
|
||||
op(0xa9, "res ", "5,", C)
|
||||
op(0xaa, "res ", "5,", D)
|
||||
op(0xab, "res ", "5,", E)
|
||||
op(0xac, "res ", "5,", H)
|
||||
op(0xad, "res ", "5,", L)
|
||||
op(0xae, "res ", "5,", IHL)
|
||||
op(0xaf, "res ", "5,", A)
|
||||
op(0xb0, "res ", "6,", B)
|
||||
op(0xb1, "res ", "6,", C)
|
||||
op(0xb2, "res ", "6,", D)
|
||||
op(0xb3, "res ", "6,", E)
|
||||
op(0xb4, "res ", "6,", H)
|
||||
op(0xb5, "res ", "6,", L)
|
||||
op(0xb6, "res ", "6,", IHL)
|
||||
op(0xb7, "res ", "6,", A)
|
||||
op(0xb8, "res ", "7,", B)
|
||||
op(0xb9, "res ", "7,", C)
|
||||
op(0xba, "res ", "7,", D)
|
||||
op(0xbb, "res ", "7,", E)
|
||||
op(0xbc, "res ", "7,", H)
|
||||
op(0xbd, "res ", "7,", L)
|
||||
op(0xbe, "res ", "7,", IHL)
|
||||
op(0xbf, "res ", "7,", A)
|
||||
op(0xc0, "set ", "0,", B)
|
||||
op(0xc1, "set ", "0,", C)
|
||||
op(0xc2, "set ", "0,", D)
|
||||
op(0xc3, "set ", "0,", E)
|
||||
op(0xc4, "set ", "0,", H)
|
||||
op(0xc5, "set ", "0,", L)
|
||||
op(0xc6, "set ", "0,", IHL)
|
||||
op(0xc7, "set ", "0,", A)
|
||||
op(0xc8, "set ", "1,", B)
|
||||
op(0xc9, "set ", "1,", C)
|
||||
op(0xca, "set ", "1,", D)
|
||||
op(0xcb, "set ", "1,", E)
|
||||
op(0xcc, "set ", "1,", H)
|
||||
op(0xcd, "set ", "1,", L)
|
||||
op(0xce, "set ", "1,", IHL)
|
||||
op(0xcf, "set ", "1,", A)
|
||||
op(0xd0, "set ", "2,", B)
|
||||
op(0xd1, "set ", "2,", C)
|
||||
op(0xd2, "set ", "2,", D)
|
||||
op(0xd3, "set ", "2,", E)
|
||||
op(0xd4, "set ", "2,", H)
|
||||
op(0xd5, "set ", "2,", L)
|
||||
op(0xd6, "set ", "2,", IHL)
|
||||
op(0xd7, "set ", "2,", A)
|
||||
op(0xd8, "set ", "3,", B)
|
||||
op(0xd9, "set ", "3,", C)
|
||||
op(0xda, "set ", "3,", D)
|
||||
op(0xdb, "set ", "3,", E)
|
||||
op(0xdc, "set ", "3,", H)
|
||||
op(0xdd, "set ", "3,", L)
|
||||
op(0xde, "set ", "3,", IHL)
|
||||
op(0xdf, "set ", "3,", A)
|
||||
op(0xe0, "set ", "4,", B)
|
||||
op(0xe1, "set ", "4,", C)
|
||||
op(0xe2, "set ", "4,", D)
|
||||
op(0xe3, "set ", "4,", E)
|
||||
op(0xe4, "set ", "4,", H)
|
||||
op(0xe5, "set ", "4,", L)
|
||||
op(0xe6, "set ", "4,", IHL)
|
||||
op(0xe7, "set ", "4,", A)
|
||||
op(0xe8, "set ", "5,", B)
|
||||
op(0xe9, "set ", "5,", C)
|
||||
op(0xea, "set ", "5,", D)
|
||||
op(0xeb, "set ", "5,", E)
|
||||
op(0xec, "set ", "5,", H)
|
||||
op(0xed, "set ", "5,", L)
|
||||
op(0xee, "set ", "5,", IHL)
|
||||
op(0xef, "set ", "5,", A)
|
||||
op(0xf0, "set ", "6,", B)
|
||||
op(0xf1, "set ", "6,", C)
|
||||
op(0xf2, "set ", "6,", D)
|
||||
op(0xf3, "set ", "6,", E)
|
||||
op(0xf4, "set ", "6,", H)
|
||||
op(0xf5, "set ", "6,", L)
|
||||
op(0xf6, "set ", "6,", IHL)
|
||||
op(0xf7, "set ", "6,", A)
|
||||
op(0xf8, "set ", "7,", B)
|
||||
op(0xf9, "set ", "7,", C)
|
||||
op(0xfa, "set ", "7,", D)
|
||||
op(0xfb, "set ", "7,", E)
|
||||
op(0xfc, "set ", "7,", H)
|
||||
op(0xfd, "set ", "7,", L)
|
||||
op(0xfe, "set ", "7,", IHL)
|
||||
op(0xff, "set ", "7,", A)
|
||||
op(0x40, "bit ", "0", B)
|
||||
op(0x41, "bit ", "0", C)
|
||||
op(0x42, "bit ", "0", D)
|
||||
op(0x43, "bit ", "0", E)
|
||||
op(0x44, "bit ", "0", H)
|
||||
op(0x45, "bit ", "0", L)
|
||||
op(0x46, "bit ", "0", IHL)
|
||||
op(0x47, "bit ", "0", A)
|
||||
op(0x48, "bit ", "1", B)
|
||||
op(0x49, "bit ", "1", C)
|
||||
op(0x4a, "bit ", "1", D)
|
||||
op(0x4b, "bit ", "1", E)
|
||||
op(0x4c, "bit ", "1", H)
|
||||
op(0x4d, "bit ", "1", L)
|
||||
op(0x4e, "bit ", "1", IHL)
|
||||
op(0x4f, "bit ", "1", A)
|
||||
op(0x50, "bit ", "2", B)
|
||||
op(0x51, "bit ", "2", C)
|
||||
op(0x52, "bit ", "2", D)
|
||||
op(0x53, "bit ", "2", E)
|
||||
op(0x54, "bit ", "2", H)
|
||||
op(0x55, "bit ", "2", L)
|
||||
op(0x56, "bit ", "2", IHL)
|
||||
op(0x57, "bit ", "2", A)
|
||||
op(0x58, "bit ", "3", B)
|
||||
op(0x59, "bit ", "3", C)
|
||||
op(0x5a, "bit ", "3", D)
|
||||
op(0x5b, "bit ", "3", E)
|
||||
op(0x5c, "bit ", "3", H)
|
||||
op(0x5d, "bit ", "3", L)
|
||||
op(0x5e, "bit ", "3", IHL)
|
||||
op(0x5f, "bit ", "3", A)
|
||||
op(0x60, "bit ", "4", B)
|
||||
op(0x61, "bit ", "4", C)
|
||||
op(0x62, "bit ", "4", D)
|
||||
op(0x63, "bit ", "4", E)
|
||||
op(0x64, "bit ", "4", H)
|
||||
op(0x65, "bit ", "4", L)
|
||||
op(0x66, "bit ", "4", IHL)
|
||||
op(0x67, "bit ", "4", A)
|
||||
op(0x68, "bit ", "5", B)
|
||||
op(0x69, "bit ", "5", C)
|
||||
op(0x6a, "bit ", "5", D)
|
||||
op(0x6b, "bit ", "5", E)
|
||||
op(0x6c, "bit ", "5", H)
|
||||
op(0x6d, "bit ", "5", L)
|
||||
op(0x6e, "bit ", "5", IHL)
|
||||
op(0x6f, "bit ", "5", A)
|
||||
op(0x70, "bit ", "6", B)
|
||||
op(0x71, "bit ", "6", C)
|
||||
op(0x72, "bit ", "6", D)
|
||||
op(0x73, "bit ", "6", E)
|
||||
op(0x74, "bit ", "6", H)
|
||||
op(0x75, "bit ", "6", L)
|
||||
op(0x76, "bit ", "6", IHL)
|
||||
op(0x77, "bit ", "6", A)
|
||||
op(0x78, "bit ", "7", B)
|
||||
op(0x79, "bit ", "7", C)
|
||||
op(0x7a, "bit ", "7", D)
|
||||
op(0x7b, "bit ", "7", E)
|
||||
op(0x7c, "bit ", "7", H)
|
||||
op(0x7d, "bit ", "7", L)
|
||||
op(0x7e, "bit ", "7", IHL)
|
||||
op(0x7f, "bit ", "7", A)
|
||||
op(0x80, "res ", "0", B)
|
||||
op(0x81, "res ", "0", C)
|
||||
op(0x82, "res ", "0", D)
|
||||
op(0x83, "res ", "0", E)
|
||||
op(0x84, "res ", "0", H)
|
||||
op(0x85, "res ", "0", L)
|
||||
op(0x86, "res ", "0", IHL)
|
||||
op(0x87, "res ", "0", A)
|
||||
op(0x88, "res ", "1", B)
|
||||
op(0x89, "res ", "1", C)
|
||||
op(0x8a, "res ", "1", D)
|
||||
op(0x8b, "res ", "1", E)
|
||||
op(0x8c, "res ", "1", H)
|
||||
op(0x8d, "res ", "1", L)
|
||||
op(0x8e, "res ", "1", IHL)
|
||||
op(0x8f, "res ", "1", A)
|
||||
op(0x90, "res ", "2", B)
|
||||
op(0x91, "res ", "2", C)
|
||||
op(0x92, "res ", "2", D)
|
||||
op(0x93, "res ", "2", E)
|
||||
op(0x94, "res ", "2", H)
|
||||
op(0x95, "res ", "2", L)
|
||||
op(0x96, "res ", "2", IHL)
|
||||
op(0x97, "res ", "2", A)
|
||||
op(0x98, "res ", "3", B)
|
||||
op(0x99, "res ", "3", C)
|
||||
op(0x9a, "res ", "3", D)
|
||||
op(0x9b, "res ", "3", E)
|
||||
op(0x9c, "res ", "3", H)
|
||||
op(0x9d, "res ", "3", L)
|
||||
op(0x9e, "res ", "3", IHL)
|
||||
op(0x9f, "res ", "3", A)
|
||||
op(0xa0, "res ", "4", B)
|
||||
op(0xa1, "res ", "4", C)
|
||||
op(0xa2, "res ", "4", D)
|
||||
op(0xa3, "res ", "4", E)
|
||||
op(0xa4, "res ", "4", H)
|
||||
op(0xa5, "res ", "4", L)
|
||||
op(0xa6, "res ", "4", IHL)
|
||||
op(0xa7, "res ", "4", A)
|
||||
op(0xa8, "res ", "5", B)
|
||||
op(0xa9, "res ", "5", C)
|
||||
op(0xaa, "res ", "5", D)
|
||||
op(0xab, "res ", "5", E)
|
||||
op(0xac, "res ", "5", H)
|
||||
op(0xad, "res ", "5", L)
|
||||
op(0xae, "res ", "5", IHL)
|
||||
op(0xaf, "res ", "5", A)
|
||||
op(0xb0, "res ", "6", B)
|
||||
op(0xb1, "res ", "6", C)
|
||||
op(0xb2, "res ", "6", D)
|
||||
op(0xb3, "res ", "6", E)
|
||||
op(0xb4, "res ", "6", H)
|
||||
op(0xb5, "res ", "6", L)
|
||||
op(0xb6, "res ", "6", IHL)
|
||||
op(0xb7, "res ", "6", A)
|
||||
op(0xb8, "res ", "7", B)
|
||||
op(0xb9, "res ", "7", C)
|
||||
op(0xba, "res ", "7", D)
|
||||
op(0xbb, "res ", "7", E)
|
||||
op(0xbc, "res ", "7", H)
|
||||
op(0xbd, "res ", "7", L)
|
||||
op(0xbe, "res ", "7", IHL)
|
||||
op(0xbf, "res ", "7", A)
|
||||
op(0xc0, "set ", "0", B)
|
||||
op(0xc1, "set ", "0", C)
|
||||
op(0xc2, "set ", "0", D)
|
||||
op(0xc3, "set ", "0", E)
|
||||
op(0xc4, "set ", "0", H)
|
||||
op(0xc5, "set ", "0", L)
|
||||
op(0xc6, "set ", "0", IHL)
|
||||
op(0xc7, "set ", "0", A)
|
||||
op(0xc8, "set ", "1", B)
|
||||
op(0xc9, "set ", "1", C)
|
||||
op(0xca, "set ", "1", D)
|
||||
op(0xcb, "set ", "1", E)
|
||||
op(0xcc, "set ", "1", H)
|
||||
op(0xcd, "set ", "1", L)
|
||||
op(0xce, "set ", "1", IHL)
|
||||
op(0xcf, "set ", "1", A)
|
||||
op(0xd0, "set ", "2", B)
|
||||
op(0xd1, "set ", "2", C)
|
||||
op(0xd2, "set ", "2", D)
|
||||
op(0xd3, "set ", "2", E)
|
||||
op(0xd4, "set ", "2", H)
|
||||
op(0xd5, "set ", "2", L)
|
||||
op(0xd6, "set ", "2", IHL)
|
||||
op(0xd7, "set ", "2", A)
|
||||
op(0xd8, "set ", "3", B)
|
||||
op(0xd9, "set ", "3", C)
|
||||
op(0xda, "set ", "3", D)
|
||||
op(0xdb, "set ", "3", E)
|
||||
op(0xdc, "set ", "3", H)
|
||||
op(0xdd, "set ", "3", L)
|
||||
op(0xde, "set ", "3", IHL)
|
||||
op(0xdf, "set ", "3", A)
|
||||
op(0xe0, "set ", "4", B)
|
||||
op(0xe1, "set ", "4", C)
|
||||
op(0xe2, "set ", "4", D)
|
||||
op(0xe3, "set ", "4", E)
|
||||
op(0xe4, "set ", "4", H)
|
||||
op(0xe5, "set ", "4", L)
|
||||
op(0xe6, "set ", "4", IHL)
|
||||
op(0xe7, "set ", "4", A)
|
||||
op(0xe8, "set ", "5", B)
|
||||
op(0xe9, "set ", "5", C)
|
||||
op(0xea, "set ", "5", D)
|
||||
op(0xeb, "set ", "5", E)
|
||||
op(0xec, "set ", "5", H)
|
||||
op(0xed, "set ", "5", L)
|
||||
op(0xee, "set ", "5", IHL)
|
||||
op(0xef, "set ", "5", A)
|
||||
op(0xf0, "set ", "6", B)
|
||||
op(0xf1, "set ", "6", C)
|
||||
op(0xf2, "set ", "6", D)
|
||||
op(0xf3, "set ", "6", E)
|
||||
op(0xf4, "set ", "6", H)
|
||||
op(0xf5, "set ", "6", L)
|
||||
op(0xf6, "set ", "6", IHL)
|
||||
op(0xf7, "set ", "6", A)
|
||||
op(0xf8, "set ", "7", B)
|
||||
op(0xf9, "set ", "7", C)
|
||||
op(0xfa, "set ", "7", D)
|
||||
op(0xfb, "set ", "7", E)
|
||||
op(0xfc, "set ", "7", H)
|
||||
op(0xfd, "set ", "7", L)
|
||||
op(0xfe, "set ", "7", IHL)
|
||||
op(0xff, "set ", "7", A)
|
||||
}
|
||||
|
||||
unreachable;
|
||||
|
|
@ -683,9 +683,249 @@ auto Z80::disassembleCBd(uint16 pc, uint8 prefix, int8 d, uint8 code) -> string
|
|||
op(0x0d, "rrc ", IHL, L)
|
||||
op(0x0e, "rrc ", IHL)
|
||||
op(0x0f, "rrc ", IHL, A)
|
||||
op(0x10, "rl ", IHL, B)
|
||||
op(0x11, "rl ", IHL, C)
|
||||
op(0x12, "rl ", IHL, D)
|
||||
op(0x13, "rl ", IHL, E)
|
||||
op(0x14, "rl ", IHL, H)
|
||||
op(0x15, "rl ", IHL, L)
|
||||
op(0x16, "rl ", IHL)
|
||||
op(0x17, "rl ", IHL, A)
|
||||
op(0x18, "rr ", IHL, B)
|
||||
op(0x19, "rr ", IHL, C)
|
||||
op(0x1a, "rr ", IHL, D)
|
||||
op(0x1b, "rr ", IHL, E)
|
||||
op(0x1c, "rr ", IHL, H)
|
||||
op(0x1d, "rr ", IHL, L)
|
||||
op(0x1e, "rr ", IHL)
|
||||
op(0x1f, "rr ", IHL, A)
|
||||
op(0x20, "sla ", IHL, B)
|
||||
op(0x21, "sla ", IHL, C)
|
||||
op(0x22, "sla ", IHL, D)
|
||||
op(0x23, "sla ", IHL, E)
|
||||
op(0x24, "sla ", IHL, H)
|
||||
op(0x25, "sla ", IHL, L)
|
||||
op(0x26, "sla ", IHL)
|
||||
op(0x27, "sla ", IHL, A)
|
||||
op(0x28, "sra ", IHL, B)
|
||||
op(0x29, "sra ", IHL, C)
|
||||
op(0x2a, "sra ", IHL, D)
|
||||
op(0x2b, "sra ", IHL, E)
|
||||
op(0x2c, "sra ", IHL, H)
|
||||
op(0x2d, "sra ", IHL, L)
|
||||
op(0x2e, "sra ", IHL)
|
||||
op(0x2f, "sra ", IHL, A)
|
||||
op(0x30, "sll ", IHL, B)
|
||||
op(0x31, "sll ", IHL, C)
|
||||
op(0x32, "sll ", IHL, D)
|
||||
op(0x33, "sll ", IHL, E)
|
||||
op(0x34, "sll ", IHL, H)
|
||||
op(0x35, "sll ", IHL, L)
|
||||
op(0x36, "sll ", IHL)
|
||||
op(0x37, "sll ", IHL, A)
|
||||
op(0x38, "srl ", IHL, B)
|
||||
op(0x39, "srl ", IHL, C)
|
||||
op(0x3a, "srl ", IHL, D)
|
||||
op(0x3b, "srl ", IHL, E)
|
||||
op(0x3c, "srl ", IHL, H)
|
||||
op(0x3d, "srl ", IHL, L)
|
||||
op(0x3e, "srl ", IHL)
|
||||
op(0x3f, "srl ", IHL, A)
|
||||
op(0x40, "bit ", "0", IHL, B)
|
||||
op(0x41, "bit ", "0", IHL, C)
|
||||
op(0x42, "bit ", "0", IHL, D)
|
||||
op(0x43, "bit ", "0", IHL, E)
|
||||
op(0x44, "bit ", "0", IHL, H)
|
||||
op(0x45, "bit ", "0", IHL, L)
|
||||
op(0x46, "bit ", "0", IHL)
|
||||
op(0x47, "bit ", "0", IHL, A)
|
||||
op(0x48, "bit ", "1", IHL, B)
|
||||
op(0x49, "bit ", "1", IHL, C)
|
||||
op(0x4a, "bit ", "1", IHL, D)
|
||||
op(0x4b, "bit ", "1", IHL, E)
|
||||
op(0x4c, "bit ", "1", IHL, H)
|
||||
op(0x4d, "bit ", "1", IHL, L)
|
||||
op(0x4e, "bit ", "1", IHL)
|
||||
op(0x4f, "bit ", "1", IHL, A)
|
||||
op(0x50, "bit ", "2", IHL, B)
|
||||
op(0x51, "bit ", "2", IHL, C)
|
||||
op(0x52, "bit ", "2", IHL, D)
|
||||
op(0x53, "bit ", "2", IHL, E)
|
||||
op(0x54, "bit ", "2", IHL, H)
|
||||
op(0x55, "bit ", "2", IHL, L)
|
||||
op(0x56, "bit ", "2", IHL)
|
||||
op(0x57, "bit ", "2", IHL, A)
|
||||
op(0x58, "bit ", "3", IHL, B)
|
||||
op(0x59, "bit ", "3", IHL, C)
|
||||
op(0x5a, "bit ", "3", IHL, D)
|
||||
op(0x5b, "bit ", "3", IHL, E)
|
||||
op(0x5c, "bit ", "3", IHL, H)
|
||||
op(0x5d, "bit ", "3", IHL, L)
|
||||
op(0x5e, "bit ", "3", IHL)
|
||||
op(0x5f, "bit ", "3", IHL, A)
|
||||
op(0x60, "bit ", "4", IHL, B)
|
||||
op(0x61, "bit ", "4", IHL, C)
|
||||
op(0x62, "bit ", "4", IHL, D)
|
||||
op(0x63, "bit ", "4", IHL, E)
|
||||
op(0x64, "bit ", "4", IHL, H)
|
||||
op(0x65, "bit ", "4", IHL, L)
|
||||
op(0x66, "bit ", "4", IHL)
|
||||
op(0x67, "bit ", "4", IHL, A)
|
||||
op(0x68, "bit ", "5", IHL, B)
|
||||
op(0x69, "bit ", "5", IHL, C)
|
||||
op(0x6a, "bit ", "5", IHL, D)
|
||||
op(0x6b, "bit ", "5", IHL, E)
|
||||
op(0x6c, "bit ", "5", IHL, H)
|
||||
op(0x6d, "bit ", "5", IHL, L)
|
||||
op(0x6e, "bit ", "5", IHL)
|
||||
op(0x6f, "bit ", "5", IHL, A)
|
||||
op(0x70, "bit ", "6", IHL, B)
|
||||
op(0x71, "bit ", "6", IHL, C)
|
||||
op(0x72, "bit ", "6", IHL, D)
|
||||
op(0x73, "bit ", "6", IHL, E)
|
||||
op(0x74, "bit ", "6", IHL, H)
|
||||
op(0x75, "bit ", "6", IHL, L)
|
||||
op(0x76, "bit ", "6", IHL)
|
||||
op(0x77, "bit ", "6", IHL, A)
|
||||
op(0x78, "bit ", "7", IHL, B)
|
||||
op(0x79, "bit ", "7", IHL, C)
|
||||
op(0x7a, "bit ", "7", IHL, D)
|
||||
op(0x7b, "bit ", "7", IHL, E)
|
||||
op(0x7c, "bit ", "7", IHL, H)
|
||||
op(0x7d, "bit ", "7", IHL, L)
|
||||
op(0x7e, "bit ", "7", IHL)
|
||||
op(0x7f, "bit ", "7", IHL, A)
|
||||
op(0x80, "res ", "0", IHL, B)
|
||||
op(0x81, "res ", "0", IHL, C)
|
||||
op(0x82, "res ", "0", IHL, D)
|
||||
op(0x83, "res ", "0", IHL, E)
|
||||
op(0x84, "res ", "0", IHL, H)
|
||||
op(0x85, "res ", "0", IHL, L)
|
||||
op(0x86, "res ", "0", IHL)
|
||||
op(0x87, "res ", "0", IHL, A)
|
||||
op(0x88, "res ", "1", IHL, B)
|
||||
op(0x89, "res ", "1", IHL, C)
|
||||
op(0x8a, "res ", "1", IHL, D)
|
||||
op(0x8b, "res ", "1", IHL, E)
|
||||
op(0x8c, "res ", "1", IHL, H)
|
||||
op(0x8d, "res ", "1", IHL, L)
|
||||
op(0x8e, "res ", "1", IHL)
|
||||
op(0x8f, "res ", "1", IHL, A)
|
||||
op(0x90, "res ", "2", IHL, B)
|
||||
op(0x91, "res ", "2", IHL, C)
|
||||
op(0x92, "res ", "2", IHL, D)
|
||||
op(0x93, "res ", "2", IHL, E)
|
||||
op(0x94, "res ", "2", IHL, H)
|
||||
op(0x95, "res ", "2", IHL, L)
|
||||
op(0x96, "res ", "2", IHL)
|
||||
op(0x97, "res ", "2", IHL, A)
|
||||
op(0x98, "res ", "3", IHL, B)
|
||||
op(0x99, "res ", "3", IHL, C)
|
||||
op(0x9a, "res ", "3", IHL, D)
|
||||
op(0x9b, "res ", "3", IHL, E)
|
||||
op(0x9c, "res ", "3", IHL, H)
|
||||
op(0x9d, "res ", "3", IHL, L)
|
||||
op(0x9e, "res ", "3", IHL)
|
||||
op(0x9f, "res ", "3", IHL, A)
|
||||
op(0xa0, "res ", "4", IHL, B)
|
||||
op(0xa1, "res ", "4", IHL, C)
|
||||
op(0xa2, "res ", "4", IHL, D)
|
||||
op(0xa3, "res ", "4", IHL, E)
|
||||
op(0xa4, "res ", "4", IHL, H)
|
||||
op(0xa5, "res ", "4", IHL, L)
|
||||
op(0xa6, "res ", "4", IHL)
|
||||
op(0xa7, "res ", "4", IHL, A)
|
||||
op(0xa8, "res ", "5", IHL, B)
|
||||
op(0xa9, "res ", "5", IHL, C)
|
||||
op(0xaa, "res ", "5", IHL, D)
|
||||
op(0xab, "res ", "5", IHL, E)
|
||||
op(0xac, "res ", "5", IHL, H)
|
||||
op(0xad, "res ", "5", IHL, L)
|
||||
op(0xae, "res ", "5", IHL)
|
||||
op(0xaf, "res ", "5", IHL, A)
|
||||
op(0xb0, "res ", "6", IHL, B)
|
||||
op(0xb1, "res ", "6", IHL, C)
|
||||
op(0xb2, "res ", "6", IHL, D)
|
||||
op(0xb3, "res ", "6", IHL, E)
|
||||
op(0xb4, "res ", "6", IHL, H)
|
||||
op(0xb5, "res ", "6", IHL, L)
|
||||
op(0xb6, "res ", "6", IHL)
|
||||
op(0xb7, "res ", "6", IHL, A)
|
||||
op(0xb8, "res ", "7", IHL, B)
|
||||
op(0xb9, "res ", "7", IHL, C)
|
||||
op(0xba, "res ", "7", IHL, D)
|
||||
op(0xbb, "res ", "7", IHL, E)
|
||||
op(0xbc, "res ", "7", IHL, H)
|
||||
op(0xbd, "res ", "7", IHL, L)
|
||||
op(0xbe, "res ", "7", IHL)
|
||||
op(0xbf, "res ", "7", IHL, A)
|
||||
op(0xc0, "set ", "0", IHL, B)
|
||||
op(0xc1, "set ", "0", IHL, C)
|
||||
op(0xc2, "set ", "0", IHL, D)
|
||||
op(0xc3, "set ", "0", IHL, E)
|
||||
op(0xc4, "set ", "0", IHL, H)
|
||||
op(0xc5, "set ", "0", IHL, L)
|
||||
op(0xc6, "set ", "0", IHL)
|
||||
op(0xc7, "set ", "0", IHL, A)
|
||||
op(0xc8, "set ", "1", IHL, B)
|
||||
op(0xc9, "set ", "1", IHL, C)
|
||||
op(0xca, "set ", "1", IHL, D)
|
||||
op(0xcb, "set ", "1", IHL, E)
|
||||
op(0xcc, "set ", "1", IHL, H)
|
||||
op(0xcd, "set ", "1", IHL, L)
|
||||
op(0xce, "set ", "1", IHL)
|
||||
op(0xcf, "set ", "1", IHL, A)
|
||||
op(0xd0, "set ", "2", IHL, B)
|
||||
op(0xd1, "set ", "2", IHL, C)
|
||||
op(0xd2, "set ", "2", IHL, D)
|
||||
op(0xd3, "set ", "2", IHL, E)
|
||||
op(0xd4, "set ", "2", IHL, H)
|
||||
op(0xd5, "set ", "2", IHL, L)
|
||||
op(0xd6, "set ", "2", IHL)
|
||||
op(0xd7, "set ", "2", IHL, A)
|
||||
op(0xd8, "set ", "3", IHL, B)
|
||||
op(0xd9, "set ", "3", IHL, C)
|
||||
op(0xda, "set ", "3", IHL, D)
|
||||
op(0xdb, "set ", "3", IHL, E)
|
||||
op(0xdc, "set ", "3", IHL, H)
|
||||
op(0xdd, "set ", "3", IHL, L)
|
||||
op(0xde, "set ", "3", IHL)
|
||||
op(0xdf, "set ", "3", IHL, A)
|
||||
op(0xe0, "set ", "4", IHL, B)
|
||||
op(0xe1, "set ", "4", IHL, C)
|
||||
op(0xe2, "set ", "4", IHL, D)
|
||||
op(0xe3, "set ", "4", IHL, E)
|
||||
op(0xe4, "set ", "4", IHL, H)
|
||||
op(0xe5, "set ", "4", IHL, L)
|
||||
op(0xe6, "set ", "4", IHL)
|
||||
op(0xe7, "set ", "4", IHL, A)
|
||||
op(0xe8, "set ", "5", IHL, B)
|
||||
op(0xe9, "set ", "5", IHL, C)
|
||||
op(0xea, "set ", "5", IHL, D)
|
||||
op(0xeb, "set ", "5", IHL, E)
|
||||
op(0xec, "set ", "5", IHL, H)
|
||||
op(0xed, "set ", "5", IHL, L)
|
||||
op(0xee, "set ", "5", IHL)
|
||||
op(0xef, "set ", "5", IHL, A)
|
||||
op(0xf0, "set ", "6", IHL, B)
|
||||
op(0xf1, "set ", "6", IHL, C)
|
||||
op(0xf2, "set ", "6", IHL, D)
|
||||
op(0xf3, "set ", "6", IHL, E)
|
||||
op(0xf4, "set ", "6", IHL, H)
|
||||
op(0xf5, "set ", "6", IHL, L)
|
||||
op(0xf6, "set ", "6", IHL)
|
||||
op(0xf7, "set ", "6", IHL, A)
|
||||
op(0xf8, "set ", "7", IHL, B)
|
||||
op(0xf9, "set ", "7", IHL, C)
|
||||
op(0xfa, "set ", "7", IHL, D)
|
||||
op(0xfb, "set ", "7", IHL, E)
|
||||
op(0xfc, "set ", "7", IHL, H)
|
||||
op(0xfd, "set ", "7", IHL, L)
|
||||
op(0xfe, "set ", "7", IHL)
|
||||
op(0xff, "set ", "7", IHL, A)
|
||||
}
|
||||
|
||||
return {"???"};
|
||||
unreachable;
|
||||
}
|
||||
|
||||
auto Z80::disassembleED(uint16 pc, uint8 prefix, uint8 code) -> string {
|
||||
|
|
|
|||
|
|
@ -567,6 +567,246 @@ auto Z80::instructionCBd(uint16 addr, uint8 code) -> void {
|
|||
op(0x0d, RRC_irr_r, addr, L)
|
||||
op(0x0e, RRC_irr_r, addr, _)
|
||||
op(0x0f, RRC_irr_r, addr, A)
|
||||
op(0x10, RL_irr_r, addr, B)
|
||||
op(0x11, RL_irr_r, addr, C)
|
||||
op(0x12, RL_irr_r, addr, D)
|
||||
op(0x13, RL_irr_r, addr, E)
|
||||
op(0x14, RL_irr_r, addr, H)
|
||||
op(0x15, RL_irr_r, addr, L)
|
||||
op(0x16, RL_irr_r, addr, _)
|
||||
op(0x17, RL_irr_r, addr, A)
|
||||
op(0x18, RR_irr_r, addr, B)
|
||||
op(0x19, RR_irr_r, addr, C)
|
||||
op(0x1a, RR_irr_r, addr, D)
|
||||
op(0x1b, RR_irr_r, addr, E)
|
||||
op(0x1c, RR_irr_r, addr, H)
|
||||
op(0x1d, RR_irr_r, addr, L)
|
||||
op(0x1e, RR_irr_r, addr, _)
|
||||
op(0x1f, RR_irr_r, addr, A)
|
||||
op(0x20, SLA_irr_r, addr, B)
|
||||
op(0x21, SLA_irr_r, addr, C)
|
||||
op(0x22, SLA_irr_r, addr, D)
|
||||
op(0x23, SLA_irr_r, addr, E)
|
||||
op(0x24, SLA_irr_r, addr, H)
|
||||
op(0x25, SLA_irr_r, addr, L)
|
||||
op(0x26, SLA_irr_r, addr, _)
|
||||
op(0x27, SLA_irr_r, addr, A)
|
||||
op(0x28, SRA_irr_r, addr, B)
|
||||
op(0x29, SRA_irr_r, addr, C)
|
||||
op(0x2a, SRA_irr_r, addr, D)
|
||||
op(0x2b, SRA_irr_r, addr, E)
|
||||
op(0x2c, SRA_irr_r, addr, H)
|
||||
op(0x2d, SRA_irr_r, addr, L)
|
||||
op(0x2e, SRA_irr_r, addr, _)
|
||||
op(0x2f, SRA_irr_r, addr, A)
|
||||
op(0x30, SLL_irr_r, addr, B)
|
||||
op(0x31, SLL_irr_r, addr, C)
|
||||
op(0x32, SLL_irr_r, addr, D)
|
||||
op(0x33, SLL_irr_r, addr, E)
|
||||
op(0x34, SLL_irr_r, addr, H)
|
||||
op(0x35, SLL_irr_r, addr, L)
|
||||
op(0x36, SLL_irr_r, addr, _)
|
||||
op(0x37, SLL_irr_r, addr, A)
|
||||
op(0x38, SRL_irr_r, addr, B)
|
||||
op(0x39, SRL_irr_r, addr, C)
|
||||
op(0x3a, SRL_irr_r, addr, D)
|
||||
op(0x3b, SRL_irr_r, addr, E)
|
||||
op(0x3c, SRL_irr_r, addr, H)
|
||||
op(0x3d, SRL_irr_r, addr, L)
|
||||
op(0x3e, SRL_irr_r, addr, _)
|
||||
op(0x3f, SRL_irr_r, addr, A)
|
||||
op(0x40, BIT_o_irr_r, 0, addr, B)
|
||||
op(0x41, BIT_o_irr_r, 0, addr, C)
|
||||
op(0x42, BIT_o_irr_r, 0, addr, D)
|
||||
op(0x43, BIT_o_irr_r, 0, addr, E)
|
||||
op(0x44, BIT_o_irr_r, 0, addr, H)
|
||||
op(0x45, BIT_o_irr_r, 0, addr, L)
|
||||
op(0x46, BIT_o_irr_r, 0, addr, _)
|
||||
op(0x47, BIT_o_irr_r, 0, addr, A)
|
||||
op(0x48, BIT_o_irr_r, 1, addr, B)
|
||||
op(0x49, BIT_o_irr_r, 1, addr, C)
|
||||
op(0x4a, BIT_o_irr_r, 1, addr, D)
|
||||
op(0x4b, BIT_o_irr_r, 1, addr, E)
|
||||
op(0x4c, BIT_o_irr_r, 1, addr, H)
|
||||
op(0x4d, BIT_o_irr_r, 1, addr, L)
|
||||
op(0x4e, BIT_o_irr_r, 1, addr, _)
|
||||
op(0x4f, BIT_o_irr_r, 1, addr, A)
|
||||
op(0x50, BIT_o_irr_r, 2, addr, B)
|
||||
op(0x51, BIT_o_irr_r, 2, addr, C)
|
||||
op(0x52, BIT_o_irr_r, 2, addr, D)
|
||||
op(0x53, BIT_o_irr_r, 2, addr, E)
|
||||
op(0x54, BIT_o_irr_r, 2, addr, H)
|
||||
op(0x55, BIT_o_irr_r, 2, addr, L)
|
||||
op(0x56, BIT_o_irr_r, 2, addr, _)
|
||||
op(0x57, BIT_o_irr_r, 2, addr, A)
|
||||
op(0x58, BIT_o_irr_r, 3, addr, B)
|
||||
op(0x59, BIT_o_irr_r, 3, addr, C)
|
||||
op(0x5a, BIT_o_irr_r, 3, addr, D)
|
||||
op(0x5b, BIT_o_irr_r, 3, addr, E)
|
||||
op(0x5c, BIT_o_irr_r, 3, addr, H)
|
||||
op(0x5d, BIT_o_irr_r, 3, addr, L)
|
||||
op(0x5e, BIT_o_irr_r, 3, addr, _)
|
||||
op(0x5f, BIT_o_irr_r, 3, addr, A)
|
||||
op(0x60, BIT_o_irr_r, 4, addr, B)
|
||||
op(0x61, BIT_o_irr_r, 4, addr, C)
|
||||
op(0x62, BIT_o_irr_r, 4, addr, D)
|
||||
op(0x63, BIT_o_irr_r, 4, addr, E)
|
||||
op(0x64, BIT_o_irr_r, 4, addr, H)
|
||||
op(0x65, BIT_o_irr_r, 4, addr, L)
|
||||
op(0x66, BIT_o_irr_r, 4, addr, _)
|
||||
op(0x67, BIT_o_irr_r, 4, addr, A)
|
||||
op(0x68, BIT_o_irr_r, 5, addr, B)
|
||||
op(0x69, BIT_o_irr_r, 5, addr, C)
|
||||
op(0x6a, BIT_o_irr_r, 5, addr, D)
|
||||
op(0x6b, BIT_o_irr_r, 5, addr, E)
|
||||
op(0x6c, BIT_o_irr_r, 5, addr, H)
|
||||
op(0x6d, BIT_o_irr_r, 5, addr, L)
|
||||
op(0x6e, BIT_o_irr_r, 5, addr, _)
|
||||
op(0x6f, BIT_o_irr_r, 5, addr, A)
|
||||
op(0x70, BIT_o_irr_r, 6, addr, B)
|
||||
op(0x71, BIT_o_irr_r, 6, addr, C)
|
||||
op(0x72, BIT_o_irr_r, 6, addr, D)
|
||||
op(0x73, BIT_o_irr_r, 6, addr, E)
|
||||
op(0x74, BIT_o_irr_r, 6, addr, H)
|
||||
op(0x75, BIT_o_irr_r, 6, addr, L)
|
||||
op(0x76, BIT_o_irr_r, 6, addr, _)
|
||||
op(0x77, BIT_o_irr_r, 6, addr, A)
|
||||
op(0x78, BIT_o_irr_r, 7, addr, B)
|
||||
op(0x79, BIT_o_irr_r, 7, addr, C)
|
||||
op(0x7a, BIT_o_irr_r, 7, addr, D)
|
||||
op(0x7b, BIT_o_irr_r, 7, addr, E)
|
||||
op(0x7c, BIT_o_irr_r, 7, addr, H)
|
||||
op(0x7d, BIT_o_irr_r, 7, addr, L)
|
||||
op(0x7e, BIT_o_irr_r, 7, addr, _)
|
||||
op(0x7f, BIT_o_irr_r, 7, addr, A)
|
||||
op(0x80, RES_o_irr_r, 0, addr, B)
|
||||
op(0x81, RES_o_irr_r, 0, addr, C)
|
||||
op(0x82, RES_o_irr_r, 0, addr, D)
|
||||
op(0x83, RES_o_irr_r, 0, addr, E)
|
||||
op(0x84, RES_o_irr_r, 0, addr, H)
|
||||
op(0x85, RES_o_irr_r, 0, addr, L)
|
||||
op(0x86, RES_o_irr_r, 0, addr, _)
|
||||
op(0x87, RES_o_irr_r, 0, addr, A)
|
||||
op(0x88, RES_o_irr_r, 1, addr, B)
|
||||
op(0x89, RES_o_irr_r, 1, addr, C)
|
||||
op(0x8a, RES_o_irr_r, 1, addr, D)
|
||||
op(0x8b, RES_o_irr_r, 1, addr, E)
|
||||
op(0x8c, RES_o_irr_r, 1, addr, H)
|
||||
op(0x8d, RES_o_irr_r, 1, addr, L)
|
||||
op(0x8e, RES_o_irr_r, 1, addr, _)
|
||||
op(0x8f, RES_o_irr_r, 1, addr, A)
|
||||
op(0x90, RES_o_irr_r, 2, addr, B)
|
||||
op(0x91, RES_o_irr_r, 2, addr, C)
|
||||
op(0x92, RES_o_irr_r, 2, addr, D)
|
||||
op(0x93, RES_o_irr_r, 2, addr, E)
|
||||
op(0x94, RES_o_irr_r, 2, addr, H)
|
||||
op(0x95, RES_o_irr_r, 2, addr, L)
|
||||
op(0x96, RES_o_irr_r, 2, addr, _)
|
||||
op(0x97, RES_o_irr_r, 2, addr, A)
|
||||
op(0x98, RES_o_irr_r, 3, addr, B)
|
||||
op(0x99, RES_o_irr_r, 3, addr, C)
|
||||
op(0x9a, RES_o_irr_r, 3, addr, D)
|
||||
op(0x9b, RES_o_irr_r, 3, addr, E)
|
||||
op(0x9c, RES_o_irr_r, 3, addr, H)
|
||||
op(0x9d, RES_o_irr_r, 3, addr, L)
|
||||
op(0x9e, RES_o_irr_r, 3, addr, _)
|
||||
op(0x9f, RES_o_irr_r, 3, addr, A)
|
||||
op(0xa0, RES_o_irr_r, 4, addr, B)
|
||||
op(0xa1, RES_o_irr_r, 4, addr, C)
|
||||
op(0xa2, RES_o_irr_r, 4, addr, D)
|
||||
op(0xa3, RES_o_irr_r, 4, addr, E)
|
||||
op(0xa4, RES_o_irr_r, 4, addr, H)
|
||||
op(0xa5, RES_o_irr_r, 4, addr, L)
|
||||
op(0xa6, RES_o_irr_r, 4, addr, _)
|
||||
op(0xa7, RES_o_irr_r, 4, addr, A)
|
||||
op(0xa8, RES_o_irr_r, 5, addr, B)
|
||||
op(0xa9, RES_o_irr_r, 5, addr, C)
|
||||
op(0xaa, RES_o_irr_r, 5, addr, D)
|
||||
op(0xab, RES_o_irr_r, 5, addr, E)
|
||||
op(0xac, RES_o_irr_r, 5, addr, H)
|
||||
op(0xad, RES_o_irr_r, 5, addr, L)
|
||||
op(0xae, RES_o_irr_r, 5, addr, _)
|
||||
op(0xaf, RES_o_irr_r, 5, addr, A)
|
||||
op(0xb0, RES_o_irr_r, 6, addr, B)
|
||||
op(0xb1, RES_o_irr_r, 6, addr, C)
|
||||
op(0xb2, RES_o_irr_r, 6, addr, D)
|
||||
op(0xb3, RES_o_irr_r, 6, addr, E)
|
||||
op(0xb4, RES_o_irr_r, 6, addr, H)
|
||||
op(0xb5, RES_o_irr_r, 6, addr, L)
|
||||
op(0xb6, RES_o_irr_r, 6, addr, _)
|
||||
op(0xb7, RES_o_irr_r, 6, addr, A)
|
||||
op(0xb8, RES_o_irr_r, 7, addr, B)
|
||||
op(0xb9, RES_o_irr_r, 7, addr, C)
|
||||
op(0xba, RES_o_irr_r, 7, addr, D)
|
||||
op(0xbb, RES_o_irr_r, 7, addr, E)
|
||||
op(0xbc, RES_o_irr_r, 7, addr, H)
|
||||
op(0xbd, RES_o_irr_r, 7, addr, L)
|
||||
op(0xbe, RES_o_irr_r, 7, addr, _)
|
||||
op(0xbf, RES_o_irr_r, 7, addr, A)
|
||||
op(0xc0, SET_o_irr_r, 0, addr, B)
|
||||
op(0xc1, SET_o_irr_r, 0, addr, C)
|
||||
op(0xc2, SET_o_irr_r, 0, addr, D)
|
||||
op(0xc3, SET_o_irr_r, 0, addr, E)
|
||||
op(0xc4, SET_o_irr_r, 0, addr, H)
|
||||
op(0xc5, SET_o_irr_r, 0, addr, L)
|
||||
op(0xc6, SET_o_irr_r, 0, addr, _)
|
||||
op(0xc7, SET_o_irr_r, 0, addr, A)
|
||||
op(0xc8, SET_o_irr_r, 1, addr, B)
|
||||
op(0xc9, SET_o_irr_r, 1, addr, C)
|
||||
op(0xca, SET_o_irr_r, 1, addr, D)
|
||||
op(0xcb, SET_o_irr_r, 1, addr, E)
|
||||
op(0xcc, SET_o_irr_r, 1, addr, H)
|
||||
op(0xcd, SET_o_irr_r, 1, addr, L)
|
||||
op(0xce, SET_o_irr_r, 1, addr, _)
|
||||
op(0xcf, SET_o_irr_r, 1, addr, A)
|
||||
op(0xd0, SET_o_irr_r, 2, addr, B)
|
||||
op(0xd1, SET_o_irr_r, 2, addr, C)
|
||||
op(0xd2, SET_o_irr_r, 2, addr, D)
|
||||
op(0xd3, SET_o_irr_r, 2, addr, E)
|
||||
op(0xd4, SET_o_irr_r, 2, addr, H)
|
||||
op(0xd5, SET_o_irr_r, 2, addr, L)
|
||||
op(0xd6, SET_o_irr_r, 2, addr, _)
|
||||
op(0xd7, SET_o_irr_r, 2, addr, A)
|
||||
op(0xd8, SET_o_irr_r, 3, addr, B)
|
||||
op(0xd9, SET_o_irr_r, 3, addr, C)
|
||||
op(0xda, SET_o_irr_r, 3, addr, D)
|
||||
op(0xdb, SET_o_irr_r, 3, addr, E)
|
||||
op(0xdc, SET_o_irr_r, 3, addr, H)
|
||||
op(0xdd, SET_o_irr_r, 3, addr, L)
|
||||
op(0xde, SET_o_irr_r, 3, addr, _)
|
||||
op(0xdf, SET_o_irr_r, 3, addr, A)
|
||||
op(0xe0, SET_o_irr_r, 4, addr, B)
|
||||
op(0xe1, SET_o_irr_r, 4, addr, C)
|
||||
op(0xe2, SET_o_irr_r, 4, addr, D)
|
||||
op(0xe3, SET_o_irr_r, 4, addr, E)
|
||||
op(0xe4, SET_o_irr_r, 4, addr, H)
|
||||
op(0xe5, SET_o_irr_r, 4, addr, L)
|
||||
op(0xe6, SET_o_irr_r, 4, addr, _)
|
||||
op(0xe7, SET_o_irr_r, 4, addr, A)
|
||||
op(0xe8, SET_o_irr_r, 5, addr, B)
|
||||
op(0xe9, SET_o_irr_r, 5, addr, C)
|
||||
op(0xea, SET_o_irr_r, 5, addr, D)
|
||||
op(0xeb, SET_o_irr_r, 5, addr, E)
|
||||
op(0xec, SET_o_irr_r, 5, addr, H)
|
||||
op(0xed, SET_o_irr_r, 5, addr, L)
|
||||
op(0xee, SET_o_irr_r, 5, addr, _)
|
||||
op(0xef, SET_o_irr_r, 5, addr, A)
|
||||
op(0xf0, SET_o_irr_r, 6, addr, B)
|
||||
op(0xf1, SET_o_irr_r, 6, addr, C)
|
||||
op(0xf2, SET_o_irr_r, 6, addr, D)
|
||||
op(0xf3, SET_o_irr_r, 6, addr, E)
|
||||
op(0xf4, SET_o_irr_r, 6, addr, H)
|
||||
op(0xf5, SET_o_irr_r, 6, addr, L)
|
||||
op(0xf6, SET_o_irr_r, 6, addr, _)
|
||||
op(0xf7, SET_o_irr_r, 6, addr, A)
|
||||
op(0xf8, SET_o_irr_r, 7, addr, B)
|
||||
op(0xf9, SET_o_irr_r, 7, addr, C)
|
||||
op(0xfa, SET_o_irr_r, 7, addr, D)
|
||||
op(0xfb, SET_o_irr_r, 7, addr, E)
|
||||
op(0xfc, SET_o_irr_r, 7, addr, H)
|
||||
op(0xfd, SET_o_irr_r, 7, addr, L)
|
||||
op(0xfe, SET_o_irr_r, 7, addr, _)
|
||||
op(0xff, SET_o_irr_r, 7, addr, A)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -40,10 +40,12 @@ auto Z80::AND(uint8 x, uint8 y) -> uint8 {
|
|||
return z;
|
||||
}
|
||||
|
||||
auto Z80::BIT(uint3 bit, uint8 x) -> void {
|
||||
auto Z80::BIT(uint3 bit, uint8 x) -> uint8 {
|
||||
NF = 0;
|
||||
HF = 1;
|
||||
ZF = (x & 1 << bit) == 0;
|
||||
|
||||
return x;
|
||||
}
|
||||
|
||||
auto Z80::DEC(uint8 x) -> uint8 {
|
||||
|
|
@ -312,8 +314,12 @@ auto Z80::instructionAND_a_r(uint8& x) -> void {
|
|||
A = AND(A, x);
|
||||
}
|
||||
|
||||
auto Z80::instructionBIT_o_irr(uint3 bit, uint16& x) -> void {
|
||||
BIT(bit, read(displace(x)));
|
||||
auto Z80::instructionBIT_o_irr(uint3 bit, uint16& addr) -> void {
|
||||
BIT(bit, read(addr));
|
||||
}
|
||||
|
||||
auto Z80::instructionBIT_o_irr_r(uint3 bit, uint16& addr, uint8& x) -> void {
|
||||
x = BIT(bit, read(addr));
|
||||
}
|
||||
|
||||
auto Z80::instructionBIT_o_r(uint3 bit, uint8& x) -> void {
|
||||
|
|
@ -688,11 +694,14 @@ auto Z80::instructionPUSH_rr(uint16& x) -> void {
|
|||
push(x);
|
||||
}
|
||||
|
||||
auto Z80::instructionRES_o_irr(uint3 bit, uint16& x) -> void {
|
||||
auto addr = displace(x);
|
||||
auto Z80::instructionRES_o_irr(uint3 bit, uint16& addr) -> void {
|
||||
write(addr, RES(bit, read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionRES_o_irr_r(uint3 bit, uint16& addr, uint8& x) -> void {
|
||||
write(addr, x = RES(bit, read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionRES_o_r(uint3 bit, uint8& x) -> void {
|
||||
x = RES(bit, x);
|
||||
}
|
||||
|
|
@ -718,11 +727,14 @@ auto Z80::instructionRETN() -> void {
|
|||
r.iff1 = r.iff2;
|
||||
}
|
||||
|
||||
auto Z80::instructionRL_irr(uint16& x) -> void {
|
||||
auto addr = displace(x);
|
||||
auto Z80::instructionRL_irr(uint16& addr) -> void {
|
||||
write(addr, RL(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionRL_irr_r(uint16& addr, uint8& x) -> void {
|
||||
write(addr, x = RL(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionRL_r(uint8& x) -> void {
|
||||
x = RL(x);
|
||||
}
|
||||
|
|
@ -777,11 +789,14 @@ auto Z80::instructionRLD() -> void {
|
|||
SF = A.bit(7);
|
||||
}
|
||||
|
||||
auto Z80::instructionRR_irr(uint16& x) -> void {
|
||||
auto addr = displace(x);
|
||||
auto Z80::instructionRR_irr(uint16& addr) -> void {
|
||||
write(addr, RR(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionRR_irr_r(uint16& addr, uint8& x) -> void {
|
||||
write(addr, x = RR(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionRR_r(uint8& x) -> void {
|
||||
x = RR(x);
|
||||
}
|
||||
|
|
@ -869,47 +884,62 @@ auto Z80::instructionSCF() -> void {
|
|||
HF = 0;
|
||||
}
|
||||
|
||||
auto Z80::instructionSET_o_irr(uint3 bit, uint16& x) -> void {
|
||||
auto addr = displace(x);
|
||||
auto Z80::instructionSET_o_irr(uint3 bit, uint16& addr) -> void {
|
||||
write(addr, SET(bit, read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionSET_o_irr_r(uint3 bit, uint16& addr, uint8& x) -> void {
|
||||
write(addr, x = SET(bit, read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionSET_o_r(uint3 bit, uint8& x) -> void {
|
||||
x = SET(bit, x);
|
||||
}
|
||||
|
||||
auto Z80::instructionSLA_irr(uint16& x) -> void {
|
||||
auto addr = displace(x);
|
||||
auto Z80::instructionSLA_irr(uint16& addr) -> void {
|
||||
write(addr, SLA(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionSLA_irr_r(uint16& addr, uint8& x) -> void {
|
||||
write(addr, x = SLA(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionSLA_r(uint8& x) -> void {
|
||||
x = SLA(x);
|
||||
}
|
||||
|
||||
auto Z80::instructionSLL_irr(uint16& x) -> void {
|
||||
auto addr = displace(x);
|
||||
auto Z80::instructionSLL_irr(uint16& addr) -> void {
|
||||
write(addr, SLL(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionSLL_irr_r(uint16& addr, uint8& x) -> void {
|
||||
write(addr, x = SLL(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionSLL_r(uint8& x) -> void {
|
||||
x = SLL(x);
|
||||
}
|
||||
|
||||
auto Z80::instructionSRA_irr(uint16& x) -> void {
|
||||
auto addr = displace(x);
|
||||
auto Z80::instructionSRA_irr(uint16& addr) -> void {
|
||||
write(addr, SRA(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionSRA_irr_r(uint16& addr, uint8& x) -> void {
|
||||
write(addr, x = SRA(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionSRA_r(uint8& x) -> void {
|
||||
x = SRA(x);
|
||||
}
|
||||
|
||||
auto Z80::instructionSRL_irr(uint16& x) -> void {
|
||||
auto addr = displace(x);
|
||||
auto Z80::instructionSRL_irr(uint16& addr) -> void {
|
||||
write(addr, SRL(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionSRL_irr_r(uint16& addr, uint8& x) -> void {
|
||||
write(addr, x = SRL(read(addr)));
|
||||
}
|
||||
|
||||
auto Z80::instructionSRL_r(uint8& x) -> void {
|
||||
x = SRL(x);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ struct Z80 {
|
|||
//instructions.cpp
|
||||
auto ADD(uint8, uint8, bool = false) -> uint8;
|
||||
auto AND(uint8, uint8) -> uint8;
|
||||
auto BIT(uint3, uint8) -> void;
|
||||
auto BIT(uint3, uint8) -> uint8;
|
||||
auto DEC(uint8) -> uint8;
|
||||
auto INC(uint8) -> uint8;
|
||||
auto OR (uint8, uint8) -> uint8;
|
||||
|
|
@ -73,6 +73,7 @@ struct Z80 {
|
|||
auto instructionAND_a_n() -> void;
|
||||
auto instructionAND_a_r(uint8&) -> void;
|
||||
auto instructionBIT_o_irr(uint3, uint16&) -> void;
|
||||
auto instructionBIT_o_irr_r(uint3, uint16&, uint8&) -> void;
|
||||
auto instructionBIT_o_r(uint3, uint8&) -> void;
|
||||
auto instructionCALL_c_nn(bool c) -> void;
|
||||
auto instructionCALL_nn() -> void;
|
||||
|
|
@ -140,12 +141,14 @@ struct Z80 {
|
|||
auto instructionPOP_rr(uint16&) -> void;
|
||||
auto instructionPUSH_rr(uint16&) -> void;
|
||||
auto instructionRES_o_irr(uint3, uint16&) -> void;
|
||||
auto instructionRES_o_irr_r(uint3, uint16&, uint8&) -> void;
|
||||
auto instructionRES_o_r(uint3, uint8&) -> void;
|
||||
auto instructionRET() -> void;
|
||||
auto instructionRET_c(bool c) -> void;
|
||||
auto instructionRETI() -> void;
|
||||
auto instructionRETN() -> void;
|
||||
auto instructionRL_irr(uint16&) -> void;
|
||||
auto instructionRL_irr_r(uint16&, uint8&) -> void;
|
||||
auto instructionRL_r(uint8&) -> void;
|
||||
auto instructionRLA() -> void;
|
||||
auto instructionRLC_irr(uint16&) -> void;
|
||||
|
|
@ -154,6 +157,7 @@ struct Z80 {
|
|||
auto instructionRLCA() -> void;
|
||||
auto instructionRLD() -> void;
|
||||
auto instructionRR_irr(uint16&) -> void;
|
||||
auto instructionRR_irr_r(uint16&, uint8&) -> void;
|
||||
auto instructionRR_r(uint8&) -> void;
|
||||
auto instructionRRA() -> void;
|
||||
auto instructionRRC_irr(uint16&) -> void;
|
||||
|
|
@ -168,14 +172,19 @@ struct Z80 {
|
|||
auto instructionSBC_hl_rr(uint16&) -> void;
|
||||
auto instructionSCF() -> void;
|
||||
auto instructionSET_o_irr(uint3, uint16&) -> void;
|
||||
auto instructionSET_o_irr_r(uint3, uint16&, uint8&) -> void;
|
||||
auto instructionSET_o_r(uint3, uint8&) -> void;
|
||||
auto instructionSLA_irr(uint16&) -> void;
|
||||
auto instructionSLA_irr_r(uint16&, uint8&) -> void;
|
||||
auto instructionSLA_r(uint8&) -> void;
|
||||
auto instructionSLL_irr(uint16&) -> void;
|
||||
auto instructionSLL_irr_r(uint16&, uint8&) -> void;
|
||||
auto instructionSLL_r(uint8&) -> void;
|
||||
auto instructionSRA_irr(uint16&) -> void;
|
||||
auto instructionSRA_irr_r(uint16&, uint8&) -> void;
|
||||
auto instructionSRA_r(uint8&) -> void;
|
||||
auto instructionSRL_irr(uint16&) -> void;
|
||||
auto instructionSRL_irr_r(uint16&, uint8&) -> void;
|
||||
auto instructionSRL_r(uint8&) -> void;
|
||||
auto instructionSUB_a_irr(uint16&) -> void;
|
||||
auto instructionSUB_a_n() -> void;
|
||||
|
|
|
|||
Loading…
Reference in New Issue