mirror of https://github.com/bsnes-emu/bsnes.git
Update to v094r33 release.
byuu says:
Small WIP, just fixes the timings for GSU multiply.
However, the actual product may still be wrong when CLSR and MS0 are
both set. Since I wasn't 'corrupting' the value in said case before,
then this behavior can only be better than before.
Turned the (cache,memory)_access_timing into functions that compute the
values; and pulled "clockspeed" into GSU.
Also, I'm thinking it might be kind of pointless to have clockspeed at
all. Supposedly even the Mario Chip can run at 21.48MHz anyway.
Enforcing 10.74MHz mode seems kind of silly. If we change it to just be
a "default value for CLSR", then we can just inline the memory access
tests without the need for the access_timing functions (literally just
clsr?2:1 then)
Slight compilation bug: go to processor/gsu/registers.hpp:33 and add
reg16_t() = default;
I missed it due to a partial recompile. Too lazy to upload another WIP
just for that.
Probably not worth doing much SuperFX testing just yet, as it looks like
they're doing some other tests at the moment on NESdev.
This commit is contained in:
Tim Allen
parent
169e400437
commit
4c9266d18f
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@ -8,7 +8,7 @@ using namespace nall;
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namespace Emulator {
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static const string Name = "higan";
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static const string Version = "094.32";
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static const string Version = "094.33";
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static const string Author = "byuu";
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static const string License = "GPLv3";
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static const string Website = "http://byuu.org/";
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@ -7,26 +7,41 @@ namespace Processor {
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#include "table.cpp"
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#include "serialization.cpp"
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void GSU::power() {
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//note: multiplication results *may* sometimes be invalid when both CLSR and MS0 are set
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//the product of multiplication in this mode (21mhz + fast-multiply) has not been analyzed;
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//however, the timing of this mode has been confirmed to work as specified below
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auto GSU::cache_access_speed() -> unsigned {
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if(clockmode == 1) return 2;
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if(clockmode == 2) return 1;
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return regs.clsr ? 1 : 2;
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}
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void GSU::reset() {
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auto GSU::memory_access_speed() -> unsigned {
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if(clockmode == 1) return 6;
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if(clockmode == 2) return 5;
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return regs.clsr ? 5 : 6;
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}
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auto GSU::power() -> void {
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}
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auto GSU::reset() -> void {
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for(auto& r : regs.r) r = 0x0000;
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regs.sfr = 0x0000;
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regs.pbr = 0x00;
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regs.rombr = 0x00;
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regs.rambr = 0;
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regs.cbr = 0x0000;
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regs.scbr = 0x00;
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regs.scmr = 0x00;
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regs.colr = 0x00;
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regs.por = 0x00;
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regs.bramr = 0;
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regs.vcr = 0x04;
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regs.cfgr = 0x00;
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regs.clsr = 0;
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regs.sfr = 0x0000;
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regs.pbr = 0x00;
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regs.rombr = 0x00;
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regs.rambr = 0;
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regs.cbr = 0x0000;
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regs.scbr = 0x00;
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regs.scmr = 0x00;
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regs.colr = 0x00;
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regs.por = 0x00;
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regs.bramr = 0;
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regs.vcr = 0x04;
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regs.cfgr = 0x00;
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regs.clsr = 0;
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regs.pipeline = 0x01; //nop
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regs.ramaddr = 0x0000;
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regs.ramaddr = 0x0000;
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regs.reset();
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}
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@ -4,113 +4,120 @@
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namespace Processor {
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struct GSU {
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unsigned clockmode; //0 = selectable; 1 = force 10.74mhz; 2 = force 21.48mhz
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#include "registers.hpp"
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virtual void step(unsigned clocks) = 0;
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virtual auto step(unsigned clocks) -> void = 0;
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virtual void stop() = 0;
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virtual uint8 color(uint8 source) = 0;
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virtual void plot(uint8 x, uint8 y) = 0;
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virtual uint8 rpix(uint8 x, uint8 y) = 0;
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virtual auto stop() -> void = 0;
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virtual auto color(uint8 source) -> uint8 = 0;
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virtual auto plot(uint8 x, uint8 y) -> void = 0;
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virtual auto rpix(uint8 x, uint8 y) -> uint8 = 0;
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virtual uint8 pipe() = 0;
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virtual void rombuffer_sync() = 0;
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virtual uint8 rombuffer_read() = 0;
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virtual void rambuffer_sync() = 0;
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virtual uint8 rambuffer_read(uint16 addr) = 0;
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virtual void rambuffer_write(uint16 addr, uint8 data) = 0;
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virtual void cache_flush() = 0;
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virtual auto pipe() -> uint8 = 0;
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virtual auto rombuffer_sync() -> void = 0;
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virtual auto rombuffer_read() -> uint8 = 0;
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virtual auto rambuffer_sync() -> void = 0;
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virtual auto rambuffer_read(uint16 addr) -> uint8 = 0;
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virtual auto rambuffer_write(uint16 addr, uint8 data) -> void = 0;
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virtual auto cache_flush() -> void = 0;
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void power();
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void reset();
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void serialize(serializer&);
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//gsu.cpp
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auto cache_access_speed() -> unsigned;
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auto memory_access_speed() -> unsigned;
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//table.cpp
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void (GSU::*opcode_table[1024])();
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void initialize_opcode_table();
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auto power() -> void;
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auto reset() -> void;
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//instructions.cpp
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template<int> void op_adc_i();
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template<int> void op_adc_r();
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template<int> void op_add_i();
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template<int> void op_add_r();
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void op_alt1();
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void op_alt2();
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void op_alt3();
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template<int> void op_and_i();
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template<int> void op_and_r();
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void op_asr();
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void op_bge();
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void op_bcc();
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void op_bcs();
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void op_beq();
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template<int> void op_bic_i();
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template<int> void op_bic_r();
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void op_blt();
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void op_bmi();
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void op_bne();
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void op_bpl();
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void op_bra();
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void op_bvc();
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void op_bvs();
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void op_cache();
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void op_cmode();
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template<int> void op_cmp_r();
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void op_color();
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template<int> void op_dec_r();
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void op_div2();
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void op_fmult();
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template<int> void op_from_r();
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void op_getb();
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void op_getbl();
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void op_getbh();
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void op_getbs();
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void op_getc();
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void op_hib();
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template<int> void op_ibt_r();
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template<int> void op_inc_r();
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template<int> void op_iwt_r();
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template<int> void op_jmp_r();
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template<int> void op_ldb_ir();
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template<int> void op_ldw_ir();
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template<int> void op_link();
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template<int> void op_ljmp_r();
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template<int> void op_lm_r();
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template<int> void op_lms_r();
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void op_lmult();
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void op_lob();
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void op_loop();
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void op_lsr();
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void op_merge();
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template<int> void op_mult_i();
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template<int> void op_mult_r();
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void op_nop();
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void op_not();
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template<int> void op_or_i();
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template<int> void op_or_r();
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void op_plot();
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void op_ramb();
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void op_rol();
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void op_romb();
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void op_ror();
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void op_rpix();
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template<int> void op_sbc_r();
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void op_sbk();
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void op_sex();
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template<int> void op_sm_r();
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template<int> void op_sms_r();
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template<int> void op_stb_ir();
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void op_stop();
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template<int> void op_stw_ir();
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template<int> void op_sub_i();
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template<int> void op_sub_r();
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void op_swap();
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template<int> void op_to_r();
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template<int> void op_umult_i();
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template<int> void op_umult_r();
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template<int> void op_with_r();
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template<int> void op_xor_i();
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template<int> void op_xor_r();
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template<int> auto op_adc_i();
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template<int> auto op_adc_r();
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template<int> auto op_add_i();
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template<int> auto op_add_r();
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auto op_alt1();
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auto op_alt2();
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auto op_alt3();
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template<int> auto op_and_i();
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template<int> auto op_and_r();
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auto op_asr();
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auto op_bge();
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auto op_bcc();
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auto op_bcs();
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auto op_beq();
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template<int> auto op_bic_i();
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template<int> auto op_bic_r();
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auto op_blt();
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auto op_bmi();
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auto op_bne();
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auto op_bpl();
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auto op_bra();
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auto op_bvc();
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auto op_bvs();
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auto op_cache();
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auto op_cmode();
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template<int> auto op_cmp_r();
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auto op_color();
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template<int> auto op_dec_r();
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auto op_div2();
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auto op_fmult();
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template<int> auto op_from_r();
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auto op_getb();
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auto op_getbl();
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auto op_getbh();
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auto op_getbs();
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auto op_getc();
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auto op_hib();
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template<int> auto op_ibt_r();
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template<int> auto op_inc_r();
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template<int> auto op_iwt_r();
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template<int> auto op_jmp_r();
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template<int> auto op_ldb_ir();
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template<int> auto op_ldw_ir();
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template<int> auto op_link();
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template<int> auto op_ljmp_r();
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template<int> auto op_lm_r();
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template<int> auto op_lms_r();
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auto op_lmult();
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auto op_lob();
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auto op_loop();
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auto op_lsr();
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auto op_merge();
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template<int> auto op_mult_i();
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template<int> auto op_mult_r();
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auto op_nop();
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auto op_not();
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template<int> auto op_or_i();
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template<int> auto op_or_r();
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auto op_plot();
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auto op_ramb();
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auto op_rol();
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auto op_romb();
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auto op_ror();
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auto op_rpix();
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template<int> auto op_sbc_r();
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auto op_sbk();
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auto op_sex();
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template<int> auto op_sm_r();
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template<int> auto op_sms_r();
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template<int> auto op_stb_ir();
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auto op_stop();
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template<int> auto op_stw_ir();
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template<int> auto op_sub_i();
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template<int> auto op_sub_r();
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auto op_swap();
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template<int> auto op_to_r();
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template<int> auto op_umult_i();
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template<int> auto op_umult_r();
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template<int> auto op_with_r();
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template<int> auto op_xor_i();
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template<int> auto op_xor_r();
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//table.cpp
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auto (GSU::*opcode_table[1024])() -> void;
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auto initialize_opcode_table() -> void;
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//serialization.cpp
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auto serialize(serializer&) -> void;
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};
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}
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@ -1,5 +1,5 @@
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//$00 stop
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void GSU::op_stop() {
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auto GSU::op_stop() {
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if(regs.cfgr.irq == 0) {
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regs.sfr.irq = 1;
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stop();
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@ -11,12 +11,12 @@ void GSU::op_stop() {
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}
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//$01 nop
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void GSU::op_nop() {
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auto GSU::op_nop() {
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regs.reset();
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}
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//$02 cache
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void GSU::op_cache() {
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auto GSU::op_cache() {
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if(regs.cbr != (regs.r[15] & 0xfff0)) {
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regs.cbr = regs.r[15] & 0xfff0;
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cache_flush();
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@ -25,7 +25,7 @@ void GSU::op_cache() {
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}
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//$03 lsr
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void GSU::op_lsr() {
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auto GSU::op_lsr() {
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regs.sfr.cy = (regs.sr() & 1);
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regs.dr() = regs.sr() >> 1;
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regs.sfr.s = (regs.dr() & 0x8000);
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@ -34,7 +34,7 @@ void GSU::op_lsr() {
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}
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//$04 rol
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void GSU::op_rol() {
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auto GSU::op_rol() {
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bool carry = (regs.sr() & 0x8000);
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regs.dr() = (regs.sr() << 1) | regs.sfr.cy;
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regs.sfr.s = (regs.dr() & 0x8000);
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@ -44,73 +44,74 @@ void GSU::op_rol() {
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}
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//$05 bra e
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void GSU::op_bra() {
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auto GSU::op_bra() {
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regs.r[15] += (int8)pipe();
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}
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//$06 blt e
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void GSU::op_blt() {
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auto GSU::op_blt() {
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int e = (int8)pipe();
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if((regs.sfr.s ^ regs.sfr.ov) == 0) regs.r[15] += e;
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}
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//$07 bge e
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void GSU::op_bge() {
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auto GSU::op_bge() {
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int e = (int8)pipe();
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if((regs.sfr.s ^ regs.sfr.ov) == 1) regs.r[15] += e;
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}
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//$08 bne e
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void GSU::op_bne() {
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auto GSU::op_bne() {
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int e = (int8)pipe();
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if(regs.sfr.z == 0) regs.r[15] += e;
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}
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//$09 beq e
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void GSU::op_beq() {
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auto GSU::op_beq() {
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int e = (int8)pipe();
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if(regs.sfr.z == 1) regs.r[15] += e;
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}
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//$0a bpl e
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void GSU::op_bpl() {
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auto GSU::op_bpl() {
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int e = (int8)pipe();
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if(regs.sfr.s == 0) regs.r[15] += e;
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}
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//$0b bmi e
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void GSU::op_bmi() {
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auto GSU::op_bmi() {
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int e = (int8)pipe();
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if(regs.sfr.s == 1) regs.r[15] += e;
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}
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//$0c bcc e
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void GSU::op_bcc() {
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auto GSU::op_bcc() {
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int e = (int8)pipe();
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if(regs.sfr.cy == 0) regs.r[15] += e;
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}
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//$0d bcs e
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void GSU::op_bcs() {
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auto GSU::op_bcs() {
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int e = (int8)pipe();
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if(regs.sfr.cy == 1) regs.r[15] += e;
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}
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//$0e bvc e
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void GSU::op_bvc() {
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auto GSU::op_bvc() {
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int e = (int8)pipe();
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if(regs.sfr.ov == 0) regs.r[15] += e;
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}
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//$0f bvs e
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void GSU::op_bvs() {
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auto GSU::op_bvs() {
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int e = (int8)pipe();
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if(regs.sfr.ov == 1) regs.r[15] += e;
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}
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//$10-1f(b0): to rN
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//$10-1f(b1): move rN
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template<int n> void GSU::op_to_r() {
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template<int n>
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auto GSU::op_to_r() {
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if(regs.sfr.b == 0) {
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regs.dreg = n;
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} else {
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@ -120,14 +121,16 @@ template<int n> void GSU::op_to_r() {
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}
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//$20-2f: with rN
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template<int n> void GSU::op_with_r() {
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template<int n>
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auto GSU::op_with_r() {
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regs.sreg = n;
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regs.dreg = n;
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regs.sfr.b = 1;
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}
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//$30-3b(alt0): stw (rN)
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template<int n> void GSU::op_stw_ir() {
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template<int n>
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auto GSU::op_stw_ir() {
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regs.ramaddr = regs.r[n];
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rambuffer_write(regs.ramaddr ^ 0, regs.sr() >> 0);
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rambuffer_write(regs.ramaddr ^ 1, regs.sr() >> 8);
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@ -135,14 +138,15 @@ template<int n> void GSU::op_stw_ir() {
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}
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//$30-3b(alt1): stb (rN)
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template<int n> void GSU::op_stb_ir() {
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template<int n>
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auto GSU::op_stb_ir() {
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regs.ramaddr = regs.r[n];
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rambuffer_write(regs.ramaddr, regs.sr());
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regs.reset();
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||||
}
|
||||
|
||||
//$3c loop
|
||||
void GSU::op_loop() {
|
||||
auto GSU::op_loop() {
|
||||
regs.r[12]--;
|
||||
regs.sfr.s = (regs.r[12] & 0x8000);
|
||||
regs.sfr.z = (regs.r[12] == 0);
|
||||
|
|
@ -151,26 +155,27 @@ void GSU::op_loop() {
|
|||
}
|
||||
|
||||
//$3d alt1
|
||||
void GSU::op_alt1() {
|
||||
auto GSU::op_alt1() {
|
||||
regs.sfr.b = 0;
|
||||
regs.sfr.alt1 = 1;
|
||||
}
|
||||
|
||||
//$3e alt2
|
||||
void GSU::op_alt2() {
|
||||
auto GSU::op_alt2() {
|
||||
regs.sfr.b = 0;
|
||||
regs.sfr.alt2 = 1;
|
||||
}
|
||||
|
||||
//$3f alt3
|
||||
void GSU::op_alt3() {
|
||||
auto GSU::op_alt3() {
|
||||
regs.sfr.b = 0;
|
||||
regs.sfr.alt1 = 1;
|
||||
regs.sfr.alt2 = 1;
|
||||
}
|
||||
|
||||
//$40-4b(alt0): ldw (rN)
|
||||
template<int n> void GSU::op_ldw_ir() {
|
||||
template<int n>
|
||||
auto GSU::op_ldw_ir() {
|
||||
regs.ramaddr = regs.r[n];
|
||||
uint16_t data;
|
||||
data = rambuffer_read(regs.ramaddr ^ 0) << 0;
|
||||
|
|
@ -180,21 +185,22 @@ template<int n> void GSU::op_ldw_ir() {
|
|||
}
|
||||
|
||||
//$40-4b(alt1): ldb (rN)
|
||||
template<int n> void GSU::op_ldb_ir() {
|
||||
template<int n>
|
||||
auto GSU::op_ldb_ir() {
|
||||
regs.ramaddr = regs.r[n];
|
||||
regs.dr() = rambuffer_read(regs.ramaddr);
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$4c(alt0): plot
|
||||
void GSU::op_plot() {
|
||||
auto GSU::op_plot() {
|
||||
plot(regs.r[1], regs.r[2]);
|
||||
regs.r[1]++;
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$4c(alt1): rpix
|
||||
void GSU::op_rpix() {
|
||||
auto GSU::op_rpix() {
|
||||
regs.dr() = rpix(regs.r[1], regs.r[2]);
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -202,7 +208,7 @@ void GSU::op_rpix() {
|
|||
}
|
||||
|
||||
//$4d: swap
|
||||
void GSU::op_swap() {
|
||||
auto GSU::op_swap() {
|
||||
regs.dr() = (regs.sr() >> 8) | (regs.sr() << 8);
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -210,19 +216,19 @@ void GSU::op_swap() {
|
|||
}
|
||||
|
||||
//$4e(alt0): color
|
||||
void GSU::op_color() {
|
||||
auto GSU::op_color() {
|
||||
regs.colr = color(regs.sr());
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$4e(alt1): cmode
|
||||
void GSU::op_cmode() {
|
||||
auto GSU::op_cmode() {
|
||||
regs.por = regs.sr();
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$4f: not
|
||||
void GSU::op_not() {
|
||||
auto GSU::op_not() {
|
||||
regs.dr() = ~regs.sr();
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -230,7 +236,8 @@ void GSU::op_not() {
|
|||
}
|
||||
|
||||
//$50-5f(alt0): add rN
|
||||
template<int n> void GSU::op_add_r() {
|
||||
template<int n>
|
||||
auto GSU::op_add_r() {
|
||||
int r = regs.sr() + regs.r[n];
|
||||
regs.sfr.ov = ~(regs.sr() ^ regs.r[n]) & (regs.r[n] ^ r) & 0x8000;
|
||||
regs.sfr.s = (r & 0x8000);
|
||||
|
|
@ -241,7 +248,8 @@ template<int n> void GSU::op_add_r() {
|
|||
}
|
||||
|
||||
//$50-5f(alt1): adc rN
|
||||
template<int n> void GSU::op_adc_r() {
|
||||
template<int n>
|
||||
auto GSU::op_adc_r() {
|
||||
int r = regs.sr() + regs.r[n] + regs.sfr.cy;
|
||||
regs.sfr.ov = ~(regs.sr() ^ regs.r[n]) & (regs.r[n] ^ r) & 0x8000;
|
||||
regs.sfr.s = (r & 0x8000);
|
||||
|
|
@ -252,7 +260,8 @@ template<int n> void GSU::op_adc_r() {
|
|||
}
|
||||
|
||||
//$50-5f(alt2): add #N
|
||||
template<int n> void GSU::op_add_i() {
|
||||
template<int n>
|
||||
auto GSU::op_add_i() {
|
||||
int r = regs.sr() + n;
|
||||
regs.sfr.ov = ~(regs.sr() ^ n) & (n ^ r) & 0x8000;
|
||||
regs.sfr.s = (r & 0x8000);
|
||||
|
|
@ -263,7 +272,8 @@ template<int n> void GSU::op_add_i() {
|
|||
}
|
||||
|
||||
//$50-5f(alt3): adc #N
|
||||
template<int n> void GSU::op_adc_i() {
|
||||
template<int n>
|
||||
auto GSU::op_adc_i() {
|
||||
int r = regs.sr() + n + regs.sfr.cy;
|
||||
regs.sfr.ov = ~(regs.sr() ^ n) & (n ^ r) & 0x8000;
|
||||
regs.sfr.s = (r & 0x8000);
|
||||
|
|
@ -274,7 +284,8 @@ template<int n> void GSU::op_adc_i() {
|
|||
}
|
||||
|
||||
//$60-6f(alt0): sub rN
|
||||
template<int n> void GSU::op_sub_r() {
|
||||
template<int n>
|
||||
auto GSU::op_sub_r() {
|
||||
int r = regs.sr() - regs.r[n];
|
||||
regs.sfr.ov = (regs.sr() ^ regs.r[n]) & (regs.sr() ^ r) & 0x8000;
|
||||
regs.sfr.s = (r & 0x8000);
|
||||
|
|
@ -285,7 +296,8 @@ template<int n> void GSU::op_sub_r() {
|
|||
}
|
||||
|
||||
//$60-6f(alt1): sbc rN
|
||||
template<int n> void GSU::op_sbc_r() {
|
||||
template<int n>
|
||||
auto GSU::op_sbc_r() {
|
||||
int r = regs.sr() - regs.r[n] - !regs.sfr.cy;
|
||||
regs.sfr.ov = (regs.sr() ^ regs.r[n]) & (regs.sr() ^ r) & 0x8000;
|
||||
regs.sfr.s = (r & 0x8000);
|
||||
|
|
@ -296,7 +308,8 @@ template<int n> void GSU::op_sbc_r() {
|
|||
}
|
||||
|
||||
//$60-6f(alt2): sub #N
|
||||
template<int n> void GSU::op_sub_i() {
|
||||
template<int n>
|
||||
auto GSU::op_sub_i() {
|
||||
int r = regs.sr() - n;
|
||||
regs.sfr.ov = (regs.sr() ^ n) & (regs.sr() ^ r) & 0x8000;
|
||||
regs.sfr.s = (r & 0x8000);
|
||||
|
|
@ -307,7 +320,8 @@ template<int n> void GSU::op_sub_i() {
|
|||
}
|
||||
|
||||
//$60-6f(alt3): cmp rN
|
||||
template<int n> void GSU::op_cmp_r() {
|
||||
template<int n>
|
||||
auto GSU::op_cmp_r() {
|
||||
int r = regs.sr() - regs.r[n];
|
||||
regs.sfr.ov = (regs.sr() ^ regs.r[n]) & (regs.sr() ^ r) & 0x8000;
|
||||
regs.sfr.s = (r & 0x8000);
|
||||
|
|
@ -317,7 +331,7 @@ template<int n> void GSU::op_cmp_r() {
|
|||
}
|
||||
|
||||
//$70: merge
|
||||
void GSU::op_merge() {
|
||||
auto GSU::op_merge() {
|
||||
regs.dr() = (regs.r[7] & 0xff00) | (regs.r[8] >> 8);
|
||||
regs.sfr.ov = (regs.dr() & 0xc0c0);
|
||||
regs.sfr.s = (regs.dr() & 0x8080);
|
||||
|
|
@ -327,7 +341,8 @@ void GSU::op_merge() {
|
|||
}
|
||||
|
||||
//$71-7f(alt0): and rN
|
||||
template<int n> void GSU::op_and_r() {
|
||||
template<int n>
|
||||
auto GSU::op_and_r() {
|
||||
regs.dr() = regs.sr() & regs.r[n];
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -335,7 +350,8 @@ template<int n> void GSU::op_and_r() {
|
|||
}
|
||||
|
||||
//$71-7f(alt1): bic rN
|
||||
template<int n> void GSU::op_bic_r() {
|
||||
template<int n>
|
||||
auto GSU::op_bic_r() {
|
||||
regs.dr() = regs.sr() & ~regs.r[n];
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -343,7 +359,8 @@ template<int n> void GSU::op_bic_r() {
|
|||
}
|
||||
|
||||
//$71-7f(alt2): and #N
|
||||
template<int n> void GSU::op_and_i() {
|
||||
template<int n>
|
||||
auto GSU::op_and_i() {
|
||||
regs.dr() = regs.sr() & n;
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -351,7 +368,8 @@ template<int n> void GSU::op_and_i() {
|
|||
}
|
||||
|
||||
//$71-7f(alt3): bic #N
|
||||
template<int n> void GSU::op_bic_i() {
|
||||
template<int n>
|
||||
auto GSU::op_bic_i() {
|
||||
regs.dr() = regs.sr() & ~n;
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -359,56 +377,61 @@ template<int n> void GSU::op_bic_i() {
|
|||
}
|
||||
|
||||
//$80-8f(alt0): mult rN
|
||||
template<int n> void GSU::op_mult_r() {
|
||||
template<int n>
|
||||
auto GSU::op_mult_r() {
|
||||
regs.dr() = (int8)regs.sr() * (int8)regs.r[n];
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
regs.reset();
|
||||
if(!regs.cfgr.ms0) step(2);
|
||||
if(!regs.cfgr.ms0) step(cache_access_speed());
|
||||
}
|
||||
|
||||
//$80-8f(alt1): umult rN
|
||||
template<int n> void GSU::op_umult_r() {
|
||||
template<int n>
|
||||
auto GSU::op_umult_r() {
|
||||
regs.dr() = (uint8)regs.sr() * (uint8)regs.r[n];
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
regs.reset();
|
||||
if(!regs.cfgr.ms0) step(2);
|
||||
if(!regs.cfgr.ms0) step(cache_access_speed());
|
||||
}
|
||||
|
||||
//$80-8f(alt2): mult #N
|
||||
template<int n> void GSU::op_mult_i() {
|
||||
template<int n>
|
||||
auto GSU::op_mult_i() {
|
||||
regs.dr() = (int8)regs.sr() * (int8)n;
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
regs.reset();
|
||||
if(!regs.cfgr.ms0) step(2);
|
||||
if(!regs.cfgr.ms0) step(cache_access_speed());
|
||||
}
|
||||
|
||||
//$80-8f(alt3): umult #N
|
||||
template<int n> void GSU::op_umult_i() {
|
||||
template<int n>
|
||||
auto GSU::op_umult_i() {
|
||||
regs.dr() = (uint8)regs.sr() * (uint8)n;
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
regs.reset();
|
||||
if(!regs.cfgr.ms0) step(2);
|
||||
if(!regs.cfgr.ms0) step(cache_access_speed());
|
||||
}
|
||||
|
||||
//$90: sbk
|
||||
void GSU::op_sbk() {
|
||||
auto GSU::op_sbk() {
|
||||
rambuffer_write(regs.ramaddr ^ 0, regs.sr() >> 0);
|
||||
rambuffer_write(regs.ramaddr ^ 1, regs.sr() >> 8);
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$91-94: link #N
|
||||
template<int n> void GSU::op_link() {
|
||||
template<int n>
|
||||
auto GSU::op_link() {
|
||||
regs.r[11] = regs.r[15] + n;
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$95: sex
|
||||
void GSU::op_sex() {
|
||||
auto GSU::op_sex() {
|
||||
regs.dr() = (int8)regs.sr();
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -416,7 +439,7 @@ void GSU::op_sex() {
|
|||
}
|
||||
|
||||
//$96(alt0): asr
|
||||
void GSU::op_asr() {
|
||||
auto GSU::op_asr() {
|
||||
regs.sfr.cy = (regs.sr() & 1);
|
||||
regs.dr() = (int16_t)regs.sr() >> 1;
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
|
|
@ -425,7 +448,7 @@ void GSU::op_asr() {
|
|||
}
|
||||
|
||||
//$96(alt1): div2
|
||||
void GSU::op_div2() {
|
||||
auto GSU::op_div2() {
|
||||
regs.sfr.cy = (regs.sr() & 1);
|
||||
regs.dr() = ((int16_t)regs.sr() >> 1) + ((regs.sr() + 1) >> 16);
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
|
|
@ -434,7 +457,7 @@ void GSU::op_div2() {
|
|||
}
|
||||
|
||||
//$97: ror
|
||||
void GSU::op_ror() {
|
||||
auto GSU::op_ror() {
|
||||
bool carry = (regs.sr() & 1);
|
||||
regs.dr() = (regs.sfr.cy << 15) | (regs.sr() >> 1);
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
|
|
@ -444,13 +467,15 @@ void GSU::op_ror() {
|
|||
}
|
||||
|
||||
//$98-9d(alt0): jmp rN
|
||||
template<int n> void GSU::op_jmp_r() {
|
||||
template<int n>
|
||||
auto GSU::op_jmp_r() {
|
||||
regs.r[15] = regs.r[n];
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$98-9d(alt1): ljmp rN
|
||||
template<int n> void GSU::op_ljmp_r() {
|
||||
template<int n>
|
||||
auto GSU::op_ljmp_r() {
|
||||
regs.pbr = regs.r[n] & 0x7f;
|
||||
regs.r[15] = regs.sr();
|
||||
regs.cbr = regs.r[15] & 0xfff0;
|
||||
|
|
@ -459,7 +484,7 @@ template<int n> void GSU::op_ljmp_r() {
|
|||
}
|
||||
|
||||
//$9e: lob
|
||||
void GSU::op_lob() {
|
||||
auto GSU::op_lob() {
|
||||
regs.dr() = regs.sr() & 0xff;
|
||||
regs.sfr.s = (regs.dr() & 0x80);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -467,7 +492,7 @@ void GSU::op_lob() {
|
|||
}
|
||||
|
||||
//$9f(alt0): fmult
|
||||
void GSU::op_fmult() {
|
||||
auto GSU::op_fmult() {
|
||||
uint32_t result = (int16_t)regs.sr() * (int16_t)regs.r[6];
|
||||
regs.dr() = result >> 16;
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
|
|
@ -478,7 +503,7 @@ void GSU::op_fmult() {
|
|||
}
|
||||
|
||||
//$9f(alt1): lmult
|
||||
void GSU::op_lmult() {
|
||||
auto GSU::op_lmult() {
|
||||
uint32_t result = (int16_t)regs.sr() * (int16_t)regs.r[6];
|
||||
regs.r[4] = result;
|
||||
regs.dr() = result >> 16;
|
||||
|
|
@ -490,13 +515,15 @@ void GSU::op_lmult() {
|
|||
}
|
||||
|
||||
//$a0-af(alt0): ibt rN,#pp
|
||||
template<int n> void GSU::op_ibt_r() {
|
||||
template<int n>
|
||||
auto GSU::op_ibt_r() {
|
||||
regs.r[n] = (int8)pipe();
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$a0-af(alt1): lms rN,(yy)
|
||||
template<int n> void GSU::op_lms_r() {
|
||||
template<int n>
|
||||
auto GSU::op_lms_r() {
|
||||
regs.ramaddr = pipe() << 1;
|
||||
uint16_t data;
|
||||
data = rambuffer_read(regs.ramaddr ^ 0) << 0;
|
||||
|
|
@ -506,7 +533,8 @@ template<int n> void GSU::op_lms_r() {
|
|||
}
|
||||
|
||||
//$a0-af(alt2): sms (yy),rN
|
||||
template<int n> void GSU::op_sms_r() {
|
||||
template<int n>
|
||||
auto GSU::op_sms_r() {
|
||||
regs.ramaddr = pipe() << 1;
|
||||
rambuffer_write(regs.ramaddr ^ 0, regs.r[n] >> 0);
|
||||
rambuffer_write(regs.ramaddr ^ 1, regs.r[n] >> 8);
|
||||
|
|
@ -515,7 +543,8 @@ template<int n> void GSU::op_sms_r() {
|
|||
|
||||
//$b0-bf(b0): from rN
|
||||
//$b0-bf(b1): moves rN
|
||||
template<int n> void GSU::op_from_r() {
|
||||
template<int n>
|
||||
auto GSU::op_from_r() {
|
||||
if(regs.sfr.b == 0) {
|
||||
regs.sreg = n;
|
||||
} else {
|
||||
|
|
@ -528,7 +557,7 @@ template<int n> void GSU::op_from_r() {
|
|||
}
|
||||
|
||||
//$c0: hib
|
||||
void GSU::op_hib() {
|
||||
auto GSU::op_hib() {
|
||||
regs.dr() = regs.sr() >> 8;
|
||||
regs.sfr.s = (regs.dr() & 0x80);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -536,7 +565,8 @@ void GSU::op_hib() {
|
|||
}
|
||||
|
||||
//$c1-cf(alt0): or rN
|
||||
template<int n> void GSU::op_or_r() {
|
||||
template<int n>
|
||||
auto GSU::op_or_r() {
|
||||
regs.dr() = regs.sr() | regs.r[n];
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -544,7 +574,8 @@ template<int n> void GSU::op_or_r() {
|
|||
}
|
||||
|
||||
//$c1-cf(alt1): xor rN
|
||||
template<int n> void GSU::op_xor_r() {
|
||||
template<int n>
|
||||
auto GSU::op_xor_r() {
|
||||
regs.dr() = regs.sr() ^ regs.r[n];
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -552,7 +583,8 @@ template<int n> void GSU::op_xor_r() {
|
|||
}
|
||||
|
||||
//$c1-cf(alt2): or #N
|
||||
template<int n> void GSU::op_or_i() {
|
||||
template<int n>
|
||||
auto GSU::op_or_i() {
|
||||
regs.dr() = regs.sr() | n;
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -560,7 +592,8 @@ template<int n> void GSU::op_or_i() {
|
|||
}
|
||||
|
||||
//$c1-cf(alt3): xor #N
|
||||
template<int n> void GSU::op_xor_i() {
|
||||
template<int n>
|
||||
auto GSU::op_xor_i() {
|
||||
regs.dr() = regs.sr() ^ n;
|
||||
regs.sfr.s = (regs.dr() & 0x8000);
|
||||
regs.sfr.z = (regs.dr() == 0);
|
||||
|
|
@ -568,7 +601,8 @@ template<int n> void GSU::op_xor_i() {
|
|||
}
|
||||
|
||||
//$d0-de: inc rN
|
||||
template<int n> void GSU::op_inc_r() {
|
||||
template<int n>
|
||||
auto GSU::op_inc_r() {
|
||||
regs.r[n]++;
|
||||
regs.sfr.s = (regs.r[n] & 0x8000);
|
||||
regs.sfr.z = (regs.r[n] == 0);
|
||||
|
|
@ -576,27 +610,28 @@ template<int n> void GSU::op_inc_r() {
|
|||
}
|
||||
|
||||
//$df(alt0): getc
|
||||
void GSU::op_getc() {
|
||||
auto GSU::op_getc() {
|
||||
regs.colr = color(rombuffer_read());
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$df(alt2): ramb
|
||||
void GSU::op_ramb() {
|
||||
auto GSU::op_ramb() {
|
||||
rambuffer_sync();
|
||||
regs.rambr = regs.sr();
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$df(alt3): romb
|
||||
void GSU::op_romb() {
|
||||
auto GSU::op_romb() {
|
||||
rombuffer_sync();
|
||||
regs.rombr = regs.sr() & 0x7f;
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$e0-ee: dec rN
|
||||
template<int n> void GSU::op_dec_r() {
|
||||
template<int n>
|
||||
auto GSU::op_dec_r() {
|
||||
regs.r[n]--;
|
||||
regs.sfr.s = (regs.r[n] & 0x8000);
|
||||
regs.sfr.z = (regs.r[n] == 0);
|
||||
|
|
@ -604,31 +639,32 @@ template<int n> void GSU::op_dec_r() {
|
|||
}
|
||||
|
||||
//$ef(alt0): getb
|
||||
void GSU::op_getb() {
|
||||
auto GSU::op_getb() {
|
||||
regs.dr() = rombuffer_read();
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$ef(alt1): getbh
|
||||
void GSU::op_getbh() {
|
||||
auto GSU::op_getbh() {
|
||||
regs.dr() = (rombuffer_read() << 8) | (regs.sr() & 0x00ff);
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$ef(alt2): getbl
|
||||
void GSU::op_getbl() {
|
||||
auto GSU::op_getbl() {
|
||||
regs.dr() = (regs.sr() & 0xff00) | (rombuffer_read() << 0);
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$ef(alt3): getbs
|
||||
void GSU::op_getbs() {
|
||||
auto GSU::op_getbs() {
|
||||
regs.dr() = (int8)rombuffer_read();
|
||||
regs.reset();
|
||||
}
|
||||
|
||||
//$f0-ff(alt0): iwt rN,#xx
|
||||
template<int n> void GSU::op_iwt_r() {
|
||||
template<int n>
|
||||
auto GSU::op_iwt_r() {
|
||||
uint16_t data;
|
||||
data = pipe() << 0;
|
||||
data |= pipe() << 8;
|
||||
|
|
@ -637,7 +673,8 @@ template<int n> void GSU::op_iwt_r() {
|
|||
}
|
||||
|
||||
//$f0-ff(alt1): lm rN,(xx)
|
||||
template<int n> void GSU::op_lm_r() {
|
||||
template<int n>
|
||||
auto GSU::op_lm_r() {
|
||||
regs.ramaddr = pipe() << 0;
|
||||
regs.ramaddr |= pipe() << 8;
|
||||
uint16_t data;
|
||||
|
|
@ -648,7 +685,8 @@ template<int n> void GSU::op_lm_r() {
|
|||
}
|
||||
|
||||
//$f0-ff(alt2): sm (xx),rN
|
||||
template<int n> void GSU::op_sm_r() {
|
||||
template<int n>
|
||||
auto GSU::op_sm_r() {
|
||||
regs.ramaddr = pipe() << 0;
|
||||
regs.ramaddr |= pipe() << 8;
|
||||
rambuffer_write(regs.ramaddr ^ 0, regs.r[n] >> 0);
|
||||
|
|
|
|||
|
|
@ -1,34 +1,36 @@
|
|||
//accepts a callback binding so r14 writes can trigger ROM buffering transparently
|
||||
struct reg16_t {
|
||||
uint16 data;
|
||||
function<void (uint16)> modify;
|
||||
uint16 data = 0;
|
||||
function<auto (uint16) -> void> modify;
|
||||
|
||||
inline operator unsigned() const { return data; }
|
||||
inline uint16 assign(uint16 i) {
|
||||
inline operator unsigned() const {
|
||||
return data;
|
||||
}
|
||||
|
||||
inline auto assign(uint16 i) -> uint16 {
|
||||
if(modify) modify(i);
|
||||
else data = i;
|
||||
return data;
|
||||
}
|
||||
|
||||
inline unsigned operator++() { return assign(data + 1); }
|
||||
inline unsigned operator--() { return assign(data - 1); }
|
||||
inline unsigned operator++(int) { unsigned r = data; assign(data + 1); return r; }
|
||||
inline unsigned operator--(int) { unsigned r = data; assign(data - 1); return r; }
|
||||
inline unsigned operator = (unsigned i) { return assign(i); }
|
||||
inline unsigned operator |= (unsigned i) { return assign(data | i); }
|
||||
inline unsigned operator ^= (unsigned i) { return assign(data ^ i); }
|
||||
inline unsigned operator &= (unsigned i) { return assign(data & i); }
|
||||
inline unsigned operator <<= (unsigned i) { return assign(data << i); }
|
||||
inline unsigned operator >>= (unsigned i) { return assign(data >> i); }
|
||||
inline unsigned operator += (unsigned i) { return assign(data + i); }
|
||||
inline unsigned operator -= (unsigned i) { return assign(data - i); }
|
||||
inline unsigned operator *= (unsigned i) { return assign(data * i); }
|
||||
inline unsigned operator /= (unsigned i) { return assign(data / i); }
|
||||
inline unsigned operator %= (unsigned i) { return assign(data % i); }
|
||||
inline auto operator++() { return assign(data + 1); }
|
||||
inline auto operator--() { return assign(data - 1); }
|
||||
inline auto operator++(int) { unsigned r = data; assign(data + 1); return r; }
|
||||
inline auto operator--(int) { unsigned r = data; assign(data - 1); return r; }
|
||||
inline auto operator = (unsigned i) { return assign(i); }
|
||||
inline auto operator |= (unsigned i) { return assign(data | i); }
|
||||
inline auto operator ^= (unsigned i) { return assign(data ^ i); }
|
||||
inline auto operator &= (unsigned i) { return assign(data & i); }
|
||||
inline auto operator <<= (unsigned i) { return assign(data << i); }
|
||||
inline auto operator >>= (unsigned i) { return assign(data >> i); }
|
||||
inline auto operator += (unsigned i) { return assign(data + i); }
|
||||
inline auto operator -= (unsigned i) { return assign(data - i); }
|
||||
inline auto operator *= (unsigned i) { return assign(data * i); }
|
||||
inline auto operator /= (unsigned i) { return assign(data / i); }
|
||||
inline auto operator %= (unsigned i) { return assign(data % i); }
|
||||
|
||||
inline unsigned operator = (const reg16_t& i) { return assign(i); }
|
||||
inline auto operator = (const reg16_t& i) { return assign(i); }
|
||||
|
||||
reg16_t() : data(0) {}
|
||||
reg16_t(const reg16_t&) = delete;
|
||||
};
|
||||
|
||||
|
|
@ -51,7 +53,7 @@ struct sfr_t {
|
|||
| (r << 6) | (g << 5) | (ov << 4) | (s << 3) | (cy << 2) | (z << 1);
|
||||
}
|
||||
|
||||
sfr_t& operator=(uint16_t data) {
|
||||
auto& operator=(uint16_t data) {
|
||||
irq = data & 0x8000;
|
||||
b = data & 0x1000;
|
||||
ih = data & 0x0800;
|
||||
|
|
@ -78,7 +80,7 @@ struct scmr_t {
|
|||
return ((ht >> 1) << 5) | (ron << 4) | (ran << 3) | ((ht & 1) << 2) | (md);
|
||||
}
|
||||
|
||||
scmr_t& operator=(uint8 data) {
|
||||
auto& operator=(uint8 data) {
|
||||
ht = (bool)(data & 0x20) << 1;
|
||||
ht |= (bool)(data & 0x04) << 0;
|
||||
ron = data & 0x10;
|
||||
|
|
@ -99,7 +101,7 @@ struct por_t {
|
|||
return (obj << 4) | (freezehigh << 3) | (highnibble << 2) | (dither << 1) | (transparent);
|
||||
}
|
||||
|
||||
por_t& operator=(uint8 data) {
|
||||
auto& operator=(uint8 data) {
|
||||
obj = data & 0x10;
|
||||
freezehigh = data & 0x08;
|
||||
highnibble = data & 0x04;
|
||||
|
|
@ -117,7 +119,7 @@ struct cfgr_t {
|
|||
return (irq << 7) | (ms0 << 5);
|
||||
}
|
||||
|
||||
cfgr_t& operator=(uint8 data) {
|
||||
auto& operator=(uint8 data) {
|
||||
irq = data & 0x80;
|
||||
ms0 = data & 0x20;
|
||||
return *this;
|
||||
|
|
@ -151,10 +153,10 @@ struct regs_t {
|
|||
uint8 ramdr; //RAM buffer data register
|
||||
|
||||
unsigned sreg, dreg;
|
||||
reg16_t& sr() { return r[sreg]; } //source register (from)
|
||||
reg16_t& dr() { return r[dreg]; } //destination register (to)
|
||||
auto& sr() { return r[sreg]; } //source register (from)
|
||||
auto& dr() { return r[dreg]; } //destination register (to)
|
||||
|
||||
void reset() {
|
||||
auto reset() -> void {
|
||||
sfr.b = 0;
|
||||
sfr.alt1 = 0;
|
||||
sfr.alt2 = 0;
|
||||
|
|
|
|||
|
|
@ -1,4 +1,6 @@
|
|||
void GSU::serialize(serializer& s) {
|
||||
auto GSU::serialize(serializer& s) -> void {
|
||||
s.integer(clockmode);
|
||||
|
||||
s.integer(regs.pipeline);
|
||||
s.integer(regs.ramaddr);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
void GSU::initialize_opcode_table() {
|
||||
auto GSU::initialize_opcode_table() -> void {
|
||||
#define op4(id, name) \
|
||||
op(id+ 0, name< 1>) op(id+ 1, name< 2>) op(id+ 2, name< 3>) op(id+ 3, name< 4>)
|
||||
|
||||
|
|
|
|||
|
|
@ -2,11 +2,11 @@
|
|||
|
||||
//ROM / RAM access from the S-CPU
|
||||
|
||||
unsigned SuperFX::CPUROM::size() const {
|
||||
auto SuperFX::CPUROM::size() const -> unsigned {
|
||||
return superfx.rom.size();
|
||||
}
|
||||
|
||||
uint8 SuperFX::CPUROM::read(unsigned addr) {
|
||||
auto SuperFX::CPUROM::read(unsigned addr) -> uint8 {
|
||||
if(superfx.regs.sfr.g && superfx.regs.scmr.ron) {
|
||||
static const uint8_t data[16] = {
|
||||
0x00, 0x01, 0x00, 0x01, 0x04, 0x01, 0x00, 0x01,
|
||||
|
|
@ -17,20 +17,20 @@ uint8 SuperFX::CPUROM::read(unsigned addr) {
|
|||
return superfx.rom.read(addr);
|
||||
}
|
||||
|
||||
void SuperFX::CPUROM::write(unsigned addr, uint8 data) {
|
||||
auto SuperFX::CPUROM::write(unsigned addr, uint8 data) -> void {
|
||||
superfx.rom.write(addr, data);
|
||||
}
|
||||
|
||||
unsigned SuperFX::CPURAM::size() const {
|
||||
auto SuperFX::CPURAM::size() const -> unsigned {
|
||||
return superfx.ram.size();
|
||||
}
|
||||
|
||||
uint8 SuperFX::CPURAM::read(unsigned addr) {
|
||||
auto SuperFX::CPURAM::read(unsigned addr) -> uint8 {
|
||||
if(superfx.regs.sfr.g && superfx.regs.scmr.ran) return cpu.regs.mdr;
|
||||
return superfx.ram.read(addr);
|
||||
}
|
||||
|
||||
void SuperFX::CPURAM::write(unsigned addr, uint8 data) {
|
||||
auto SuperFX::CPURAM::write(unsigned addr, uint8 data) -> void {
|
||||
superfx.ram.write(addr, data);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
struct CPUROM : Memory {
|
||||
unsigned size() const;
|
||||
uint8 read(unsigned);
|
||||
void write(unsigned, uint8);
|
||||
auto size() const -> unsigned;
|
||||
auto read(unsigned) -> uint8;
|
||||
auto write(unsigned, uint8) -> void;
|
||||
} cpurom;
|
||||
|
||||
struct CPURAM : Memory {
|
||||
unsigned size() const;
|
||||
uint8 read(unsigned);
|
||||
void write(unsigned, uint8);
|
||||
auto size() const -> unsigned;
|
||||
auto read(unsigned) -> uint8;
|
||||
auto write(unsigned, uint8) -> void;
|
||||
} cpuram;
|
||||
|
|
|
|||
|
|
@ -1,16 +1,16 @@
|
|||
#ifdef SUPERFX_CPP
|
||||
|
||||
void SuperFX::stop() {
|
||||
auto SuperFX::stop() -> void {
|
||||
cpu.regs.irq = 1;
|
||||
}
|
||||
|
||||
uint8 SuperFX::color(uint8 source) {
|
||||
auto SuperFX::color(uint8 source) -> uint8 {
|
||||
if(regs.por.highnibble) return (regs.colr & 0xf0) | (source >> 4);
|
||||
if(regs.por.freezehigh) return (regs.colr & 0xf0) | (source & 0x0f);
|
||||
return source;
|
||||
}
|
||||
|
||||
void SuperFX::plot(uint8 x, uint8 y) {
|
||||
auto SuperFX::plot(uint8 x, uint8 y) -> void {
|
||||
uint8 color = regs.colr;
|
||||
|
||||
if(regs.por.dither && regs.scmr.md != 3) {
|
||||
|
|
@ -48,7 +48,7 @@ void SuperFX::plot(uint8 x, uint8 y) {
|
|||
}
|
||||
}
|
||||
|
||||
uint8 SuperFX::rpix(uint8 x, uint8 y) {
|
||||
auto SuperFX::rpix(uint8 x, uint8 y) -> uint8 {
|
||||
pixelcache_flush(pixelcache[1]);
|
||||
pixelcache_flush(pixelcache[0]);
|
||||
|
||||
|
|
@ -66,14 +66,14 @@ uint8 SuperFX::rpix(uint8 x, uint8 y) {
|
|||
|
||||
for(unsigned n = 0; n < bpp; n++) {
|
||||
unsigned byte = ((n >> 1) << 4) + (n & 1); // = [n]{ 0, 1, 16, 17, 32, 33, 48, 49 };
|
||||
step(memory_access_speed);
|
||||
step(memory_access_speed());
|
||||
data |= ((bus_read(addr + byte) >> x) & 1) << n;
|
||||
}
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
void SuperFX::pixelcache_flush(pixelcache_t& cache) {
|
||||
auto SuperFX::pixelcache_flush(pixelcache_t& cache) -> void {
|
||||
if(cache.bitpend == 0x00) return;
|
||||
|
||||
uint8 x = cache.offset << 3;
|
||||
|
|
@ -94,11 +94,11 @@ void SuperFX::pixelcache_flush(pixelcache_t& cache) {
|
|||
uint8 data = 0x00;
|
||||
for(unsigned x = 0; x < 8; x++) data |= ((cache.data[x] >> n) & 1) << x;
|
||||
if(cache.bitpend != 0xff) {
|
||||
step(memory_access_speed);
|
||||
step(memory_access_speed());
|
||||
data &= cache.bitpend;
|
||||
data |= bus_read(addr + byte) & ~cache.bitpend;
|
||||
}
|
||||
step(memory_access_speed);
|
||||
step(memory_access_speed());
|
||||
bus_write(addr + byte, data);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
void stop();
|
||||
uint8 color(uint8 source);
|
||||
void plot(uint8 x, uint8 y);
|
||||
uint8 rpix(uint8 x, uint8 y);
|
||||
void pixelcache_flush(pixelcache_t& cache);
|
||||
auto stop() -> void;
|
||||
auto color(uint8 source) -> uint8;
|
||||
auto plot(uint8 x, uint8 y) -> void;
|
||||
auto rpix(uint8 x, uint8 y) -> uint8;
|
||||
auto pixelcache_flush(pixelcache_t& cache) -> void;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
//TODO: this belongs in processor/gsu
|
||||
|
||||
void SuperFX::disassemble_opcode(char* output) {
|
||||
auto SuperFX::disassemble_opcode(char* output) -> void {
|
||||
*output = 0;
|
||||
|
||||
if(!regs.sfr.alt2) {
|
||||
|
|
@ -41,7 +41,7 @@ void SuperFX::disassemble_opcode(char* output) {
|
|||
#define op1 bus_read((regs.pbr << 16) + regs.r[15] + 0)
|
||||
#define op2 bus_read((regs.pbr << 16) + regs.r[15] + 1)
|
||||
|
||||
void SuperFX::disassemble_alt0(char* output) {
|
||||
auto SuperFX::disassemble_alt0(char* output) -> void {
|
||||
char t[256] = "";
|
||||
switch(op0) {
|
||||
case (0x00): sprintf(t, "stop"); break;
|
||||
|
|
@ -98,7 +98,7 @@ void SuperFX::disassemble_alt0(char* output) {
|
|||
strcat(output, t);
|
||||
}
|
||||
|
||||
void SuperFX::disassemble_alt1(char* output) {
|
||||
auto SuperFX::disassemble_alt1(char* output) -> void {
|
||||
char t[256] = "";
|
||||
switch(op0) {
|
||||
case (0x00): sprintf(t, "stop"); break;
|
||||
|
|
@ -155,7 +155,7 @@ void SuperFX::disassemble_alt1(char* output) {
|
|||
strcat(output, t);
|
||||
}
|
||||
|
||||
void SuperFX::disassemble_alt2(char* output) {
|
||||
auto SuperFX::disassemble_alt2(char* output) -> void {
|
||||
char t[256] = "";
|
||||
switch(op0) {
|
||||
case (0x00): sprintf(t, "stop"); break;
|
||||
|
|
@ -212,7 +212,7 @@ void SuperFX::disassemble_alt2(char* output) {
|
|||
strcat(output, t);
|
||||
}
|
||||
|
||||
void SuperFX::disassemble_alt3(char* output) {
|
||||
auto SuperFX::disassemble_alt3(char* output) -> void {
|
||||
char t[256] = "";
|
||||
switch(op0) {
|
||||
case (0x00): sprintf(t, "stop"); break;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
void disassemble_opcode(char* output);
|
||||
void disassemble_alt0(char* output);
|
||||
void disassemble_alt1(char* output);
|
||||
void disassemble_alt2(char* output);
|
||||
void disassemble_alt3(char* output);
|
||||
auto disassemble_opcode(char* output) -> void;
|
||||
auto disassemble_alt0(char* output) -> void;
|
||||
auto disassemble_alt1(char* output) -> void;
|
||||
auto disassemble_alt2(char* output) -> void;
|
||||
auto disassemble_alt3(char* output) -> void;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#ifdef SUPERFX_CPP
|
||||
|
||||
uint8 SuperFX::bus_read(unsigned addr) {
|
||||
auto SuperFX::bus_read(unsigned addr) -> uint8 {
|
||||
if((addr & 0xc00000) == 0x000000) { //$00-3f:0000-7fff, $00-3f:8000-ffff
|
||||
while(!regs.scmr.ron && scheduler.sync != Scheduler::SynchronizeMode::All) {
|
||||
step(6);
|
||||
|
|
@ -26,7 +26,7 @@ uint8 SuperFX::bus_read(unsigned addr) {
|
|||
}
|
||||
}
|
||||
|
||||
void SuperFX::bus_write(unsigned addr, uint8 data) {
|
||||
auto SuperFX::bus_write(unsigned addr, uint8 data) -> void {
|
||||
if((addr & 0xe00000) == 0x600000) { //$60-7f:0000-ffff
|
||||
while(!regs.scmr.ran && scheduler.sync != Scheduler::SynchronizeMode::All) {
|
||||
step(6);
|
||||
|
|
@ -36,19 +36,19 @@ void SuperFX::bus_write(unsigned addr, uint8 data) {
|
|||
}
|
||||
}
|
||||
|
||||
uint8 SuperFX::op_read(uint16 addr) {
|
||||
auto SuperFX::op_read(uint16 addr) -> uint8 {
|
||||
uint16 offset = addr - regs.cbr;
|
||||
if(offset < 512) {
|
||||
if(cache.valid[offset >> 4] == false) {
|
||||
unsigned dp = offset & 0xfff0;
|
||||
unsigned sp = (regs.pbr << 16) + ((regs.cbr + dp) & 0xfff0);
|
||||
for(unsigned n = 0; n < 16; n++) {
|
||||
step(memory_access_speed);
|
||||
step(memory_access_speed());
|
||||
cache.buffer[dp++] = bus_read(sp++);
|
||||
}
|
||||
cache.valid[offset >> 4] = true;
|
||||
} else {
|
||||
step(cache_access_speed);
|
||||
step(cache_access_speed());
|
||||
}
|
||||
return cache.buffer[offset];
|
||||
}
|
||||
|
|
@ -56,46 +56,46 @@ uint8 SuperFX::op_read(uint16 addr) {
|
|||
if(regs.pbr <= 0x5f) {
|
||||
//$[00-5f]:[0000-ffff] ROM
|
||||
rombuffer_sync();
|
||||
step(memory_access_speed);
|
||||
step(memory_access_speed());
|
||||
return bus_read((regs.pbr << 16) + addr);
|
||||
} else {
|
||||
//$[60-7f]:[0000-ffff] RAM
|
||||
rambuffer_sync();
|
||||
step(memory_access_speed);
|
||||
step(memory_access_speed());
|
||||
return bus_read((regs.pbr << 16) + addr);
|
||||
}
|
||||
}
|
||||
|
||||
uint8 SuperFX::peekpipe() {
|
||||
auto SuperFX::peekpipe() -> uint8 {
|
||||
uint8 result = regs.pipeline;
|
||||
regs.pipeline = op_read(regs.r[15]);
|
||||
r15_modified = false;
|
||||
return result;
|
||||
}
|
||||
|
||||
uint8 SuperFX::pipe() {
|
||||
auto SuperFX::pipe() -> uint8 {
|
||||
uint8 result = regs.pipeline;
|
||||
regs.pipeline = op_read(++regs.r[15]);
|
||||
r15_modified = false;
|
||||
return result;
|
||||
}
|
||||
|
||||
void SuperFX::cache_flush() {
|
||||
auto SuperFX::cache_flush() -> void {
|
||||
for(unsigned n = 0; n < 32; n++) cache.valid[n] = false;
|
||||
}
|
||||
|
||||
uint8 SuperFX::cache_mmio_read(uint16 addr) {
|
||||
auto SuperFX::cache_mmio_read(uint16 addr) -> uint8 {
|
||||
addr = (addr + regs.cbr) & 511;
|
||||
return cache.buffer[addr];
|
||||
}
|
||||
|
||||
void SuperFX::cache_mmio_write(uint16 addr, uint8 data) {
|
||||
auto SuperFX::cache_mmio_write(uint16 addr, uint8 data) -> void {
|
||||
addr = (addr + regs.cbr) & 511;
|
||||
cache.buffer[addr] = data;
|
||||
if((addr & 15) == 15) cache.valid[addr >> 4] = true;
|
||||
}
|
||||
|
||||
void SuperFX::memory_reset() {
|
||||
auto SuperFX::memory_reset() -> void {
|
||||
rom_mask = rom.size() - 1;
|
||||
ram_mask = ram.size() - 1;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,14 +1,15 @@
|
|||
unsigned rom_mask; //rom_size - 1
|
||||
unsigned ram_mask; //ram_size - 1
|
||||
uint8 bus_read(unsigned addr);
|
||||
void bus_write(unsigned addr, uint8 data);
|
||||
|
||||
uint8 op_read(uint16 addr);
|
||||
alwaysinline uint8 peekpipe();
|
||||
alwaysinline uint8 pipe();
|
||||
auto bus_read(unsigned addr) -> uint8;
|
||||
auto bus_write(unsigned addr, uint8 data) -> void;
|
||||
|
||||
void cache_flush();
|
||||
uint8 cache_mmio_read(uint16 addr);
|
||||
void cache_mmio_write(uint16 addr, uint8 data);
|
||||
auto op_read(uint16 addr) -> uint8;
|
||||
alwaysinline auto peekpipe() -> uint8;
|
||||
alwaysinline auto pipe() -> uint8;
|
||||
|
||||
void memory_reset();
|
||||
auto cache_flush() -> void;
|
||||
auto cache_mmio_read(uint16 addr) -> uint8;
|
||||
auto cache_mmio_write(uint16 addr, uint8 data) -> void;
|
||||
|
||||
auto memory_reset() -> void;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#ifdef SUPERFX_CPP
|
||||
|
||||
uint8 SuperFX::mmio_read(unsigned addr) {
|
||||
auto SuperFX::mmio_read(unsigned addr) -> uint8 {
|
||||
cpu.synchronize_coprocessors();
|
||||
addr &= 0xffff;
|
||||
|
||||
|
|
@ -52,7 +52,7 @@ uint8 SuperFX::mmio_read(unsigned addr) {
|
|||
return 0x00;
|
||||
}
|
||||
|
||||
void SuperFX::mmio_write(unsigned addr, uint8 data) {
|
||||
auto SuperFX::mmio_write(unsigned addr, uint8 data) -> void {
|
||||
cpu.synchronize_coprocessors();
|
||||
addr &= 0xffff;
|
||||
|
||||
|
|
@ -97,7 +97,6 @@ void SuperFX::mmio_write(unsigned addr, uint8 data) {
|
|||
|
||||
case 0x3037: {
|
||||
regs.cfgr = data;
|
||||
update_speed();
|
||||
} break;
|
||||
|
||||
case 0x3038: {
|
||||
|
|
@ -106,7 +105,6 @@ void SuperFX::mmio_write(unsigned addr, uint8 data) {
|
|||
|
||||
case 0x3039: {
|
||||
regs.clsr = data;
|
||||
update_speed();
|
||||
} break;
|
||||
|
||||
case 0x303a: {
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
uint8 mmio_read(unsigned addr);
|
||||
void mmio_write(unsigned addr, uint8 data);
|
||||
auto mmio_read(unsigned addr) -> uint8;
|
||||
auto mmio_write(unsigned addr, uint8 data) -> void;
|
||||
|
|
|
|||
|
|
@ -1,16 +1,11 @@
|
|||
#ifdef SUPERFX_CPP
|
||||
|
||||
void SuperFX::serialize(serializer& s) {
|
||||
auto SuperFX::serialize(serializer& s) -> void {
|
||||
GSU::serialize(s);
|
||||
Thread::serialize(s);
|
||||
|
||||
s.array(ram.data(), ram.size());
|
||||
|
||||
s.integer(clockmode);
|
||||
s.integer(instruction_counter);
|
||||
|
||||
s.integer(cache_access_speed);
|
||||
s.integer(memory_access_speed);
|
||||
s.integer(r15_modified);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -13,9 +13,11 @@ namespace SuperFamicom {
|
|||
|
||||
SuperFX superfx;
|
||||
|
||||
void SuperFX::Enter() { superfx.enter(); }
|
||||
auto SuperFX::Enter() -> void {
|
||||
superfx.enter();
|
||||
}
|
||||
|
||||
void SuperFX::enter() {
|
||||
auto SuperFX::enter() -> void {
|
||||
while(true) {
|
||||
if(scheduler.sync == Scheduler::SynchronizeMode::All) {
|
||||
scheduler.exit(Scheduler::ExitReason::SynchronizeEvent);
|
||||
|
|
@ -37,25 +39,25 @@ void SuperFX::enter() {
|
|||
}
|
||||
}
|
||||
|
||||
void SuperFX::init() {
|
||||
auto SuperFX::init() -> void {
|
||||
initialize_opcode_table();
|
||||
regs.r[14].modify = {&SuperFX::r14_modify, this};
|
||||
regs.r[15].modify = {&SuperFX::r15_modify, this};
|
||||
}
|
||||
|
||||
void SuperFX::load() {
|
||||
auto SuperFX::load() -> void {
|
||||
}
|
||||
|
||||
void SuperFX::unload() {
|
||||
auto SuperFX::unload() -> void {
|
||||
rom.reset();
|
||||
ram.reset();
|
||||
}
|
||||
|
||||
void SuperFX::power() {
|
||||
auto SuperFX::power() -> void {
|
||||
GSU::power();
|
||||
}
|
||||
|
||||
void SuperFX::reset() {
|
||||
auto SuperFX::reset() -> void {
|
||||
GSU::reset();
|
||||
create(SuperFX::Enter, system.cpu_frequency());
|
||||
instruction_counter = 0;
|
||||
|
|
|
|||
|
|
@ -9,18 +9,21 @@ struct SuperFX : Processor::GSU, Coprocessor {
|
|||
#include "timing/timing.hpp"
|
||||
#include "disassembler/disassembler.hpp"
|
||||
|
||||
static void Enter();
|
||||
void enter();
|
||||
void init();
|
||||
void load();
|
||||
void unload();
|
||||
void power();
|
||||
void reset();
|
||||
void serialize(serializer&);
|
||||
//superfx.cpp
|
||||
static auto Enter() -> void;
|
||||
|
||||
auto enter() -> void;
|
||||
auto init() -> void;
|
||||
auto load() -> void;
|
||||
auto unload() -> void;
|
||||
auto power() -> void;
|
||||
auto reset() -> void;
|
||||
|
||||
//serialization.cpp
|
||||
auto serialize(serializer&) -> void;
|
||||
|
||||
privileged:
|
||||
unsigned clockmode = 0; //0 = selectable, 1 = force 10.74mhz, 2 = force 21.48mhz
|
||||
unsigned instruction_counter;
|
||||
unsigned instruction_counter = 0;
|
||||
};
|
||||
|
||||
extern SuperFX superfx;
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#ifdef SUPERFX_CPP
|
||||
|
||||
void SuperFX::step(unsigned clocks) {
|
||||
auto SuperFX::step(unsigned clocks) -> void {
|
||||
if(regs.romcl) {
|
||||
regs.romcl -= min(clocks, regs.romcl);
|
||||
if(regs.romcl == 0) {
|
||||
|
|
@ -20,70 +20,47 @@ void SuperFX::step(unsigned clocks) {
|
|||
synchronize_cpu();
|
||||
}
|
||||
|
||||
void SuperFX::rombuffer_sync() {
|
||||
auto SuperFX::rombuffer_sync() -> void {
|
||||
if(regs.romcl) step(regs.romcl);
|
||||
}
|
||||
|
||||
void SuperFX::rombuffer_update() {
|
||||
auto SuperFX::rombuffer_update() -> void {
|
||||
regs.sfr.r = 1;
|
||||
regs.romcl = memory_access_speed;
|
||||
regs.romcl = memory_access_speed();
|
||||
}
|
||||
|
||||
uint8 SuperFX::rombuffer_read() {
|
||||
auto SuperFX::rombuffer_read() -> uint8 {
|
||||
rombuffer_sync();
|
||||
return regs.romdr;
|
||||
}
|
||||
|
||||
void SuperFX::rambuffer_sync() {
|
||||
auto SuperFX::rambuffer_sync() -> void {
|
||||
if(regs.ramcl) step(regs.ramcl);
|
||||
}
|
||||
|
||||
uint8 SuperFX::rambuffer_read(uint16 addr) {
|
||||
auto SuperFX::rambuffer_read(uint16 addr) -> uint8 {
|
||||
rambuffer_sync();
|
||||
return bus_read(0x700000 + (regs.rambr << 16) + addr);
|
||||
}
|
||||
|
||||
void SuperFX::rambuffer_write(uint16 addr, uint8 data) {
|
||||
auto SuperFX::rambuffer_write(uint16 addr, uint8 data) -> void {
|
||||
rambuffer_sync();
|
||||
regs.ramcl = memory_access_speed;
|
||||
regs.ramcl = memory_access_speed();
|
||||
regs.ramar = addr;
|
||||
regs.ramdr = data;
|
||||
}
|
||||
|
||||
void SuperFX::r14_modify(uint16 data) {
|
||||
auto SuperFX::r14_modify(uint16 data) -> void {
|
||||
regs.r[14].data = data;
|
||||
rombuffer_update();
|
||||
}
|
||||
|
||||
void SuperFX::r15_modify(uint16 data) {
|
||||
auto SuperFX::r15_modify(uint16 data) -> void {
|
||||
regs.r[15].data = data;
|
||||
r15_modified = true;
|
||||
}
|
||||
|
||||
void SuperFX::update_speed() {
|
||||
//force SuperFX1 mode?
|
||||
if(clockmode == 1) {
|
||||
cache_access_speed = 2;
|
||||
memory_access_speed = 6;
|
||||
return;
|
||||
}
|
||||
|
||||
//force SuperFX2 mode?
|
||||
if(clockmode == 2) {
|
||||
cache_access_speed = 1;
|
||||
memory_access_speed = 5;
|
||||
regs.cfgr.ms0 = 0; //cannot use high-speed multiplication in 21MHz mode
|
||||
return;
|
||||
}
|
||||
|
||||
//default: allow S-CPU to select mode
|
||||
cache_access_speed = (regs.clsr ? 1 : 2);
|
||||
memory_access_speed = (regs.clsr ? 5 : 6);
|
||||
if(regs.clsr) regs.cfgr.ms0 = 0; //cannot use high-speed multiplication in 21MHz mode
|
||||
}
|
||||
|
||||
void SuperFX::timing_reset() {
|
||||
update_speed();
|
||||
auto SuperFX::timing_reset() -> void {
|
||||
r15_modified = false;
|
||||
|
||||
regs.romcl = 0;
|
||||
|
|
|
|||
|
|
@ -1,19 +1,16 @@
|
|||
unsigned cache_access_speed;
|
||||
unsigned memory_access_speed;
|
||||
bool r15_modified;
|
||||
bool r15_modified = false;
|
||||
|
||||
void step(unsigned clocks);
|
||||
auto step(unsigned clocks) -> void;
|
||||
|
||||
void rombuffer_sync();
|
||||
void rombuffer_update();
|
||||
uint8 rombuffer_read();
|
||||
auto rombuffer_sync() -> void;
|
||||
auto rombuffer_update() -> void;
|
||||
auto rombuffer_read() -> uint8;
|
||||
|
||||
void rambuffer_sync();
|
||||
uint8 rambuffer_read(uint16 addr);
|
||||
void rambuffer_write(uint16 addr, uint8 data);
|
||||
auto rambuffer_sync() -> void;
|
||||
auto rambuffer_read(uint16 addr) -> uint8;
|
||||
auto rambuffer_write(uint16 addr, uint8 data) -> void;
|
||||
|
||||
void r14_modify(uint16);
|
||||
void r15_modify(uint16);
|
||||
auto r14_modify(uint16) -> void;
|
||||
auto r15_modify(uint16) -> void;
|
||||
|
||||
void update_speed();
|
||||
void timing_reset();
|
||||
auto timing_reset() -> void;
|
||||
|
|
|
|||
Loading…
Reference in New Issue