mirror of https://github.com/bsnes-emu/bsnes.git
Update to v087r19 release.
byuu says: Changelog: - added FIFO buffer emulation (with DMA and all that jazz) [Cydrak] - fixed timers and vcounter assign [Cydrak] - emulated EEPROM (you have to change size manually for 14-bit mode, we need a database badly now) [SMA runs now] - removed OAM array, now decoding directly to struct Object {} [128] and ObjectParam {} [32] (faster this way) - check forceblank (still doesn't remove all garble between transitions, though??) - lots of other stuff Delete your settings.cfg, or manually change frequencyGBA to 32768, or bad things will happen (this may change back to 256KHz-4MHz later.) 15 of 16 games are fully playable now, and look and sound great. The major missing detail right now is PPU blending support, and we really need to optimize the hell out of the code.
This commit is contained in:
parent
6189c93f3d
commit
17b5bae86a
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@ -1,7 +1,7 @@
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#ifndef BASE_HPP
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#ifndef BASE_HPP
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#define BASE_HPP
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#define BASE_HPP
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static const char Version[] = "087.18";
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static const char Version[] = "087.19";
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#include <nall/platform.hpp>
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#include <nall/platform.hpp>
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#include <nall/algorithm.hpp>
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#include <nall/algorithm.hpp>
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@ -96,6 +96,7 @@ void APU::Square1::write(unsigned r, uint8 data) {
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if(initialize) {
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if(initialize) {
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enable = dac_enable();
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enable = dac_enable();
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period = 4 * (2048 - frequency);
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envelope_period = envelope_frequency;
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envelope_period = envelope_frequency;
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volume = envelope_volume;
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volume = envelope_volume;
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frequency_shadow = frequency;
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frequency_shadow = frequency;
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@ -106,8 +107,6 @@ void APU::Square1::write(unsigned r, uint8 data) {
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//if(length == 0) length = 64;
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//if(length == 0) length = 64;
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}
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}
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}
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}
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period = 4 * (2048 - frequency);
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}
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}
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void APU::Square1::power() {
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void APU::Square1::power() {
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@ -65,13 +65,12 @@ void APU::Square2::write(unsigned r, uint8 data) {
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if(initialize) {
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if(initialize) {
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enable = dac_enable();
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enable = dac_enable();
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period = 4 * (2048 - frequency);
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envelope_period = envelope_frequency;
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envelope_period = envelope_frequency;
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volume = envelope_volume;
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volume = envelope_volume;
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//if(length == 0) length = 64;
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//if(length == 0) length = 64;
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}
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}
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}
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}
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period = 4 * (2048 - frequency);
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}
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}
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void APU::Square2::power() {
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void APU::Square2::power() {
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@ -52,12 +52,11 @@ void APU::Wave::write(unsigned r, uint8 data) {
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if(initialize) {
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if(initialize) {
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enable = dac_enable;
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enable = dac_enable;
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period = 2 * (2048 - frequency);
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pattern_offset = 0;
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pattern_offset = 0;
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//if(length == 0) length = 256;
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//if(length == 0) length = 256;
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}
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}
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}
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}
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period = 2 * (2048 - frequency);
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}
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}
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void APU::Wave::write_pattern(unsigned p, uint8 data) {
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void APU::Wave::write_pattern(unsigned p, uint8 data) {
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@ -10,15 +10,59 @@ namespace GBA {
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#include "wave.cpp"
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#include "wave.cpp"
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#include "noise.cpp"
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#include "noise.cpp"
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#include "sequencer.cpp"
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#include "sequencer.cpp"
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#include "fifo.cpp"
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APU apu;
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APU apu;
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void APU::Enter() { apu.enter(); }
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void APU::Enter() { apu.main(); }
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void APU::enter() {
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void APU::main() {
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while(true) {
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while(true) {
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runsequencer();
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for(unsigned n = 0; n < 128; n++) {
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interface->audioSample(sequencer.lsample, sequencer.rsample);
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runsequencer();
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step(4);
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}
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signed lsample = regs.bias.level - 0x0200;
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signed rsample = regs.bias.level - 0x0200;
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//(4-bit x 4 -> 6-bit) + 3-bit volume = 9-bit output
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if(sequencer.masterenable) {
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signed lsequence = 0;
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if(sequencer.lenable[0]) lsequence += square1.output;
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if(sequencer.lenable[1]) lsequence += square2.output;
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if(sequencer.lenable[2]) lsequence += wave.output;
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if(sequencer.lenable[3]) lsequence += noise.output;
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signed rsequence = 0;
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if(sequencer.renable[0]) rsequence += square1.output;
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if(sequencer.renable[1]) rsequence += square2.output;
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if(sequencer.renable[2]) rsequence += wave.output;
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if(sequencer.renable[3]) rsequence += noise.output;
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if(sequencer.volume < 3) {
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lsample += lsequence * (sequencer.lvolume + 1) >> (2 - sequencer.volume);
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rsample += rsequence * (sequencer.rvolume + 1) >> (2 - sequencer.volume);
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}
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}
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//(8-bit x 2 -> 7-bit) + 1-bit volume = 10-bit output
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signed fifo0 = fifo[0].output + (1 << fifo[0].volume);
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signed fifo1 = fifo[1].output + (1 << fifo[1].volume);
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if(fifo[0].lenable) lsample += fifo0;
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if(fifo[1].lenable) lsample += fifo1;
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if(fifo[0].renable) rsample += fifo0;
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if(fifo[1].renable) rsample += fifo1;
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lsample = sclamp<10>(lsample);
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rsample = sclamp<10>(rsample);
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if(regs.bias.amplitude == 1) lsample &= ~3, rsample &= ~3;
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if(regs.bias.amplitude == 2) lsample &= ~7, rsample &= ~7;
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if(regs.bias.amplitude == 3) lsample &= ~15, rsample &= ~15;
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interface->audioSample(lsample << 5, rsample << 5);
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step(512);
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}
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}
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}
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}
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wave.power();
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wave.power();
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noise.power();
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noise.power();
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sequencer.power();
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sequencer.power();
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fifo[0].power();
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fifo[1].power();
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regs.bias = 0x0200;
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regs.bias = 0x0200;
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@ -2,7 +2,7 @@ struct APU : Thread, MMIO {
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#include "registers.hpp"
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#include "registers.hpp"
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static void Enter();
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static void Enter();
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void enter();
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void main();
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void step(unsigned clocks);
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void step(unsigned clocks);
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uint8 read(uint32 addr);
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uint8 read(uint32 addr);
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@ -0,0 +1,28 @@
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void APU::FIFO::read() {
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if(size == 0) return;
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size--;
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output = sample[rdoffset++];
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}
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void APU::FIFO::write(int8 byte) {
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if(size == 32) return;
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size++;
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sample[wroffset++] = byte;
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}
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void APU::FIFO::reset() {
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for(auto &byte : sample) byte = 0;
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output = 0;
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rdoffset = 0;
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wroffset = 0;
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size = 0;
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}
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void APU::FIFO::power() {
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reset();
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lenable = 0;
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renable = 0;
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timer = 0;
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}
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case 0x04000081: return sequencer.write(1, byte);
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case 0x04000081: return sequencer.write(1, byte);
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//SOUND_CNT_H
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//SOUND_CNT_H
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case 0x04000082: return;
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case 0x04000082:
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case 0x04000083: return;
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sequencer.volume = byte >> 0;
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fifo[0].volume = byte >> 2;
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fifo[1].volume = byte >> 3;
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return;
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case 0x04000083:
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fifo[0].renable = byte >> 0;
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fifo[0].lenable = byte >> 1;
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fifo[0].timer = byte >> 2;
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if(byte & 1 << 3) fifo[0].reset();
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fifo[1].renable = byte >> 4;
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fifo[1].lenable = byte >> 5;
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fifo[1].timer = byte >> 6;
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if(byte & 1 << 7) fifo[0].reset();
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return;
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//NR52
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//NR52
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case 0x04000084: return sequencer.write(2, byte);
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case 0x04000084: return sequencer.write(2, byte);
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case 0x0400009e: return wave.writeram(14, byte);
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case 0x0400009e: return wave.writeram(14, byte);
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case 0x0400009f: return wave.writeram(15, byte);
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case 0x0400009f: return wave.writeram(15, byte);
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//FIFO_A_L
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//FIFO_A_H
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case 0x040000a0: case 0x040000a1:
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case 0x040000a2: case 0x040000a3:
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return fifo[0].write(byte);
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//FIFO_B_L
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//FIFO_B_H
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case 0x040000a4: case 0x040000a5:
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case 0x040000a6: case 0x040000a7:
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return fifo[1].write(byte);
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}
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}
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}
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}
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} noise;
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} noise;
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struct Sequencer {
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struct Sequencer {
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uint2 volume;
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uint3 lvolume;
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uint3 lvolume;
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uint3 rvolume;
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uint3 rvolume;
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uint1 lenable[4];
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uint1 lenable[4];
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struct FIFO {
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struct FIFO {
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int8 sample[32];
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int8 sample[32];
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int8 output;
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uint5 rdoffset;
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uint5 rdoffset;
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uint5 wroffset;
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uint5 wroffset;
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uint6 size;
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uint6 size;
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inline int8 pull() {
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uint1 volume; //0 = 50%, 1 = 100%
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size--;
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uint1 lenable;
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return sample[rdoffset++];
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uint1 renable;
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}
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uint1 timer;
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inline void push(int8 data) {
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void read();
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size++;
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void write(int8 byte);
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sample[wroffset++] = data;
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void reset();
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}
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void power();
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} fifo[2];
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inline void reset() {
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rdoffset = 0;
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wroffset = 0;
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size = 0;
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for(auto &byte : sample) byte = 0;
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}
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};
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if(r.enable[0]) square1.run();
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if(r.enable[0]) square1.run();
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if(r.enable[1]) square2.run();
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if(r.enable[1]) square2.run();
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if(r.enable[2]) wave.run();
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if(r.enable[2]) wave.run();
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if(r.enable[3]) noise.run();
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if(r.enable[3]) noise.run();
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signed lsample = 0;
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if(r.lenable[0]) lsample += square1.output;
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if(r.lenable[1]) lsample += square2.output;
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if(r.lenable[2]) lsample += wave.output;
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if(r.lenable[3]) lsample += noise.output;
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lsample = (lsample * 512) - 15360;
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lsample = (lsample * (r.lvolume + 1)) / 8;
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r.lsample = lsample;
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signed rsample = 0;
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if(r.renable[0]) rsample += square1.output;
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if(r.renable[1]) rsample += square2.output;
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if(r.renable[2]) rsample += wave.output;
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if(r.renable[3]) rsample += noise.output;
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rsample = (rsample * 512) - 15360;
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rsample = (rsample * (r.rvolume + 1)) / 8;
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r.rsample = rsample;
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if(r.masterenable == false) {
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r.lsample = 0;
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r.rsample = 0;
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}
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}
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}
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uint8 APU::Sequencer::read(unsigned addr) const {
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uint8 APU::Sequencer::read(unsigned addr) const {
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@ -64,6 +64,7 @@ void APU::Square1::write(unsigned addr, uint8 byte) {
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if(initialize) {
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if(initialize) {
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enable = envelope.dacenable();
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enable = envelope.dacenable();
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period = 4 * (2048 - frequency);
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envelope.period = envelope.frequency;
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envelope.period = envelope.frequency;
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volume = envelope.volume;
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volume = envelope.volume;
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shadowfrequency = frequency;
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shadowfrequency = frequency;
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@ -75,8 +76,6 @@ void APU::Square1::write(unsigned addr, uint8 byte) {
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break;
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break;
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}
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}
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period = 4 * (2048 - frequency);
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}
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}
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void APU::Square1::power() {
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void APU::Square1::power() {
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@ -32,14 +32,13 @@ void APU::Square2::write(unsigned addr, uint8 byte) {
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if(initialize) {
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if(initialize) {
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enable = envelope.dacenable();
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enable = envelope.dacenable();
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period = 4 * (2048 - frequency);
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envelope.period = envelope.frequency;
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envelope.period = envelope.frequency;
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volume = envelope.volume;
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volume = envelope.volume;
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}
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}
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break;
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break;
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}
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}
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period = 4 * (2048 - frequency);
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}
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}
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|
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void APU::Square2::power() {
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void APU::Square2::power() {
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|
|
|
@ -55,14 +55,13 @@ void APU::Wave::write(unsigned addr, uint8 byte) {
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|
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if(initialize) {
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if(initialize) {
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enable = dacenable;
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enable = dacenable;
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period = 2 * (2048 - frequency);
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patternaddr = 0;
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patternaddr = 0;
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patternbank = mode ? (uint1)0 : bank;
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patternbank = mode ? (uint1)0 : bank;
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}
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}
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|
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break;
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break;
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}
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}
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period = 2 * (2048 - frequency);
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|
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}
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}
|
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|
|
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uint8 APU::Wave::readram(unsigned addr) const {
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uint8 APU::Wave::readram(unsigned addr) const {
|
||||||
|
|
|
@ -2,19 +2,20 @@
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||||||
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|
||||||
namespace GBA {
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namespace GBA {
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|
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#include "eeprom.cpp"
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Cartridge cartridge;
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Cartridge cartridge;
|
||||||
|
|
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bool Cartridge::load(const string &markup, const uint8_t *data, unsigned size) {
|
bool Cartridge::load(const string &markup, const uint8_t *data, unsigned size) {
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if(cartridge.rom.data) delete[] cartridge.rom.data;
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if(rom.data) delete[] rom.data;
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cartridge.rom.data = new uint8[cartridge.rom.size = 32 * 1024 * 1024];
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rom.data = new uint8[rom.size = 32 * 1024 * 1024];
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for(unsigned addr = 0; addr < 32 * 1024 * 1024; addr++) {
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for(unsigned addr = 0; addr < 32 * 1024 * 1024; addr++) {
|
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cartridge.rom.data[addr] = data[Bus::mirror(addr, size)];
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rom.data[addr] = data[Bus::mirror(addr, size)];
|
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}
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}
|
||||||
|
|
||||||
if(cartridge.ram.data) delete[] cartridge.ram.data;
|
if(ram.data) delete[] ram.data;
|
||||||
cartridge.ram.data = new uint8[cartridge.ram.size = 64 * 1024]();
|
ram.data = new uint8[ram.size = 64 * 1024]();
|
||||||
|
|
||||||
sha256 = nall::sha256(cartridge.rom.data, cartridge.rom.size);
|
sha256 = nall::sha256(rom.data, rom.size);
|
||||||
|
|
||||||
return loaded = true;
|
return loaded = true;
|
||||||
}
|
}
|
||||||
|
@ -23,9 +24,30 @@ void Cartridge::unload() {
|
||||||
if(loaded) return;
|
if(loaded) return;
|
||||||
loaded = false;
|
loaded = false;
|
||||||
|
|
||||||
delete[] cartridge.rom.data;
|
delete[] rom.data;
|
||||||
cartridge.rom.data = nullptr;
|
rom.data = nullptr;
|
||||||
cartridge.rom.size = 0u;
|
rom.size = 0u;
|
||||||
|
}
|
||||||
|
|
||||||
|
void Cartridge::power() {
|
||||||
|
eeprom.power();
|
||||||
|
|
||||||
|
has_eeprom = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32 Cartridge::read(uint32 addr, uint32 size) {
|
||||||
|
if(has_eeprom && (addr & 0x0f000000) == 0x0d000000) return eeprom.read();
|
||||||
|
|
||||||
|
if((addr & 0x0e000000) == 0x08000000) return rom.read(addr & 0x01ffffff, size);
|
||||||
|
if((addr & 0x0e000000) == 0x0a000000) return rom.read(addr & 0x01ffffff, size);
|
||||||
|
if((addr & 0x0e000000) == 0x0c000000) return rom.read(addr & 0x01ffffff, size);
|
||||||
|
if((addr & 0x0e000000) == 0x0e000000) return ram.read(addr & 0x0000ffff, size);
|
||||||
|
}
|
||||||
|
|
||||||
|
void Cartridge::write(uint32 addr, uint32 size, uint32 word) {
|
||||||
|
if((addr & 0x0f000000) == 0x0d000000) { has_eeprom = true; return eeprom.write(word & 1); }
|
||||||
|
|
||||||
|
if((addr & 0x0e000000) == 0x0e000000) return ram.write(addr & 0x0000ffff, size, word);
|
||||||
}
|
}
|
||||||
|
|
||||||
Cartridge::Cartridge() {
|
Cartridge::Cartridge() {
|
||||||
|
|
|
@ -1,12 +1,18 @@
|
||||||
struct Cartridge : property<Cartridge> {
|
struct Cartridge : property<Cartridge> {
|
||||||
StaticMemory rom;
|
StaticMemory rom;
|
||||||
StaticMemory ram;
|
StaticMemory ram;
|
||||||
|
#include "memory.hpp"
|
||||||
|
|
||||||
readonly<bool> loaded;
|
readonly<bool> loaded;
|
||||||
readonly<string> sha256;
|
readonly<string> sha256;
|
||||||
|
readonly<bool> has_eeprom;
|
||||||
|
|
||||||
bool load(const string &markup, const uint8_t *data, unsigned size);
|
bool load(const string &markup, const uint8_t *data, unsigned size);
|
||||||
void unload();
|
void unload();
|
||||||
|
void power();
|
||||||
|
|
||||||
|
uint32 read(uint32 addr, uint32 size);
|
||||||
|
void write(uint32 addr, uint32 size, uint32 word);
|
||||||
|
|
||||||
Cartridge();
|
Cartridge();
|
||||||
};
|
};
|
||||||
|
|
|
@ -0,0 +1,65 @@
|
||||||
|
bool Cartridge::EEPROM::read() {
|
||||||
|
bool bit = 1;
|
||||||
|
|
||||||
|
if(mode == Mode::ReadData) {
|
||||||
|
if(offset >= 4) bit = data[address * 64 + (offset - 4)];
|
||||||
|
if(++offset == 68) mode = Mode::Wait;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bit;
|
||||||
|
}
|
||||||
|
|
||||||
|
void Cartridge::EEPROM::write(bool bit) {
|
||||||
|
if(mode == Mode::Wait) {
|
||||||
|
if(bit == 1) mode = Mode::Command;
|
||||||
|
}
|
||||||
|
|
||||||
|
else if(mode == Mode::Command) {
|
||||||
|
if(bit == 0) mode = Mode::WriteAddress;
|
||||||
|
if(bit == 1) mode = Mode::ReadAddress;
|
||||||
|
offset = 0;
|
||||||
|
address = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
else if(mode == Mode::ReadAddress) {
|
||||||
|
address = (address << 1) | bit;
|
||||||
|
if(++offset == size) {
|
||||||
|
mode = Mode::ReadValidate;
|
||||||
|
offset = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
else if(mode == Mode::ReadValidate) {
|
||||||
|
if(bit == 1); //invalid
|
||||||
|
mode = Mode::ReadData;
|
||||||
|
}
|
||||||
|
|
||||||
|
else if(mode == Mode::WriteAddress) {
|
||||||
|
address = (address << 1) | bit;
|
||||||
|
if(++offset == size) {
|
||||||
|
mode = Mode::WriteData;
|
||||||
|
offset = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
else if(mode == Mode::WriteData) {
|
||||||
|
data[address * 64 + offset] = bit;
|
||||||
|
if(++offset == 64) {
|
||||||
|
mode = Mode::WriteValidate;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
else if(mode == Mode::WriteValidate) {
|
||||||
|
if(bit == 1); //invalid
|
||||||
|
mode = Mode::Wait;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void Cartridge::EEPROM::power() {
|
||||||
|
for(auto &bit : data) bit = 0;
|
||||||
|
size = 6;
|
||||||
|
|
||||||
|
mode = Mode::Wait;
|
||||||
|
offset = 0;
|
||||||
|
address = 0;
|
||||||
|
}
|
|
@ -0,0 +1,12 @@
|
||||||
|
struct EEPROM {
|
||||||
|
bool data[64 * 1024];
|
||||||
|
unsigned size;
|
||||||
|
|
||||||
|
enum class Mode : unsigned { Wait, Command, ReadAddress, ReadValidate, ReadData, WriteAddress, WriteData, WriteValidate } mode;
|
||||||
|
unsigned offset;
|
||||||
|
unsigned address;
|
||||||
|
|
||||||
|
bool read();
|
||||||
|
void write(bool bit);
|
||||||
|
void power();
|
||||||
|
} eeprom;
|
|
@ -21,6 +21,7 @@ void CPU::enter() {
|
||||||
}
|
}
|
||||||
|
|
||||||
processor.irqline = regs.ime && (regs.irq.enable & regs.irq.flag);
|
processor.irqline = regs.ime && (regs.irq.enable & regs.irq.flag);
|
||||||
|
dma_run();
|
||||||
|
|
||||||
if(regs.mode == Registers::Mode::Halt) {
|
if(regs.mode == Registers::Mode::Halt) {
|
||||||
if((regs.irq.enable & regs.irq.flag) == 0) {
|
if((regs.irq.enable & regs.irq.flag) == 0) {
|
||||||
|
@ -30,7 +31,6 @@ void CPU::enter() {
|
||||||
regs.mode = Registers::Mode::Normal;
|
regs.mode = Registers::Mode::Normal;
|
||||||
}
|
}
|
||||||
|
|
||||||
dma_run();
|
|
||||||
exec();
|
exec();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -7,6 +7,7 @@ struct CPU : Processor::ARM, Thread, MMIO {
|
||||||
static void Enter();
|
static void Enter();
|
||||||
void enter();
|
void enter();
|
||||||
void step(unsigned clocks);
|
void step(unsigned clocks);
|
||||||
|
|
||||||
uint32 bus_read(uint32 addr, uint32 size);
|
uint32 bus_read(uint32 addr, uint32 size);
|
||||||
void bus_write(uint32 addr, uint32 size, uint32 word);
|
void bus_write(uint32 addr, uint32 size, uint32 word);
|
||||||
|
|
||||||
|
|
|
@ -19,7 +19,19 @@ void CPU::dma_run() {
|
||||||
case 0: break;
|
case 0: break;
|
||||||
case 1: if(pending.dma.vblank == false) continue; break;
|
case 1: if(pending.dma.vblank == false) continue; break;
|
||||||
case 2: if(pending.dma.hblank == false) continue; break;
|
case 2: if(pending.dma.hblank == false) continue; break;
|
||||||
case 3: if(pending.dma.hdma == false || n != 3) continue; break;
|
case 3:
|
||||||
|
if(n == 0) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if(n == 1 || n == 2) {
|
||||||
|
if(apu.fifo[n - 1].size > 16) continue;
|
||||||
|
dma.control.targetmode = 2;
|
||||||
|
dma.control.size = 1;
|
||||||
|
dma.run.length = 4;
|
||||||
|
}
|
||||||
|
if(n == 3) {
|
||||||
|
if(pending.dma.hdma == false) continue;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
dma_transfer(dma);
|
dma_transfer(dma);
|
||||||
|
|
|
@ -4,52 +4,40 @@ uint8 CPU::read(uint32 addr) {
|
||||||
switch(addr) {
|
switch(addr) {
|
||||||
|
|
||||||
//DMA0CNT_H
|
//DMA0CNT_H
|
||||||
case 0x040000ba: return regs.dma[0].control >> 0;
|
|
||||||
case 0x040000bb: return regs.dma[0].control >> 8;
|
|
||||||
|
|
||||||
//DMA1CNT_H
|
//DMA1CNT_H
|
||||||
case 0x040000c6: return regs.dma[1].control >> 0;
|
|
||||||
case 0x040000c7: return regs.dma[1].control >> 8;
|
|
||||||
|
|
||||||
//DMA2CNT_H
|
//DMA2CNT_H
|
||||||
case 0x040000d2: return regs.dma[2].control >> 0;
|
|
||||||
case 0x040000d3: return regs.dma[2].control >> 8;
|
|
||||||
|
|
||||||
//DMA3CNT_H
|
//DMA3CNT_H
|
||||||
case 0x040000de: return regs.dma[3].control >> 0;
|
case 0x040000ba: case 0x040000bb:
|
||||||
case 0x040000df: return regs.dma[3].control >> 8;
|
case 0x040000c6: case 0x040000c7:
|
||||||
|
case 0x040000d2: case 0x040000d3:
|
||||||
|
case 0x040000de: case 0x040000df: {
|
||||||
|
auto &dma = regs.dma[(addr - 0x040000ba) / 12];
|
||||||
|
unsigned shift = (addr & 1) * 8;
|
||||||
|
return dma.control >> shift;
|
||||||
|
}
|
||||||
|
|
||||||
//TM0CNT_L
|
//TM0CNT_L
|
||||||
case 0x04000100: return regs.timer[0].counter >> 0;
|
//TM1CNT_L
|
||||||
case 0x04000101: return regs.timer[0].counter >> 8;
|
//TM2CNT_L
|
||||||
|
//TM3CNT_L
|
||||||
|
case 0x04000100: case 0x04000101:
|
||||||
|
case 0x04000104: case 0x04000105:
|
||||||
|
case 0x04000108: case 0x04000109:
|
||||||
|
case 0x0400010c: case 0x0400010d: {
|
||||||
|
auto &timer = regs.timer[(addr >> 2) & 3];
|
||||||
|
unsigned shift = (addr & 1) * 8;
|
||||||
|
return timer.counter >> shift;
|
||||||
|
}
|
||||||
|
|
||||||
//TIM0CNT_H
|
//TIM0CNT_H
|
||||||
case 0x04000102: return regs.timer[0].control >> 0;
|
case 0x04000102: case 0x04000103:
|
||||||
case 0x04000103: return regs.timer[0].control >> 8;
|
case 0x04000106: case 0x04000107:
|
||||||
|
case 0x0400010a: case 0x0400010b:
|
||||||
//TM1CNT_L
|
case 0x0400010e: case 0x0400010f: {
|
||||||
case 0x04000104: return regs.timer[1].reload >> 0;
|
auto &timer = regs.timer[(addr >> 2) & 3];
|
||||||
case 0x04000105: return regs.timer[1].reload >> 8;
|
unsigned shift = (addr & 1) * 8;
|
||||||
|
return timer.control >> shift;
|
||||||
//TM1CNT_H
|
}
|
||||||
case 0x04000106: return regs.timer[1].control >> 0;
|
|
||||||
case 0x04000107: return regs.timer[1].control >> 8;
|
|
||||||
|
|
||||||
//TM2CNT_L
|
|
||||||
case 0x04000108: return regs.timer[2].reload >> 0;
|
|
||||||
case 0x04000109: return regs.timer[2].reload >> 8;
|
|
||||||
|
|
||||||
//TM2CNT_H
|
|
||||||
case 0x0400010a: return regs.timer[2].control >> 0;
|
|
||||||
case 0x0400010b: return regs.timer[2].control >> 8;
|
|
||||||
|
|
||||||
//TM3CNT_L
|
|
||||||
case 0x0400010c: return regs.timer[3].reload >> 0;
|
|
||||||
case 0x0400010d: return regs.timer[3].reload >> 8;
|
|
||||||
|
|
||||||
//TM3CNT_H
|
|
||||||
case 0x0400010e: return regs.timer[3].control >> 0;
|
|
||||||
case 0x0400010f: return regs.timer[3].control >> 8;
|
|
||||||
|
|
||||||
//KEYINPUT
|
//KEYINPUT
|
||||||
case 0x04000130:
|
case 0x04000130:
|
||||||
|
@ -208,10 +196,10 @@ void CPU::write(uint32 addr, uint8 byte) {
|
||||||
case 0x0400010e: {
|
case 0x0400010e: {
|
||||||
auto &timer = regs.timer[(addr >> 2) & 3];
|
auto &timer = regs.timer[(addr >> 2) & 3];
|
||||||
bool enable = timer.control.enable;
|
bool enable = timer.control.enable;
|
||||||
if(timer.control.enable == 0 && enable == 1) {
|
timer.control = byte;
|
||||||
|
if(enable == 0 && timer.control.enable == 1) {
|
||||||
timer.counter = timer.reload;
|
timer.counter = timer.reload;
|
||||||
}
|
}
|
||||||
timer.control = byte;
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -25,7 +25,7 @@ struct Registers {
|
||||||
struct Run {
|
struct Run {
|
||||||
uint32 target;
|
uint32 target;
|
||||||
uint32 source;
|
uint32 source;
|
||||||
uint32 length;
|
uint16 length;
|
||||||
} run;
|
} run;
|
||||||
uint32 basetarget;
|
uint32 basetarget;
|
||||||
} dma[4];
|
} dma[4];
|
||||||
|
|
|
@ -17,7 +17,11 @@ void CPU::timer_increment(unsigned n) {
|
||||||
if(++regs.timer[n].counter == 0) {
|
if(++regs.timer[n].counter == 0) {
|
||||||
if(regs.timer[n].control.irq) regs.irq.flag.timer[n] = 1;
|
if(regs.timer[n].control.irq) regs.irq.flag.timer[n] = 1;
|
||||||
|
|
||||||
|
if(apu.fifo[0].timer == n) apu.fifo[0].read();
|
||||||
|
if(apu.fifo[1].timer == n) apu.fifo[1].read();
|
||||||
|
|
||||||
regs.timer[n].counter = regs.timer[n].reload;
|
regs.timer[n].counter = regs.timer[n].reload;
|
||||||
|
|
||||||
if(n < 3 && regs.timer[n + 1].control.cascade) {
|
if(n < 3 && regs.timer[n + 1].control.cascade) {
|
||||||
timer_increment(n + 1);
|
timer_increment(n + 1);
|
||||||
}
|
}
|
||||||
|
|
|
@ -74,7 +74,9 @@ uint32 Bus::mirror(uint32 addr, uint32 size) {
|
||||||
}
|
}
|
||||||
|
|
||||||
uint32 Bus::read(uint32 addr, uint32 size) {
|
uint32 Bus::read(uint32 addr, uint32 size) {
|
||||||
switch(addr & 0x0f000000) {
|
if(addr & 0x08000000) return cartridge.read(addr, size);
|
||||||
|
|
||||||
|
switch(addr & 0x07000000) {
|
||||||
case 0x00000000: return system.bios.read(addr & 0x3fff, size);
|
case 0x00000000: return system.bios.read(addr & 0x3fff, size);
|
||||||
case 0x01000000: return system.bios.read(addr & 0x3fff, size);
|
case 0x01000000: return system.bios.read(addr & 0x3fff, size);
|
||||||
case 0x02000000: return cpu.ewram.read(addr & 0x3ffff, size);
|
case 0x02000000: return cpu.ewram.read(addr & 0x3ffff, size);
|
||||||
|
@ -85,20 +87,14 @@ uint32 Bus::read(uint32 addr, uint32 size) {
|
||||||
return 0u;
|
return 0u;
|
||||||
case 0x05000000: return ppu.pram.read(addr & 0x3ff, size);
|
case 0x05000000: return ppu.pram.read(addr & 0x3ff, size);
|
||||||
case 0x06000000: return ppu.vram.read(addr & 0x10000 ? (0x10000 + (addr & 0x7fff)) : (addr & 0xffff), size);
|
case 0x06000000: return ppu.vram.read(addr & 0x10000 ? (0x10000 + (addr & 0x7fff)) : (addr & 0xffff), size);
|
||||||
case 0x07000000: return ppu.oam.read(addr & 0x3ff, size);
|
case 0x07000000: return ppu.oam_read(addr & 0x3ff, size);
|
||||||
case 0x08000000: return cartridge.rom.read(addr & 0x1ffffff, size);
|
|
||||||
case 0x09000000: return cartridge.rom.read(addr & 0x1ffffff, size);
|
|
||||||
case 0x0a000000: return cartridge.rom.read(addr & 0x1ffffff, size);
|
|
||||||
case 0x0b000000: return cartridge.rom.read(addr & 0x1ffffff, size);
|
|
||||||
case 0x0c000000: return cartridge.rom.read(addr & 0x1ffffff, size);
|
|
||||||
case 0x0d000000: return cartridge.rom.read(addr & 0x1ffffff, size);
|
|
||||||
case 0x0e000000: return cartridge.ram.read(addr & 0xffff, size);
|
|
||||||
case 0x0f000000: return cartridge.ram.read(addr & 0xffff, size);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void Bus::write(uint32 addr, uint32 size, uint32 word) {
|
void Bus::write(uint32 addr, uint32 size, uint32 word) {
|
||||||
switch(addr & 0x0f000000) {
|
if(addr & 0x08000000) return cartridge.write(addr, size, word);
|
||||||
|
|
||||||
|
switch(addr & 0x07000000) {
|
||||||
case 0x00000000: return;
|
case 0x00000000: return;
|
||||||
case 0x01000000: return;
|
case 0x01000000: return;
|
||||||
case 0x02000000: return cpu.ewram.write(addr & 0x3ffff, size, word);
|
case 0x02000000: return cpu.ewram.write(addr & 0x3ffff, size, word);
|
||||||
|
@ -109,15 +105,7 @@ void Bus::write(uint32 addr, uint32 size, uint32 word) {
|
||||||
return;
|
return;
|
||||||
case 0x05000000: return ppu.pram.write(addr & 0x3ff, size, word);
|
case 0x05000000: return ppu.pram.write(addr & 0x3ff, size, word);
|
||||||
case 0x06000000: return ppu.vram.write(addr & 0x10000 ? (0x10000 + (addr & 0x7fff)) : (addr & 0xffff), size, word);
|
case 0x06000000: return ppu.vram.write(addr & 0x10000 ? (0x10000 + (addr & 0x7fff)) : (addr & 0xffff), size, word);
|
||||||
case 0x07000000: return ppu.oam.write(addr & 0x3ff, size, word);
|
case 0x07000000: return ppu.oam_write(addr & 0x3ff, size, word);
|
||||||
case 0x08000000: return;
|
|
||||||
case 0x09000000: return;
|
|
||||||
case 0x0a000000: return;
|
|
||||||
case 0x0b000000: return;
|
|
||||||
case 0x0c000000: return;
|
|
||||||
case 0x0d000000: return;
|
|
||||||
case 0x0e000000: return cartridge.ram.write(addr & 0xffff, size, word);
|
|
||||||
case 0x0f000000: return cartridge.ram.write(addr & 0xffff, size, word);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -66,7 +66,7 @@ void PPU::write(uint32 addr, uint8 byte) {
|
||||||
regs.status.irqvcoincidence = byte & (1 << 5);
|
regs.status.irqvcoincidence = byte & (1 << 5);
|
||||||
return;
|
return;
|
||||||
case 0x04000005:
|
case 0x04000005:
|
||||||
regs.status.vcoincidence = byte;
|
regs.status.vcompare = byte;
|
||||||
return;
|
return;
|
||||||
|
|
||||||
//BG0CNT
|
//BG0CNT
|
||||||
|
|
|
@ -3,47 +3,8 @@ void PPU::render_objects() {
|
||||||
|
|
||||||
for(signed n = 127; n >= 0; n--) {
|
for(signed n = 127; n >= 0; n--) {
|
||||||
auto &obj = object[n];
|
auto &obj = object[n];
|
||||||
uint16 attr0 = oam.read(n * 8 + 0, Half);
|
|
||||||
uint16 attr1 = oam.read(n * 8 + 2, Half);
|
|
||||||
uint16 attr2 = oam.read(n * 8 + 4, Half);
|
|
||||||
|
|
||||||
obj.y = attr0 >> 0;
|
|
||||||
obj.affine = attr0 >> 8;
|
|
||||||
obj.affinesize = attr0 >> 9;
|
|
||||||
obj.mode = attr0 >> 10;
|
|
||||||
obj.mosaic = attr0 >> 12;
|
|
||||||
obj.colors = attr0 >> 13;
|
|
||||||
obj.shape = attr0 >> 14;
|
|
||||||
|
|
||||||
obj.x = attr1 >> 0;
|
|
||||||
obj.affineparam = attr1 >> 9;
|
|
||||||
obj.hflip = attr1 >> 12;
|
|
||||||
obj.vflip = attr1 >> 13;
|
|
||||||
obj.size = attr1 >> 14;
|
|
||||||
|
|
||||||
obj.character = attr2 >> 0;
|
|
||||||
obj.priority = attr2 >> 10;
|
|
||||||
obj.palette = attr2 >> 12;
|
|
||||||
|
|
||||||
static unsigned widths[] = {
|
|
||||||
8, 16, 32, 64,
|
|
||||||
16, 32, 32, 64,
|
|
||||||
8, 8, 16, 32,
|
|
||||||
0, 0, 0, 0, //8?
|
|
||||||
};
|
|
||||||
|
|
||||||
static unsigned heights[] = {
|
|
||||||
8, 16, 32, 64,
|
|
||||||
8, 8, 16, 32,
|
|
||||||
16, 32, 32, 64,
|
|
||||||
0, 0, 0, 0, //8?
|
|
||||||
};
|
|
||||||
|
|
||||||
obj.width = widths [obj.shape * 4 + obj.size];
|
|
||||||
obj.height = heights[obj.shape * 4 + obj.size];
|
|
||||||
|
|
||||||
uint8 py = regs.vcounter - obj.y;
|
uint8 py = regs.vcounter - obj.y;
|
||||||
if(py >= obj.height << obj.affinesize) continue;
|
if(py >= obj.height << obj.affinesize) continue; //offscreen
|
||||||
if(obj.affine == 0 && obj.affinesize == 1) continue; //hidden
|
if(obj.affine == 0 && obj.affinesize == 1) continue; //hidden
|
||||||
|
|
||||||
if(obj.affine == 0) render_object_linear(obj);
|
if(obj.affine == 0) render_object_linear(obj);
|
||||||
|
@ -85,10 +46,10 @@ void PPU::render_object_affine(Object &obj) {
|
||||||
unsigned baseaddr = 0x10000 + obj.character * 32;
|
unsigned baseaddr = 0x10000 + obj.character * 32;
|
||||||
uint9 sx = obj.x;
|
uint9 sx = obj.x;
|
||||||
|
|
||||||
int16 pa = oam.read(obj.affineparam * 32 + 0x06, Half);
|
int16 pa = objectparam[obj.affineparam].pa;
|
||||||
int16 pb = oam.read(obj.affineparam * 32 + 0x0e, Half);
|
int16 pb = objectparam[obj.affineparam].pb;
|
||||||
int16 pc = oam.read(obj.affineparam * 32 + 0x16, Half);
|
int16 pc = objectparam[obj.affineparam].pc;
|
||||||
int16 pd = oam.read(obj.affineparam * 32 + 0x1e, Half);
|
int16 pd = objectparam[obj.affineparam].pd;
|
||||||
|
|
||||||
//center-of-sprite coordinates
|
//center-of-sprite coordinates
|
||||||
int16 centerx = obj.width / 2;
|
int16 centerx = obj.width / 2;
|
||||||
|
@ -123,3 +84,142 @@ void PPU::render_object_affine(Object &obj) {
|
||||||
fy += pc;
|
fy += pc;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
uint32 PPU::oam_read(uint32 addr, uint32 size) {
|
||||||
|
uint32 word = 0;
|
||||||
|
|
||||||
|
switch(size) {
|
||||||
|
case Word:
|
||||||
|
addr &= ~3;
|
||||||
|
word |= oam_read(addr + 0) << 0;
|
||||||
|
word |= oam_read(addr + 1) << 8;
|
||||||
|
word |= oam_read(addr + 2) << 16;
|
||||||
|
word |= oam_read(addr + 3) << 24;
|
||||||
|
break;
|
||||||
|
case Half:
|
||||||
|
word |= oam_read(addr + 0) << 0;
|
||||||
|
word |= oam_read(addr + 1) << 8;
|
||||||
|
break;
|
||||||
|
case Byte:
|
||||||
|
word |= oam_read(addr + 0) << 0;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return word;
|
||||||
|
}
|
||||||
|
|
||||||
|
//16-bit bus (8-bit writes are ignored)
|
||||||
|
void PPU::oam_write(uint32 addr, uint32 size, uint32 word) {
|
||||||
|
switch(size) {
|
||||||
|
case Word:
|
||||||
|
addr &= ~3;
|
||||||
|
oam_write(addr + 0, word >> 0);
|
||||||
|
oam_write(addr + 1, word >> 8);
|
||||||
|
oam_write(addr + 2, word >> 16);
|
||||||
|
oam_write(addr + 3, word >> 24);
|
||||||
|
break;
|
||||||
|
case Half:
|
||||||
|
addr &= ~1;
|
||||||
|
oam_write(addr + 0, word >> 0);
|
||||||
|
oam_write(addr + 1, word >> 8);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
uint8 PPU::oam_read(uint32 addr) {
|
||||||
|
auto &obj = object[(addr >> 3) & 127];
|
||||||
|
auto &par = objectparam[(addr >> 5) & 31];
|
||||||
|
|
||||||
|
switch(addr & 7) {
|
||||||
|
case 0: return (obj.y);
|
||||||
|
case 1: return (obj.affine << 0) + (obj.affinesize << 1) + (obj.mode << 2) + (obj.mosaic << 4) + (obj.colors << 5) + (obj.shape << 6);
|
||||||
|
case 2: return (obj.x >> 0);
|
||||||
|
case 3: return (obj.x >> 8) + (obj.affineparam << 1) + (obj.hflip << 4) + (obj.vflip << 5) + (obj.size << 6);
|
||||||
|
case 4: return (obj.character >> 0);
|
||||||
|
case 5: return (obj.character >> 8) + (obj.priority << 2) + (obj.palette << 4);
|
||||||
|
case 6:
|
||||||
|
switch((addr >> 3) & 3) {
|
||||||
|
case 0: return par.pa >> 0;
|
||||||
|
case 1: return par.pb >> 0;
|
||||||
|
case 2: return par.pc >> 0;
|
||||||
|
case 3: return par.pd >> 0;
|
||||||
|
}
|
||||||
|
case 7:
|
||||||
|
switch((addr >> 3) & 3) {
|
||||||
|
case 0: return par.pa >> 8;
|
||||||
|
case 1: return par.pb >> 8;
|
||||||
|
case 2: return par.pc >> 8;
|
||||||
|
case 3: return par.pd >> 8;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void PPU::oam_write(uint32 addr, uint8 byte) {
|
||||||
|
auto &obj = object[(addr >> 3) & 127];
|
||||||
|
auto &par = objectparam[(addr >> 5) & 31];
|
||||||
|
|
||||||
|
switch(addr & 7) {
|
||||||
|
case 0:
|
||||||
|
obj.y = byte;
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
obj.affine = byte >> 0;
|
||||||
|
obj.affinesize = byte >> 1;
|
||||||
|
obj.mode = byte >> 2;
|
||||||
|
obj.mosaic = byte >> 4;
|
||||||
|
obj.colors = byte >> 5;
|
||||||
|
obj.shape = byte >> 6;
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
obj.x = (obj.x & 0xff00) | (byte << 0);
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
obj.x = (obj.x & 0x00ff) | (byte << 8);
|
||||||
|
obj.affineparam = byte >> 1;
|
||||||
|
obj.hflip = byte >> 4;
|
||||||
|
obj.vflip = byte >> 5;
|
||||||
|
obj.size = byte >> 6;
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
obj.character = (obj.character & 0xff00) | (byte << 0);
|
||||||
|
break;
|
||||||
|
case 5:
|
||||||
|
obj.character = (obj.character & 0x00ff) | (byte << 8);
|
||||||
|
obj.priority = byte >> 2;
|
||||||
|
obj.palette = byte >> 4;
|
||||||
|
break;
|
||||||
|
case 6:
|
||||||
|
switch((addr >> 3) & 3) {
|
||||||
|
case 0: par.pa = (par.pa & 0xff00) | (byte << 0); break;
|
||||||
|
case 1: par.pb = (par.pb & 0xff00) | (byte << 0); break;
|
||||||
|
case 2: par.pc = (par.pc & 0xff00) | (byte << 0); break;
|
||||||
|
case 3: par.pd = (par.pd & 0xff00) | (byte << 0); break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 7:
|
||||||
|
switch((addr >> 3) & 3) {
|
||||||
|
case 0: par.pa = (par.pa & 0x00ff) | (byte << 8); break;
|
||||||
|
case 1: par.pb = (par.pb & 0x00ff) | (byte << 8); break;
|
||||||
|
case 2: par.pc = (par.pc & 0x00ff) | (byte << 8); break;
|
||||||
|
case 3: par.pd = (par.pd & 0x00ff) | (byte << 8); break;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned widths[] = {
|
||||||
|
8, 16, 32, 64,
|
||||||
|
16, 32, 32, 64,
|
||||||
|
8, 8, 16, 32,
|
||||||
|
0, 0, 0, 0, //8?
|
||||||
|
};
|
||||||
|
|
||||||
|
static unsigned heights[] = {
|
||||||
|
8, 16, 32, 64,
|
||||||
|
8, 8, 16, 32,
|
||||||
|
16, 32, 32, 64,
|
||||||
|
0, 0, 0, 0, //8?
|
||||||
|
};
|
||||||
|
|
||||||
|
obj.width = widths [obj.shape * 4 + obj.size];
|
||||||
|
obj.height = heights[obj.shape * 4 + obj.size];
|
||||||
|
}
|
||||||
|
|
|
@ -36,10 +36,11 @@ void PPU::power() {
|
||||||
create(PPU::Enter, 16777216);
|
create(PPU::Enter, 16777216);
|
||||||
|
|
||||||
for(unsigned n = 0; n < vram.size; n++) vram.data[n] = 0;
|
for(unsigned n = 0; n < vram.size; n++) vram.data[n] = 0;
|
||||||
for(unsigned n = 0; n < oam.size; n++) oam.data[n] = 0;
|
|
||||||
for(unsigned n = 0; n < pram.size; n++) pram.data[n] = 0;
|
for(unsigned n = 0; n < pram.size; n++) pram.data[n] = 0;
|
||||||
for(unsigned n = 0; n < 240 * 160; n++) output[n] = 0;
|
for(unsigned n = 0; n < 240 * 160; n++) output[n] = 0;
|
||||||
|
|
||||||
|
for(unsigned n = 0; n < 1024; n++) oam_write(n, 0);
|
||||||
|
|
||||||
regs.control = 0;
|
regs.control = 0;
|
||||||
regs.greenswap = 0;
|
regs.greenswap = 0;
|
||||||
regs.status = 0;
|
regs.status = 0;
|
||||||
|
@ -109,15 +110,19 @@ void PPU::scanline() {
|
||||||
layer[3][x].exists = false;
|
layer[3][x].exists = false;
|
||||||
}
|
}
|
||||||
|
|
||||||
render_backgrounds();
|
if(regs.control.forceblank) {
|
||||||
render_objects();
|
render_forceblank();
|
||||||
render_screen();
|
} else {
|
||||||
|
render_backgrounds();
|
||||||
|
render_objects();
|
||||||
|
render_screen();
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
step(960);
|
step(960);
|
||||||
regs.status.hblank = 1;
|
regs.status.hblank = 1;
|
||||||
if(regs.status.irqhblank) cpu.regs.irq.flag.hblank = 1;
|
if(regs.status.irqhblank) cpu.regs.irq.flag.hblank = 1;
|
||||||
cpu.pending.dma.hblank = true;
|
if(regs.vcounter < 160) cpu.pending.dma.hblank = true;
|
||||||
|
|
||||||
step(240);
|
step(240);
|
||||||
regs.status.hblank = 0;
|
regs.status.hblank = 0;
|
||||||
|
@ -134,7 +139,6 @@ void PPU::frame() {
|
||||||
|
|
||||||
PPU::PPU() {
|
PPU::PPU() {
|
||||||
vram.data = new uint8[vram.size = 96 * 1024];
|
vram.data = new uint8[vram.size = 96 * 1024];
|
||||||
oam.data = new uint8[oam.size = 1024];
|
|
||||||
pram.data = new uint8[pram.size = 1024];
|
pram.data = new uint8[pram.size = 1024];
|
||||||
output = new uint16[240 * 160];
|
output = new uint16[240 * 160];
|
||||||
}
|
}
|
||||||
|
|
|
@ -1,6 +1,5 @@
|
||||||
struct PPU : Thread, MMIO {
|
struct PPU : Thread, MMIO {
|
||||||
StaticMemory vram;
|
StaticMemory vram;
|
||||||
StaticMemory oam;
|
|
||||||
StaticMemory pram;
|
StaticMemory pram;
|
||||||
#include "registers.hpp"
|
#include "registers.hpp"
|
||||||
#include "state.hpp"
|
#include "state.hpp"
|
||||||
|
@ -25,8 +24,13 @@ struct PPU : Thread, MMIO {
|
||||||
void render_objects();
|
void render_objects();
|
||||||
void render_object_linear(Object&);
|
void render_object_linear(Object&);
|
||||||
void render_object_affine(Object&);
|
void render_object_affine(Object&);
|
||||||
|
uint32 oam_read(uint32 addr, uint32 size);
|
||||||
|
void oam_write(uint32 addr, uint32 size, uint32 word);
|
||||||
|
uint8 oam_read(uint32 addr);
|
||||||
|
void oam_write(uint32 addr, uint8 byte);
|
||||||
|
|
||||||
uint15 palette(uint9 index);
|
uint15 palette(uint9 index);
|
||||||
|
void render_forceblank();
|
||||||
void render_screen();
|
void render_screen();
|
||||||
|
|
||||||
PPU();
|
PPU();
|
||||||
|
|
|
@ -5,9 +5,13 @@ uint15 PPU::palette(uint9 index) {
|
||||||
return result;
|
return result;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void PPU::render_forceblank() {
|
||||||
|
uint16 *line = output + regs.vcounter * 240;
|
||||||
|
for(unsigned x = 0; x < 240; x++) line[x] = 0x7fff;
|
||||||
|
}
|
||||||
|
|
||||||
void PPU::render_screen() {
|
void PPU::render_screen() {
|
||||||
uint16 *line = output + regs.vcounter * 240;
|
uint16 *line = output + regs.vcounter * 240;
|
||||||
|
|
||||||
for(unsigned x = 0; x < 240; x++) {
|
for(unsigned x = 0; x < 240; x++) {
|
||||||
uint15 color = palette(0) & 0x7fff;
|
uint15 color = palette(0) & 0x7fff;
|
||||||
if(layer[3][x].exists) color = layer[3][x].color;
|
if(layer[3][x].exists) color = layer[3][x].color;
|
||||||
|
|
|
@ -27,6 +27,13 @@ struct Object {
|
||||||
unsigned height;
|
unsigned height;
|
||||||
} object[128];
|
} object[128];
|
||||||
|
|
||||||
|
struct ObjectParam {
|
||||||
|
int16 pa;
|
||||||
|
int16 pb;
|
||||||
|
int16 pc;
|
||||||
|
int16 pd;
|
||||||
|
} objectparam[32];
|
||||||
|
|
||||||
struct Tile {
|
struct Tile {
|
||||||
uint10 character;
|
uint10 character;
|
||||||
uint1 hflip;
|
uint1 hflip;
|
||||||
|
|
|
@ -28,6 +28,7 @@ void System::power() {
|
||||||
cpu.power();
|
cpu.power();
|
||||||
ppu.power();
|
ppu.power();
|
||||||
apu.power();
|
apu.power();
|
||||||
|
cartridge.power();
|
||||||
scheduler.power();
|
scheduler.power();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -21,7 +21,6 @@ void ARM::arm_step() {
|
||||||
}
|
}
|
||||||
|
|
||||||
instructions++;
|
instructions++;
|
||||||
if(pipeline.execute.address == 0x08000000) print("Entry Point\n");
|
|
||||||
if(trace) {
|
if(trace) {
|
||||||
print(disassemble_registers(), "\n");
|
print(disassemble_registers(), "\n");
|
||||||
print(disassemble_arm_instruction(pipeline.execute.address), "\n");
|
print(disassemble_arm_instruction(pipeline.execute.address), "\n");
|
||||||
|
|
|
@ -32,7 +32,7 @@ Config::Config() {
|
||||||
append(audio.frequencyNES = 1789772, "Audio::Frequency::NES");
|
append(audio.frequencyNES = 1789772, "Audio::Frequency::NES");
|
||||||
append(audio.frequencySNES = 32000, "Audio::Frequency::SNES");
|
append(audio.frequencySNES = 32000, "Audio::Frequency::SNES");
|
||||||
append(audio.frequencyGB = 4194304, "Audio::Frequency::GB");
|
append(audio.frequencyGB = 4194304, "Audio::Frequency::GB");
|
||||||
append(audio.frequencyGBA = 4194304, "Audio::Frequency::GBA");
|
append(audio.frequencyGBA = 32768, "Audio::Frequency::GBA");
|
||||||
|
|
||||||
append(input.driver = "", "Input::Driver");
|
append(input.driver = "", "Input::Driver");
|
||||||
append(input.focusPolicy = 1, "Input::FocusPolicy");
|
append(input.focusPolicy = 1, "Input::FocusPolicy");
|
||||||
|
|
|
@ -70,8 +70,8 @@ AudioSettings::AudioSettings() {
|
||||||
|
|
||||||
gba.name.setText("GBA:");
|
gba.name.setText("GBA:");
|
||||||
gba.slider.setLength(2001);
|
gba.slider.setLength(2001);
|
||||||
gba.base = 4194304;
|
gba.base = 32768;
|
||||||
gba.step = 131;
|
gba.step = 1;
|
||||||
|
|
||||||
append(title, { ~0, 0 }, 5);
|
append(title, { ~0, 0 }, 5);
|
||||||
append(outputLabel, { ~0, 0 }, 0);
|
append(outputLabel, { ~0, 0 }, 0);
|
||||||
|
|
Loading…
Reference in New Issue