bsnes/higan/gba/player/player.cpp

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#include <gba/gba.hpp>
namespace GameBoyAdvance {
//Game Boy Player emulation
Player player;
Update to v103r07 release. byuu says: Changelog: - gba/cpu: massive code cleanup effort - gba/cpu: DMA can run in between active instructions¹ - gba/cpu: added two-cycle startup delay between DMA activation and DMA transfers² - processor/spc700: BBC, BBC, CBNE cycle 4 is an idle cycle - processor/spc700: ADDW, SUBW, MOVW (read) cycle 4 is an idle cycle ¹: unfortunately, this causes yet another performance penalty for the poor GBA core =( Also, I think I may have missed disabling DMAs while the CPU is stopped. I'll fix that in the next WIP. ²: I put the waiting counter decrement at the wrong place, so this doesn't actually work. Needs to be more like this:    auto CPU::step(uint clocks) -> void {      for(auto _ : range(clocks)) {        for(auto& timer : this->timer) timer.run();        for(auto& dma : this->dma) if(dma.active && dma.waiting) dma.waiting--;        context.clock++;      }      ...    auto CPU::DMA::run() -> bool {      if(cpu.stopped() || !active || waiting) return false;      transfer();      if(irq) cpu.irq.flag |= CPU::Interrupt::DMA0 << id;      if(drq && id == 3) cpu.irq.flag |= CPU::Interrupt::Cartridge;      return true;    } Of course, the real fix will be restructuring how DMA works, so that it's always running in parallel with the CPU instead of this weird design where it tries to run all channels in some kind of loop until no channels are active anymore whenever one channel is activated. Not really sure how to design that yet, however.
2017-07-05 05:29:27 +00:00
#include "serialization.cpp"
auto Player::power() -> void {
status.enable = false;
status.rumble = false;
status.logoDetected = false;
status.logoCounter = 0;
status.packet = 0;
status.send = 0;
status.recv = 0;
}
auto Player::frame() -> void {
Update to v094r09 release. byuu says: This will easily be the biggest diff in the history of higan. And not in a good way. * target-higan and target-loki have been blown away completely * nall and ruby massively updated * phoenix replaced with hiro (pretty near a total rewrite) * target-higan restarted using hiro (just a window for now) * all emulation cores updated to compile again * installation changed to not require root privileges (installs locally) For the foreseeable future (maybe even permanently?), the new higan UI will only build under Linux/BSD with GTK+ 2.20+. Probably the most likely route for Windows/OS X will be to try and figure out how to build hiro/GTK on those platforms, as awful as that would be. The other alternative would be to produce new UIs for those platforms ... which would actually be a good opportunity to make something much more user friendly. Being that I just started on this a few hours ago, that means that for at least a few weeks, don't expect to be able to actually play any games. Right now, you can pretty much just compile the binary and that's it. It's quite possible that some nall changes didn't produce compilation errors, but will produce runtime errors. So until the UI can actually load games, we won't know if anything is broken. But we should mostly be okay. It was mostly just trim<1> -> trim changes, moving to Hash::SHA256 (much cleaner), and patching some reckless memory copy functions enough to compile. Progress isn't going to be like it was before: I'm now dividing my time much thinner between studying and other hobbies. My aim this time is not to produce a binary for everyone to play games on. Rather, it's to keep the emulator alive. I want to be able to apply critical patches again. And I would also like the base of the emulator to live on, for use in other emulator frontends that utilize higan.
2015-02-26 10:10:46 +00:00
uint32 hash = Hash::CRC32(ppu.output, 240 * 160 * sizeof(uint32)).value();
status.logoDetected = (hash == 0x7776eb55);
if(status.logoDetected) {
status.enable = true;
status.logoCounter = (status.logoCounter + 1) % 3;
status.packet = 0;
}
if(!status.enable) return;
//todo: verify which settings are actually required
//values were taken from observing GBP-compatible games
Update to v103r07 release. byuu says: Changelog: - gba/cpu: massive code cleanup effort - gba/cpu: DMA can run in between active instructions¹ - gba/cpu: added two-cycle startup delay between DMA activation and DMA transfers² - processor/spc700: BBC, BBC, CBNE cycle 4 is an idle cycle - processor/spc700: ADDW, SUBW, MOVW (read) cycle 4 is an idle cycle ¹: unfortunately, this causes yet another performance penalty for the poor GBA core =( Also, I think I may have missed disabling DMAs while the CPU is stopped. I'll fix that in the next WIP. ²: I put the waiting counter decrement at the wrong place, so this doesn't actually work. Needs to be more like this:    auto CPU::step(uint clocks) -> void {      for(auto _ : range(clocks)) {        for(auto& timer : this->timer) timer.run();        for(auto& dma : this->dma) if(dma.active && dma.waiting) dma.waiting--;        context.clock++;      }      ...    auto CPU::DMA::run() -> bool {      if(cpu.stopped() || !active || waiting) return false;      transfer();      if(irq) cpu.irq.flag |= CPU::Interrupt::DMA0 << id;      if(drq && id == 3) cpu.irq.flag |= CPU::Interrupt::Cartridge;      return true;    } Of course, the real fix will be restructuring how DMA works, so that it's always running in parallel with the CPU instead of this weird design where it tries to run all channels in some kind of loop until no channels are active anymore whenever one channel is activated. Not really sure how to design that yet, however.
2017-07-05 05:29:27 +00:00
if(!cpu.joybus.sc
&& !cpu.joybus.sd
&& !cpu.joybus.si
&& !cpu.joybus.so
&& !cpu.joybus.scMode
&& !cpu.joybus.sdMode
&& !cpu.joybus.siMode
&& !cpu.joybus.soMode
&& !cpu.joybus.siIRQEnable
&& !cpu.joybus.mode
&& !cpu.serial.shiftClockSelect
&& !cpu.serial.shiftClockFrequency
&& !cpu.serial.transferEnableReceive
&& cpu.serial.transferEnableSend
&& cpu.serial.startBit
&& cpu.serial.transferLength
&& cpu.serial.irqEnable
) {
status.packet = (status.packet + 1) % 17;
switch(status.packet) {
case 0: status.send = 0x0000494e; break;
case 1: status.send = 0xb6b1494e; break;
case 2: status.send = 0xb6b1494e; break;
case 3: status.send = 0xb6b1544e; break;
case 4: status.send = 0xabb1544e; break;
case 5: status.send = 0xabb14e45; break;
case 6: status.send = 0xb1ba4e45; break;
case 7: status.send = 0xb1ba4f44; break;
case 8: status.send = 0xb0bb4f44; break;
case 9: status.send = 0xb0bb8002; break;
case 10: status.send = 0x10000010; break;
case 11: status.send = 0x20000013; break;
case 12: status.send = 0x30000003; break;
case 13: status.send = 0x30000003; break;
case 14: status.send = 0x30000003; break;
case 15: status.send = 0x30000003; break;
case 16: status.send = 0x30000003; break;
}
Update to v103r07 release. byuu says: Changelog: - gba/cpu: massive code cleanup effort - gba/cpu: DMA can run in between active instructions¹ - gba/cpu: added two-cycle startup delay between DMA activation and DMA transfers² - processor/spc700: BBC, BBC, CBNE cycle 4 is an idle cycle - processor/spc700: ADDW, SUBW, MOVW (read) cycle 4 is an idle cycle ¹: unfortunately, this causes yet another performance penalty for the poor GBA core =( Also, I think I may have missed disabling DMAs while the CPU is stopped. I'll fix that in the next WIP. ²: I put the waiting counter decrement at the wrong place, so this doesn't actually work. Needs to be more like this:    auto CPU::step(uint clocks) -> void {      for(auto _ : range(clocks)) {        for(auto& timer : this->timer) timer.run();        for(auto& dma : this->dma) if(dma.active && dma.waiting) dma.waiting--;        context.clock++;      }      ...    auto CPU::DMA::run() -> bool {      if(cpu.stopped() || !active || waiting) return false;      transfer();      if(irq) cpu.irq.flag |= CPU::Interrupt::DMA0 << id;      if(drq && id == 3) cpu.irq.flag |= CPU::Interrupt::Cartridge;      return true;    } Of course, the real fix will be restructuring how DMA works, so that it's always running in parallel with the CPU instead of this weird design where it tries to run all channels in some kind of loop until no channels are active anymore whenever one channel is activated. Not really sure how to design that yet, however.
2017-07-05 05:29:27 +00:00
cpu.irq.flag |= CPU::Interrupt::Serial;
}
}
auto Player::keyinput() -> maybe<uint16> {
if(status.logoDetected) {
switch(status.logoCounter) {
case 0: return {0x03ff};
case 1: return {0x03ff};
case 2: return {0x030f};
}
}
return nothing;
}
auto Player::read() -> maybe<uint32> {
if(status.enable) return status.send;
return nothing;
}
auto Player::write(uint2 addr, uint8 byte) -> void {
if(!status.enable) return;
uint shift = addr << 3;
status.recv &= ~(255 << shift);
status.recv |= byte << shift;
if(addr == 3 && status.packet == 15) {
status.rumble = (status.recv & 0xff) == 0x26; //on = 0x26, off = 0x04
platform->inputRumble(0, 0, 10, status.rumble);
}
}
}