2012-04-29 06:16:44 +00:00
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#include <sfc/sfc.hpp>
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2010-08-09 13:28:56 +00:00
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2012-04-26 10:51:13 +00:00
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namespace SuperFamicom {
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2010-08-09 13:28:56 +00:00
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Update to v085r03 release.
byuu says:
Changelog:
- fixed cursor being visible under Metacity window manager (hopefully
doesn't cause regression with other WMs)
- show normal cursor when using SDL video driver
- added menu accelerators (meh, why not?)
- removed debugvirtual, ChipDebugger and chip/debugger functionality
entirely
- alt/smp disassembler moved up
- fixed alt/smp incw/decw instructions (unsigned->uint16 for internal
variables)
My plan going forward for a debugger is not to hardcode functionality
that causes the 10-15% slowdown right into the emulator itself.
Instead, I'm going to make a callback class, which will be a specialized
version of nall::function:
- can call function even if not assigned (results in no-op, return type
must have a trivial default constructor)
- if compiled without #define DEBUGGER, the entire thing turns into
a huge no-op; and will be eliminated entirely when compiled
- strategically place the functions: cb_step, cb_read, cb_write, etc.
From here, the ui-debugger GUI will bind the callbacks, implement
breakpoint checking, usage table generation, etc itself.
I'll probably have to add some breakout commands to exit the emulation
core prior to a frame event in some cases as well.
I didn't initially want any debugger-related stuff in the base cores,
but the #if debugger sCPUDebugger #else sCPU #endif stuff was already
more of a burden than this will be.
2012-02-04 09:23:53 +00:00
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SMP smp;
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2010-08-09 13:28:56 +00:00
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2012-04-29 06:16:44 +00:00
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#include "memory.cpp"
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#include "timing.cpp"
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2010-08-09 13:28:56 +00:00
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#include "serialization.cpp"
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2015-11-10 11:02:29 +00:00
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auto SMP::step(uint clocks) -> void {
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2010-08-09 13:28:56 +00:00
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clock += clocks * (uint64)cpu.frequency;
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dsp.clock -= clocks;
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}
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2015-11-10 11:02:29 +00:00
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auto SMP::synchronizeCPU() -> void {
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Update to v098r01 release.
byuu says:
Changelog:
- SFC: balanced profile removed
- SFC: performance profile removed
- SFC: code for handling non-threaded CPU, SMP, DSP, PPU removed
- SFC: Coprocessor, Controller (and expansion port) shared Thread code
merged to SFC::Cothread
- Cothread here just means "Thread with CPU affinity" (couldn't think
of a better name, sorry)
- SFC: CPU now has vector<Thread*> coprocessors, peripherals;
- this is the beginning of work to allow expansion port devices to be
dynamically changed at run-time
- ruby: all audio drivers default to 48000hz instead of 22050hz now if
no frequency is assigned
- note: the WASAPI driver can default to whatever the native frequency
is; doesn't have to be 48000hz
- tomoko: removed the ability to change the frequency from the UI (but
it will display the frequency used)
- tomoko: removed the timing settings panel
- the goal is to work toward smooth video via adaptive sync
- the model is broken by not being in control of the audio frequency
anyway
- it's further broken by PAL running at 50hz and WSC running at 75hz
- it was always broken anyway by SNES interlace timing varying from
progressive timing
- higan: audio/ stub created (for now, it's just nall/dsp/ moved here
and included as a header)
- higan: video/ stub created
- higan/GNUmakefile: now includes build rules for essential components
(libco, emulator, audio, video)
The audio changes are in preparation to merge wareya's awesome WASAPI
work without the need for the nall/dsp resampler.
2016-04-09 03:40:12 +00:00
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if(clock >= 0 && !scheduler.synchronizing()) co_switch(cpu.thread);
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2010-08-09 13:28:56 +00:00
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}
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2015-11-10 11:02:29 +00:00
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auto SMP::synchronizeDSP() -> void {
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Update to v098r01 release.
byuu says:
Changelog:
- SFC: balanced profile removed
- SFC: performance profile removed
- SFC: code for handling non-threaded CPU, SMP, DSP, PPU removed
- SFC: Coprocessor, Controller (and expansion port) shared Thread code
merged to SFC::Cothread
- Cothread here just means "Thread with CPU affinity" (couldn't think
of a better name, sorry)
- SFC: CPU now has vector<Thread*> coprocessors, peripherals;
- this is the beginning of work to allow expansion port devices to be
dynamically changed at run-time
- ruby: all audio drivers default to 48000hz instead of 22050hz now if
no frequency is assigned
- note: the WASAPI driver can default to whatever the native frequency
is; doesn't have to be 48000hz
- tomoko: removed the ability to change the frequency from the UI (but
it will display the frequency used)
- tomoko: removed the timing settings panel
- the goal is to work toward smooth video via adaptive sync
- the model is broken by not being in control of the audio frequency
anyway
- it's further broken by PAL running at 50hz and WSC running at 75hz
- it was always broken anyway by SNES interlace timing varying from
progressive timing
- higan: audio/ stub created (for now, it's just nall/dsp/ moved here
and included as a header)
- higan: video/ stub created
- higan/GNUmakefile: now includes build rules for essential components
(libco, emulator, audio, video)
The audio changes are in preparation to merge wareya's awesome WASAPI
work without the need for the nall/dsp resampler.
2016-04-09 03:40:12 +00:00
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if(dsp.clock < 0 && !scheduler.synchronizing()) co_switch(dsp.thread);
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2010-08-09 13:28:56 +00:00
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}
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2016-02-09 11:51:12 +00:00
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auto SMP::Enter() -> void {
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while(true) scheduler.synchronize(), smp.main();
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}
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2010-08-09 13:28:56 +00:00
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2016-02-09 11:51:12 +00:00
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auto SMP::main() -> void {
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2016-06-17 13:03:54 +00:00
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debugger.execute(regs.pc);
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2016-06-05 04:52:43 +00:00
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instruction();
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2010-08-09 13:28:56 +00:00
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}
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2015-11-10 11:02:29 +00:00
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auto SMP::power() -> void {
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2010-08-09 13:28:56 +00:00
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//targets not initialized/changed upon reset
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2011-05-05 11:37:46 +00:00
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timer0.target = 0;
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timer1.target = 0;
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timer2.target = 0;
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2010-08-09 13:28:56 +00:00
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}
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2015-11-10 11:02:29 +00:00
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auto SMP::reset() -> void {
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create(Enter, system.apuFrequency());
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2010-08-09 13:28:56 +00:00
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2015-11-10 11:02:29 +00:00
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regs.pc.l = iplrom[62];
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regs.pc.h = iplrom[63];
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Updated to v067r23 release.
byuu says:
Added missing $4200 IRQ lock, which fixes Chou Aniki on the fast CPU
core, so slower PCs can get their brotherly love on.
Added range-based controller IOBit latching to the fast CPU core, which
enables Super Scope and Justifier support. Uses the priority queue as
well, so there is zero speed-hit. Given the way range-testing works, the
trigger point may vary by 1-2 pixels when firing at the same spot. Not
really a big deal when it avoids a massive speed penalty.
Fixed PAL and interlace-mode HVIRQs at V=0,H<2 on the fast CPU core.
Added the dot-renderer's sprite list update-on-OAM-write functionality
to the scanline-based PPU renderer. Unfortunately it looks like all the
speed gain was already taken from the global dirty flag I was using
before, but this certainly won't hurt speed any, so whatever.
Added #ifdef to stop CoInitialize(0) on non-Windows ports.
Added #ifdefs to stop gradient fade on Windows port. Not going to fuck
over the Linux port aesthetic because of Qt bug #47,326,927. If there's
a way to tell what Qt theme is being used, I can leave it enabled for
XP/Vista themes.
Moved HDMA trigger from 1104 to 1112, and reduced channel overhead from
24 to 16, to better simulate one-cycle DMA->CPU sync.
Code clarity: I've re-added my varint.hpp classes, and am actively using
them in the accuracy cores. So far, I haven't done anything that would
detriment speed, but it is certainly cool. The APU ports exposed by the
CPU and SMP now take uint2 address arguments, the CPU WRAM address
register is a uint17, and the IRQ H/VTIME values are uint10. This
basically allows the source to clearly convey the data sizes, and
eliminates the need to manually mask values when writing to registers or
reading from memory. I'm going to be doing this everywhere, and it will
have a speed impact eventually, because the automation means we can't
skip masks when we know the data is already masked off.
Source: archive contains the launcher code, so that I can look into why
it's crashing on XP tomorrow.
It doesn't look like Circuit USA's flags are going to work too well with
this new CPU core. Still not sure what the hell Robocop vs The
Terminator is doing, I'll read through the mega SNES thread for clues
tomorrow. Speedy Gonzales is definitely broken, as modifying the MDR was
breaking things with my current core. Probably because the new CPU core
doesn't wait for a cycle edge to trigger.
I was thinking that perhaps we could keep some form of cheat codes list
to work as game-specific hacks for the performance core. Keeps the hacks
out of the emulator, but could allow the remaining bugs to be worked
around for people who have no choice but to use the performance core.
2010-08-16 09:42:20 +00:00
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regs.a = 0x00;
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regs.x = 0x00;
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regs.y = 0x00;
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Update to v084r01 release.
I rewrote the S-SMP processor core (implementation of the 256 opcodes),
utilizing my new 6502-like syntax. It matches what bass v05r01 uses.
Took 10 hours.
Due to being able to group the "mov reg,mem" opcodes together with
"adc/sbc/ora/and/eor/cmp" sets, the total code size was reduced from
55.7KB to 42.5KB for identical accuracy and speed.
I also dropped the trick I was using to pass register variables as
template arguments, and instead just use a switch table to pass them as
function arguments. Makes the table a lot easier to read.
Passes all of my S-SMP tests, and all of blargg's
arithmetic/cycle-timing S-SMP tests. Runs Zelda 3 great as well. Didn't
test further.
This does have the potential to cause some regressions if I've messed
anything up, and none of the above tests caught it, so as always,
testing would be appreciated.
Anyway, yeah. By writing the actual processor with this new mnemonic
set, it confirms the parallels I've made.
My guess is that Sony really did clone the 6502, but was worried about
legal implications or something and changed the mnemonics last-minute.
(Note to self: need to re-enable snes.random before v085 official.)
EDIT: oh yeah, I also commented out the ALSA snd_pcm_drain() inside
term(). Without it, there is a tiny pop when the driver is
re-initialized. But with it, the entire emulator would lock up for five
whole seconds waiting on that call to complete. I'll take the pop any
day over that.
2011-11-17 12:05:35 +00:00
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regs.s = 0xef;
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Updated to v067r23 release.
byuu says:
Added missing $4200 IRQ lock, which fixes Chou Aniki on the fast CPU
core, so slower PCs can get their brotherly love on.
Added range-based controller IOBit latching to the fast CPU core, which
enables Super Scope and Justifier support. Uses the priority queue as
well, so there is zero speed-hit. Given the way range-testing works, the
trigger point may vary by 1-2 pixels when firing at the same spot. Not
really a big deal when it avoids a massive speed penalty.
Fixed PAL and interlace-mode HVIRQs at V=0,H<2 on the fast CPU core.
Added the dot-renderer's sprite list update-on-OAM-write functionality
to the scanline-based PPU renderer. Unfortunately it looks like all the
speed gain was already taken from the global dirty flag I was using
before, but this certainly won't hurt speed any, so whatever.
Added #ifdef to stop CoInitialize(0) on non-Windows ports.
Added #ifdefs to stop gradient fade on Windows port. Not going to fuck
over the Linux port aesthetic because of Qt bug #47,326,927. If there's
a way to tell what Qt theme is being used, I can leave it enabled for
XP/Vista themes.
Moved HDMA trigger from 1104 to 1112, and reduced channel overhead from
24 to 16, to better simulate one-cycle DMA->CPU sync.
Code clarity: I've re-added my varint.hpp classes, and am actively using
them in the accuracy cores. So far, I haven't done anything that would
detriment speed, but it is certainly cool. The APU ports exposed by the
CPU and SMP now take uint2 address arguments, the CPU WRAM address
register is a uint17, and the IRQ H/VTIME values are uint10. This
basically allows the source to clearly convey the data sizes, and
eliminates the need to manually mask values when writing to registers or
reading from memory. I'm going to be doing this everywhere, and it will
have a speed impact eventually, because the automation means we can't
skip masks when we know the data is already masked off.
Source: archive contains the launcher code, so that I can look into why
it's crashing on XP tomorrow.
It doesn't look like Circuit USA's flags are going to work too well with
this new CPU core. Still not sure what the hell Robocop vs The
Terminator is doing, I'll read through the mega SNES thread for clues
tomorrow. Speedy Gonzales is definitely broken, as modifying the MDR was
breaking things with my current core. Probably because the new CPU core
doesn't wait for a cycle edge to trigger.
I was thinking that perhaps we could keep some form of cheat codes list
to work as game-specific hacks for the performance core. Keeps the hacks
out of the emulator, but could allow the remaining bugs to be worked
around for people who have no choice but to use the performance core.
2010-08-16 09:42:20 +00:00
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regs.p = 0x02;
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2010-08-09 13:28:56 +00:00
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2015-11-10 11:02:29 +00:00
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for(auto& byte : apuram) byte = random(0x00);
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2011-05-05 11:37:46 +00:00
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apuram[0x00f4] = 0x00;
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apuram[0x00f5] = 0x00;
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apuram[0x00f6] = 0x00;
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apuram[0x00f7] = 0x00;
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2010-08-09 13:28:56 +00:00
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2015-11-10 11:02:29 +00:00
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status.clockCounter = 0;
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status.dspCounter = 0;
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status.timerStep = 3;
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2010-08-09 13:28:56 +00:00
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//$00f0
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2015-11-10 11:02:29 +00:00
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status.clockSpeed = 0;
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status.timerSpeed = 0;
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status.timersEnable = true;
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status.ramDisable = false;
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status.ramWritable = true;
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status.timersDisable = false;
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2010-08-09 13:28:56 +00:00
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//$00f1
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2015-11-10 11:02:29 +00:00
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status.iplromEnable = true;
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2010-08-09 13:28:56 +00:00
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//$00f2
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2015-11-10 11:02:29 +00:00
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status.dspAddr = 0x00;
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2010-08-09 13:28:56 +00:00
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//$00f8,$00f9
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2011-05-02 13:53:16 +00:00
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status.ram00f8 = 0x00;
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status.ram00f9 = 0x00;
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2010-08-09 13:28:56 +00:00
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2015-11-10 11:02:29 +00:00
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timer0.stage0 = 0;
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timer1.stage0 = 0;
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timer2.stage0 = 0;
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2010-08-09 13:28:56 +00:00
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2015-11-10 11:02:29 +00:00
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timer0.stage1 = 0;
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timer1.stage1 = 0;
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timer2.stage1 = 0;
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2010-08-09 13:28:56 +00:00
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2015-11-10 11:02:29 +00:00
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timer0.stage2 = 0;
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timer1.stage2 = 0;
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timer2.stage2 = 0;
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2010-08-09 13:28:56 +00:00
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2015-11-10 11:02:29 +00:00
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timer0.stage3 = 0;
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timer1.stage3 = 0;
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timer2.stage3 = 0;
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2010-08-09 13:28:56 +00:00
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2015-11-10 11:02:29 +00:00
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timer0.line = 0;
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timer1.line = 0;
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timer2.line = 0;
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2010-08-09 13:28:56 +00:00
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2011-05-05 11:37:46 +00:00
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timer0.enable = false;
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timer1.enable = false;
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timer2.enable = false;
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2010-08-09 13:28:56 +00:00
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}
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}
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