bsnes/higan/processor/v30mz/v30mz.hpp

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//NEC V30MZ
#pragma once
namespace Processor {
struct V30MZ {
using Size = uint;
enum : uint { Byte = 1, Word = 2, Long = 4 };
Update to v097r24 release. byuu says: Changelog: - WS: fixed bug when IRQs triggered during a rep string instruction - WS: added sprite attribute caching (per-scanline); absolutely massive speed-up - WS: emulated limit of 32 sprites per scanline - WS: emulated the extended PPU register bit behavior based on the DISP_CTRL tile bit-depth setting - WS: added "Rotate" key binding; can be used to flip the WS display between horizontal and vertical in real-time The prefix emulation may not be 100% hardware-accurate, but the edge cases should be extreme enough to not come up in the WS library. No way to get the emulation 100% down without intensive hardware testing. trap15 pointed me at a workflow diagram for it, but that diagram is impossible without a magic internal stack frame that grows with every IRQ, and can thus grow infinitely large. The rotation thing isn't exactly the most friendly set-up, but oh well. I'll see about adding a default rotation setting to manifests, so that games like GunPey can start in the correct orientation. After that, if the LCD orientation icon turns out to be reliable, then I'll start using that. But if there are cases where it's not reliable, then I'll leave it to manual button presses. Speaking of icons, I'll need a set of icons to render on the screen. Going to put them to the top right on vertical orientation, and on the bottom left for horizontal orientation. Just outside of the video output, of course. Overall, WS is getting pretty far along, but still some major bugs in various games. I really need sound emulation, though. Nobody's going to use this at all without that.
2016-03-12 13:27:41 +00:00
enum : uint {
SegmentOverrideES = 0x26,
SegmentOverrideCS = 0x2e,
SegmentOverrideSS = 0x36,
SegmentOverrideDS = 0x3e,
Lock = 0xf0,
RepeatWhileNotZero = 0xf2,
RepeatWhileZero = 0xf3,
};
virtual auto wait(uint clocks = 1) -> void = 0;
virtual auto read(uint20 addr) -> uint8 = 0;
virtual auto write(uint20 addr, uint8 data) -> void = 0;
virtual auto in(uint16 port) -> uint8 = 0;
virtual auto out(uint16 port, uint8 data) -> void = 0;
auto warning(string text) -> void;
Update to v097r24 release. byuu says: Changelog: - WS: fixed bug when IRQs triggered during a rep string instruction - WS: added sprite attribute caching (per-scanline); absolutely massive speed-up - WS: emulated limit of 32 sprites per scanline - WS: emulated the extended PPU register bit behavior based on the DISP_CTRL tile bit-depth setting - WS: added "Rotate" key binding; can be used to flip the WS display between horizontal and vertical in real-time The prefix emulation may not be 100% hardware-accurate, but the edge cases should be extreme enough to not come up in the WS library. No way to get the emulation 100% down without intensive hardware testing. trap15 pointed me at a workflow diagram for it, but that diagram is impossible without a magic internal stack frame that grows with every IRQ, and can thus grow infinitely large. The rotation thing isn't exactly the most friendly set-up, but oh well. I'll see about adding a default rotation setting to manifests, so that games like GunPey can start in the correct orientation. After that, if the LCD orientation icon turns out to be reliable, then I'll start using that. But if there are cases where it's not reliable, then I'll leave it to manual button presses. Speaking of icons, I'll need a set of icons to render on the screen. Going to put them to the top right on vertical orientation, and on the bottom left for horizontal orientation. Just outside of the video output, of course. Overall, WS is getting pretty far along, but still some major bugs in various games. I really need sound emulation, though. Nobody's going to use this at all without that.
2016-03-12 13:27:41 +00:00
auto power() -> void;
auto exec() -> void;
Update to v102r24 release. byuu says Changelog: - FC: fixed three MOS6502 regressions [hex\_usr] - GBA: return fetched instruction instead of 0 for unmapped MMIO (passes all of endrift's I/O tests) - MD: fix VDP control port read Vblank bit to test screen height instead of hard-code 240 (fixes Phantasy Star IV) - MD: swap USP,SSP when executing an exception (allows Super Street Fighter II to run; but no sprites visible yet) - MD: grant 68K access to Z80 bus on reset (fixes vdpdoc demo ROM from freezing immediately) - SFC: reads from $00-3f,80-bf:4000-43ff no longer update MDR [p4plus2] - SFC: massive, eight-hour cleanup of WDC65816 CPU core ... still not complete The big change this time around is the SFC CPU core. I've renamed everything from R65816 to WDC65816, and then went through and tried to clean up the code as much as possible. This core is so much larger than the 6502 core that I chose cleaning up the code to rewriting it. First off, I really don't care for the BitRange style functionality. It was an interesting experiment, but its fatal flaw are that the types are just bizarre, which makes them hard to pass around generically to other functions as arguments. So I went back to the list of bools for flags, and union/struct blocks for the registers. Next, I renamed all of the functions to be more descriptive: eg `op_read_idpx_w` becomes `instructionIndexedIndirectRead16`. `op_adc_b` becomes `algorithmADC8`. And so forth. I eliminated about ten instructions because they were functionally identical sans the index, so I just added a uint index=0 parameter to said functions. I added a few new ones (adjust→INC,DEC; pflag→REP,SEP) where it seemed appropriate. I cleaned up the disaster of the instruction switch table into something a whole lot more elegant without all the weird argument decoding nonsense (still need M vs X variants to avoid having to have 4-5 separate switch tables, but all the F/I flags are gone now); and made some things saner, like the flag clear/set and branch conditions, now that I have normal types for flags and registers once again. I renamed all of the memory access functions to be more descriptive to what they're doing: eg writeSP→push, readPC→fetch, writeDP→writeDirect, etc. Eliminated some of the special read/write modes that were only used in one single instruction. I started to clean up some of the actual instructions themselves, but haven't really accomplished much here. The big thing I want to do is get rid of the global state (aa, rd, iaddr, etc) and instead use local variables like I am doing with my other 65xx CPU cores now. But this will take some time ... the algorithm functions depend on rd to be set to work on them, rather than taking arguments. So I'll need to rework that. And then lastly, the disassembler is still a mess. I want to finish the CPU cleanups, and then post a new WIP, and then rewrite the disassembler after that. The reason being ... I want a WIP that can generate identical trace logs to older versions, in case the CPU cleanup causes any regressions. That way I can more easily spot the errors. Oh ... and a bit of good news. v102 was running at ~140fps on the SNES core. With the new support to suspend/resume WAI/STP, plus the internal CPU registers not updating the MDR, the framerate dropped to ~132fps. But with the CPU cleanups, performance went back to ~140fps. So, hooray. Of course, without those two other improvements, we'd have ended up at possibly ~146-148fps, but oh well.
2017-06-13 01:42:31 +00:00
//instruction.cpp
auto interrupt(uint8 vector) -> void;
Update to v097r24 release. byuu says: Changelog: - WS: fixed bug when IRQs triggered during a rep string instruction - WS: added sprite attribute caching (per-scanline); absolutely massive speed-up - WS: emulated limit of 32 sprites per scanline - WS: emulated the extended PPU register bit behavior based on the DISP_CTRL tile bit-depth setting - WS: added "Rotate" key binding; can be used to flip the WS display between horizontal and vertical in real-time The prefix emulation may not be 100% hardware-accurate, but the edge cases should be extreme enough to not come up in the WS library. No way to get the emulation 100% down without intensive hardware testing. trap15 pointed me at a workflow diagram for it, but that diagram is impossible without a magic internal stack frame that grows with every IRQ, and can thus grow infinitely large. The rotation thing isn't exactly the most friendly set-up, but oh well. I'll see about adding a default rotation setting to manifests, so that games like GunPey can start in the correct orientation. After that, if the LCD orientation icon turns out to be reliable, then I'll start using that. But if there are cases where it's not reliable, then I'll leave it to manual button presses. Speaking of icons, I'll need a set of icons to render on the screen. Going to put them to the top right on vertical orientation, and on the bottom left for horizontal orientation. Just outside of the video output, of course. Overall, WS is getting pretty far along, but still some major bugs in various games. I really need sound emulation, though. Nobody's going to use this at all without that.
2016-03-12 13:27:41 +00:00
auto instruction() -> void;
//registers.cpp
Update to v097r24 release. byuu says: Changelog: - WS: fixed bug when IRQs triggered during a rep string instruction - WS: added sprite attribute caching (per-scanline); absolutely massive speed-up - WS: emulated limit of 32 sprites per scanline - WS: emulated the extended PPU register bit behavior based on the DISP_CTRL tile bit-depth setting - WS: added "Rotate" key binding; can be used to flip the WS display between horizontal and vertical in real-time The prefix emulation may not be 100% hardware-accurate, but the edge cases should be extreme enough to not come up in the WS library. No way to get the emulation 100% down without intensive hardware testing. trap15 pointed me at a workflow diagram for it, but that diagram is impossible without a magic internal stack frame that grows with every IRQ, and can thus grow infinitely large. The rotation thing isn't exactly the most friendly set-up, but oh well. I'll see about adding a default rotation setting to manifests, so that games like GunPey can start in the correct orientation. After that, if the LCD orientation icon turns out to be reliable, then I'll start using that. But if there are cases where it's not reliable, then I'll leave it to manual button presses. Speaking of icons, I'll need a set of icons to render on the screen. Going to put them to the top right on vertical orientation, and on the bottom left for horizontal orientation. Just outside of the video output, of course. Overall, WS is getting pretty far along, but still some major bugs in various games. I really need sound emulation, though. Nobody's going to use this at all without that.
2016-03-12 13:27:41 +00:00
auto repeat() -> uint8;
auto segment(uint16) -> uint16;
auto getAcc(Size) -> uint32;
auto setAcc(Size, uint32) -> void;
//modrm.cpp
auto modRM() -> void;
auto getMem(Size, uint offset = 0) -> uint16;
auto setMem(Size, uint16) -> void;
auto getReg(Size) -> uint16;
auto setReg(Size, uint16) -> void;
auto getSeg() -> uint16;
auto setSeg(uint16) -> void;
//memory.cpp
auto read(Size, uint16, uint16) -> uint32;
auto write(Size, uint16, uint16, uint16) -> void;
auto in(Size, uint16) -> uint16;
auto out(Size, uint16, uint16) -> void;
auto fetch(Size = Byte) -> uint16;
auto pop() -> uint16;
auto push(uint16) -> void;
//algorithms.cpp
auto parity(uint8) const -> bool;
Update to v103r31 release. byuu says: Changelog: - gba/cpu: slight speedup to CPU::step() - processor/arm7tdmi: fixed about ten bugs, ST018 and GBA games are now playable once again - processor/arm: removed core from codebase - processor/v30mz: code cleanup (renamed functions; updated instruction() for consistency with other cores) It turns out on my much faster system, the new ARM7TDMI core is very slightly slower than the old one (by about 2% or so FPS.) But the CPU::step() improvement basically made it a wash. So yeah, I'm in really serious trouble with how slow my GBA core is now. Sigh. As for higan/processor ... this concludes the first phase of major cleanups and rewrites. There will always be work to do, and I have two more phases in mind. One is that a lot of the instruction disassemblers are very old. One even uses sprintf still. I'd like to modernize them all. Also, the ARM7TDMI core (and the ARM core before it) can't really disassemble because the PC address used for instruction execution is not known prior to calling instruction(), due to pipeline reload fetches that may occur inside of said function. I had a nasty hack for debugging the new core, but I'd like to come up with a clean way to allow tracing the new ARM7TDMI core. Another is that I'd still like to rename a lot of instruction function names in various cores to be more descriptive. I really liked how the LR35902 core came out there, and would like to get that level of detail in with the other cores as well.
2017-08-10 11:26:02 +00:00
auto ADC (Size, uint16, uint16) -> uint16;
auto ADD (Size, uint16, uint16) -> uint16;
auto AND (Size, uint16, uint16) -> uint16;
auto DEC (Size, uint16 ) -> uint16;
auto DIV (Size, uint32, uint32) -> uint32;
auto DIVI(Size, int32, int32) -> uint32;
auto INC (Size, uint16 ) -> uint16;
auto MUL (Size, uint16, uint16) -> uint32;
auto MULI(Size, int16, int16) -> uint32;
auto NEG (Size, uint16 ) -> uint16;
auto NOT (Size, uint16 ) -> uint16;
auto OR (Size, uint16, uint16) -> uint16;
auto RCL (Size, uint16, uint5) -> uint16;
auto RCR (Size, uint16, uint5) -> uint16;
auto ROL (Size, uint16, uint4) -> uint16;
auto ROR (Size, uint16, uint4) -> uint16;
auto SAL (Size, uint16, uint5) -> uint16;
auto SAR (Size, uint16, uint5) -> uint16;
auto SBB (Size, uint16, uint16) -> uint16;
auto SUB (Size, uint16, uint16) -> uint16;
auto SHL (Size, uint16, uint5) -> uint16;
auto SHR (Size, uint16, uint5) -> uint16;
auto XOR (Size, uint16, uint16) -> uint16;
//instructions-adjust.cpp
Update to v103r31 release. byuu says: Changelog: - gba/cpu: slight speedup to CPU::step() - processor/arm7tdmi: fixed about ten bugs, ST018 and GBA games are now playable once again - processor/arm: removed core from codebase - processor/v30mz: code cleanup (renamed functions; updated instruction() for consistency with other cores) It turns out on my much faster system, the new ARM7TDMI core is very slightly slower than the old one (by about 2% or so FPS.) But the CPU::step() improvement basically made it a wash. So yeah, I'm in really serious trouble with how slow my GBA core is now. Sigh. As for higan/processor ... this concludes the first phase of major cleanups and rewrites. There will always be work to do, and I have two more phases in mind. One is that a lot of the instruction disassemblers are very old. One even uses sprintf still. I'd like to modernize them all. Also, the ARM7TDMI core (and the ARM core before it) can't really disassemble because the PC address used for instruction execution is not known prior to calling instruction(), due to pipeline reload fetches that may occur inside of said function. I had a nasty hack for debugging the new core, but I'd like to come up with a clean way to allow tracing the new ARM7TDMI core. Another is that I'd still like to rename a lot of instruction function names in various cores to be more descriptive. I really liked how the LR35902 core came out there, and would like to get that level of detail in with the other cores as well.
2017-08-10 11:26:02 +00:00
auto instructionDecimalAdjust(bool) -> void;
auto instructionAsciiAdjust(bool) -> void;
auto instructionAdjustAfterMultiply() -> void;
auto instructionAdjustAfterDivide() -> void;
//instructions-alu.cpp
Update to v103r31 release. byuu says: Changelog: - gba/cpu: slight speedup to CPU::step() - processor/arm7tdmi: fixed about ten bugs, ST018 and GBA games are now playable once again - processor/arm: removed core from codebase - processor/v30mz: code cleanup (renamed functions; updated instruction() for consistency with other cores) It turns out on my much faster system, the new ARM7TDMI core is very slightly slower than the old one (by about 2% or so FPS.) But the CPU::step() improvement basically made it a wash. So yeah, I'm in really serious trouble with how slow my GBA core is now. Sigh. As for higan/processor ... this concludes the first phase of major cleanups and rewrites. There will always be work to do, and I have two more phases in mind. One is that a lot of the instruction disassemblers are very old. One even uses sprintf still. I'd like to modernize them all. Also, the ARM7TDMI core (and the ARM core before it) can't really disassemble because the PC address used for instruction execution is not known prior to calling instruction(), due to pipeline reload fetches that may occur inside of said function. I had a nasty hack for debugging the new core, but I'd like to come up with a clean way to allow tracing the new ARM7TDMI core. Another is that I'd still like to rename a lot of instruction function names in various cores to be more descriptive. I really liked how the LR35902 core came out there, and would like to get that level of detail in with the other cores as well.
2017-08-10 11:26:02 +00:00
auto instructionAddMemReg(Size) -> void;
auto instructionAddRegMem(Size) -> void;
auto instructionAddAccImm(Size) -> void;
auto instructionOrMemReg(Size) -> void;
auto instructionOrRegMem(Size) -> void;
auto instructionOrAccImm(Size) -> void;
auto instructionAdcMemReg(Size) -> void;
auto instructionAdcRegMem(Size) -> void;
auto instructionAdcAccImm(Size) -> void;
auto instructionSbbMemReg(Size) -> void;
auto instructionSbbRegMem(Size) -> void;
auto instructionSbbAccImm(Size) -> void;
auto instructionAndMemReg(Size) -> void;
auto instructionAndRegMem(Size) -> void;
auto instructionAndAccImm(Size) -> void;
auto instructionSubMemReg(Size) -> void;
auto instructionSubRegMem(Size) -> void;
auto instructionSubAccImm(Size) -> void;
auto instructionXorMemReg(Size) -> void;
auto instructionXorRegMem(Size) -> void;
auto instructionXorAccImm(Size) -> void;
auto instructionCmpMemReg(Size) -> void;
auto instructionCmpRegMem(Size) -> void;
auto instructionCmpAccImm(Size) -> void;
auto instructionTestMemReg(Size) -> void;
auto instructionTestAcc(Size) -> void;
auto instructionMultiplySignedRegMemImm(Size) -> void;
auto instructionIncReg(uint16_t&) -> void;
auto instructionDecReg(uint16_t&) -> void;
auto instructionSignExtendByte() -> void;
auto instructionSignExtendWord() -> void;
//instructions-exec.cpp
Update to v103r31 release. byuu says: Changelog: - gba/cpu: slight speedup to CPU::step() - processor/arm7tdmi: fixed about ten bugs, ST018 and GBA games are now playable once again - processor/arm: removed core from codebase - processor/v30mz: code cleanup (renamed functions; updated instruction() for consistency with other cores) It turns out on my much faster system, the new ARM7TDMI core is very slightly slower than the old one (by about 2% or so FPS.) But the CPU::step() improvement basically made it a wash. So yeah, I'm in really serious trouble with how slow my GBA core is now. Sigh. As for higan/processor ... this concludes the first phase of major cleanups and rewrites. There will always be work to do, and I have two more phases in mind. One is that a lot of the instruction disassemblers are very old. One even uses sprintf still. I'd like to modernize them all. Also, the ARM7TDMI core (and the ARM core before it) can't really disassemble because the PC address used for instruction execution is not known prior to calling instruction(), due to pipeline reload fetches that may occur inside of said function. I had a nasty hack for debugging the new core, but I'd like to come up with a clean way to allow tracing the new ARM7TDMI core. Another is that I'd still like to rename a lot of instruction function names in various cores to be more descriptive. I really liked how the LR35902 core came out there, and would like to get that level of detail in with the other cores as well.
2017-08-10 11:26:02 +00:00
auto instructionLoop() -> void;
auto instructionLoopWhile(bool) -> void;
auto instructionJumpShort() -> void;
auto instructionJumpIf(bool) -> void;
auto instructionJumpNear() -> void;
auto instructionJumpFar() -> void;
auto instructionCallNear() -> void;
auto instructionCallFar() -> void;
auto instructionReturn() -> void;
auto instructionReturnImm() -> void;
auto instructionReturnFar() -> void;
auto instructionReturnFarImm() -> void;
auto instructionReturnInt() -> void;
auto instructionInt3() -> void;
auto instructionIntImm() -> void;
auto instructionInto() -> void;
auto instructionEnter() -> void;
auto instructionLeave() -> void;
auto instructionPushReg(uint16_t&) -> void;
auto instructionPopReg(uint16_t&) -> void;
auto instructionPushFlags() -> void;
auto instructionPopFlags() -> void;
auto instructionPushAll() -> void;
auto instructionPopAll() -> void;
auto instructionPushImm(Size) -> void;
auto instructionPopMem() -> void;
//instructions-flag.cpp
Update to v103r31 release. byuu says: Changelog: - gba/cpu: slight speedup to CPU::step() - processor/arm7tdmi: fixed about ten bugs, ST018 and GBA games are now playable once again - processor/arm: removed core from codebase - processor/v30mz: code cleanup (renamed functions; updated instruction() for consistency with other cores) It turns out on my much faster system, the new ARM7TDMI core is very slightly slower than the old one (by about 2% or so FPS.) But the CPU::step() improvement basically made it a wash. So yeah, I'm in really serious trouble with how slow my GBA core is now. Sigh. As for higan/processor ... this concludes the first phase of major cleanups and rewrites. There will always be work to do, and I have two more phases in mind. One is that a lot of the instruction disassemblers are very old. One even uses sprintf still. I'd like to modernize them all. Also, the ARM7TDMI core (and the ARM core before it) can't really disassemble because the PC address used for instruction execution is not known prior to calling instruction(), due to pipeline reload fetches that may occur inside of said function. I had a nasty hack for debugging the new core, but I'd like to come up with a clean way to allow tracing the new ARM7TDMI core. Another is that I'd still like to rename a lot of instruction function names in various cores to be more descriptive. I really liked how the LR35902 core came out there, and would like to get that level of detail in with the other cores as well.
2017-08-10 11:26:02 +00:00
auto instructionStoreFlagsAcc() -> void;
auto instructionLoadAccFlags() -> void;
auto instructionComplementCarry() -> void;
auto instructionClearFlag(uint) -> void;
auto instructionSetFlag(uint) -> void;
//instructions-group.cpp
Update to v103r31 release. byuu says: Changelog: - gba/cpu: slight speedup to CPU::step() - processor/arm7tdmi: fixed about ten bugs, ST018 and GBA games are now playable once again - processor/arm: removed core from codebase - processor/v30mz: code cleanup (renamed functions; updated instruction() for consistency with other cores) It turns out on my much faster system, the new ARM7TDMI core is very slightly slower than the old one (by about 2% or so FPS.) But the CPU::step() improvement basically made it a wash. So yeah, I'm in really serious trouble with how slow my GBA core is now. Sigh. As for higan/processor ... this concludes the first phase of major cleanups and rewrites. There will always be work to do, and I have two more phases in mind. One is that a lot of the instruction disassemblers are very old. One even uses sprintf still. I'd like to modernize them all. Also, the ARM7TDMI core (and the ARM core before it) can't really disassemble because the PC address used for instruction execution is not known prior to calling instruction(), due to pipeline reload fetches that may occur inside of said function. I had a nasty hack for debugging the new core, but I'd like to come up with a clean way to allow tracing the new ARM7TDMI core. Another is that I'd still like to rename a lot of instruction function names in various cores to be more descriptive. I really liked how the LR35902 core came out there, and would like to get that level of detail in with the other cores as well.
2017-08-10 11:26:02 +00:00
auto instructionGroup1MemImm(Size, bool) -> void;
auto instructionGroup2MemImm(Size, maybe<uint8> = {}) -> void;
auto instructionGroup3MemImm(Size) -> void;
auto instructionGroup4MemImm(Size) -> void;
//instructions-misc.cpp
Update to v103r31 release. byuu says: Changelog: - gba/cpu: slight speedup to CPU::step() - processor/arm7tdmi: fixed about ten bugs, ST018 and GBA games are now playable once again - processor/arm: removed core from codebase - processor/v30mz: code cleanup (renamed functions; updated instruction() for consistency with other cores) It turns out on my much faster system, the new ARM7TDMI core is very slightly slower than the old one (by about 2% or so FPS.) But the CPU::step() improvement basically made it a wash. So yeah, I'm in really serious trouble with how slow my GBA core is now. Sigh. As for higan/processor ... this concludes the first phase of major cleanups and rewrites. There will always be work to do, and I have two more phases in mind. One is that a lot of the instruction disassemblers are very old. One even uses sprintf still. I'd like to modernize them all. Also, the ARM7TDMI core (and the ARM core before it) can't really disassemble because the PC address used for instruction execution is not known prior to calling instruction(), due to pipeline reload fetches that may occur inside of said function. I had a nasty hack for debugging the new core, but I'd like to come up with a clean way to allow tracing the new ARM7TDMI core. Another is that I'd still like to rename a lot of instruction function names in various cores to be more descriptive. I really liked how the LR35902 core came out there, and would like to get that level of detail in with the other cores as well.
2017-08-10 11:26:02 +00:00
auto instructionSegment(uint16) -> void;
auto instructionRepeat(bool) -> void;
auto instructionLock() -> void;
auto instructionWait() -> void;
auto instructionHalt() -> void;
auto instructionNop() -> void;
auto instructionIn(Size) -> void;
auto instructionOut(Size) -> void;
auto instructionInDX(Size) -> void;
auto instructionOutDX(Size) -> void;
auto instructionTranslate() -> void;
auto instructionBound() -> void;
//instructions-move.cpp
Update to v103r31 release. byuu says: Changelog: - gba/cpu: slight speedup to CPU::step() - processor/arm7tdmi: fixed about ten bugs, ST018 and GBA games are now playable once again - processor/arm: removed core from codebase - processor/v30mz: code cleanup (renamed functions; updated instruction() for consistency with other cores) It turns out on my much faster system, the new ARM7TDMI core is very slightly slower than the old one (by about 2% or so FPS.) But the CPU::step() improvement basically made it a wash. So yeah, I'm in really serious trouble with how slow my GBA core is now. Sigh. As for higan/processor ... this concludes the first phase of major cleanups and rewrites. There will always be work to do, and I have two more phases in mind. One is that a lot of the instruction disassemblers are very old. One even uses sprintf still. I'd like to modernize them all. Also, the ARM7TDMI core (and the ARM core before it) can't really disassemble because the PC address used for instruction execution is not known prior to calling instruction(), due to pipeline reload fetches that may occur inside of said function. I had a nasty hack for debugging the new core, but I'd like to come up with a clean way to allow tracing the new ARM7TDMI core. Another is that I'd still like to rename a lot of instruction function names in various cores to be more descriptive. I really liked how the LR35902 core came out there, and would like to get that level of detail in with the other cores as well.
2017-08-10 11:26:02 +00:00
auto instructionMoveMemReg(Size) -> void;
auto instructionMoveRegMem(Size) -> void;
auto instructionMoveMemSeg() -> void;
auto instructionMoveSegMem() -> void;
auto instructionMoveAccMem(Size) -> void;
auto instructionMoveMemAcc(Size) -> void;
auto instructionMoveRegImm(uint8_t&) -> void;
auto instructionMoveRegImm(uint16_t&) -> void;
auto instructionMoveMemImm(Size) -> void;
auto instructionExchange(uint16_t&, uint16_t&) -> void;
auto instructionExchangeMemReg(Size) -> void;
auto instructionLoadEffectiveAddressRegMem() -> void;
auto instructionLoadSegmentMem(uint16_t&) -> void;
//instructions-string.cpp
Update to v103r31 release. byuu says: Changelog: - gba/cpu: slight speedup to CPU::step() - processor/arm7tdmi: fixed about ten bugs, ST018 and GBA games are now playable once again - processor/arm: removed core from codebase - processor/v30mz: code cleanup (renamed functions; updated instruction() for consistency with other cores) It turns out on my much faster system, the new ARM7TDMI core is very slightly slower than the old one (by about 2% or so FPS.) But the CPU::step() improvement basically made it a wash. So yeah, I'm in really serious trouble with how slow my GBA core is now. Sigh. As for higan/processor ... this concludes the first phase of major cleanups and rewrites. There will always be work to do, and I have two more phases in mind. One is that a lot of the instruction disassemblers are very old. One even uses sprintf still. I'd like to modernize them all. Also, the ARM7TDMI core (and the ARM core before it) can't really disassemble because the PC address used for instruction execution is not known prior to calling instruction(), due to pipeline reload fetches that may occur inside of said function. I had a nasty hack for debugging the new core, but I'd like to come up with a clean way to allow tracing the new ARM7TDMI core. Another is that I'd still like to rename a lot of instruction function names in various cores to be more descriptive. I really liked how the LR35902 core came out there, and would like to get that level of detail in with the other cores as well.
2017-08-10 11:26:02 +00:00
auto instructionInString(Size) -> void;
auto instructionOutString(Size) -> void;
auto instructionMoveString(Size) -> void;
auto instructionCompareString(Size) -> void;
auto instructionStoreString(Size) -> void;
auto instructionLoadString(Size) -> void;
auto instructionScanString(Size) -> void;
Update to v097r28 release. byuu says: Changelog: (all WSC unless otherwise noted) - fixed LINECMP=0 interrupt case (fixes FF4 world map during airship sequence) - improved CPU timing (fixes Magical Drop flickering and FF1 battle music) - added per-frame OAM caching (fixes sprite glitchiness in Magical Drop, Riviera, etc.) - added RTC emulation (fixes Dicing Knight and Judgement Silversword) - added save state support - added cheat code support (untested because I don't know of any cheat codes that exist for this system) - icarus: can now detect games with RTC chips - SFC: bugfix to SharpRTC emulation (Dai Kaijuu Monogatari II) - ( I was adding the extra leap year day to all 12 months instead of just February ... >_< ) Note that the RTC emulation is very incomplete. It's not really documented at all, and the two games I've tried that use it never even ask you to set the date/time (so they're probably just using it to count seconds.) I'm not even sure if I've implement the level-sensitive behavior correctly (actually, now that I think about it, I need to mask the clear bit in INT_ACK for the level-sensitive interrupts ...) A bit worried about the RTC alarm, because it seems like it'll fire continuously for a full minute. Or even if you turn it off after it fires, then that doesn't seem to be lowering the line until the next second ticks on the RTC, so that likely needs to happen when changing the alarm flag. Also not sure on this RTC's weekday byte. On the SharpRTC, it actually computes this for you. Because it's not at all an easy thing to calculate yourself in 65816 or V30MZ assembler. About 40 lines of code to do it in C. For now, I'm requiring the program to calculate the value itself. Also note that there's some gibberish tiles in Judgement Silversword, sadly. Not sure what's up there, but the game's still fully playable at least. Finally, no surprise: Beat-Mania doesn't run :P
2016-03-25 06:19:08 +00:00
//serialization.cpp
auto serialize(serializer&) -> void;
//disassembler.cpp
auto disassemble(uint16 cs, uint16 ip, bool registers = true, bool bytes = true) -> string;
struct State {
bool halt; //set to true for hlt instruction; blocks execution until next interrupt
bool poll; //set to false to suppress interrupt polling between CPU instructions
bool prefix; //set to true for prefix instructions; prevents flushing of Prefix struct
} state;
Update to v097r24 release. byuu says: Changelog: - WS: fixed bug when IRQs triggered during a rep string instruction - WS: added sprite attribute caching (per-scanline); absolutely massive speed-up - WS: emulated limit of 32 sprites per scanline - WS: emulated the extended PPU register bit behavior based on the DISP_CTRL tile bit-depth setting - WS: added "Rotate" key binding; can be used to flip the WS display between horizontal and vertical in real-time The prefix emulation may not be 100% hardware-accurate, but the edge cases should be extreme enough to not come up in the WS library. No way to get the emulation 100% down without intensive hardware testing. trap15 pointed me at a workflow diagram for it, but that diagram is impossible without a magic internal stack frame that grows with every IRQ, and can thus grow infinitely large. The rotation thing isn't exactly the most friendly set-up, but oh well. I'll see about adding a default rotation setting to manifests, so that games like GunPey can start in the correct orientation. After that, if the LCD orientation icon turns out to be reliable, then I'll start using that. But if there are cases where it's not reliable, then I'll leave it to manual button presses. Speaking of icons, I'll need a set of icons to render on the screen. Going to put them to the top right on vertical orientation, and on the bottom left for horizontal orientation. Just outside of the video output, of course. Overall, WS is getting pretty far along, but still some major bugs in various games. I really need sound emulation, though. Nobody's going to use this at all without that.
2016-03-12 13:27:41 +00:00
uint8 opcode;
vector<uint8> prefixes;
struct ModRM {
uint2 mod;
uint3 reg;
uint3 mem;
uint16 segment;
uint16 address;
} modrm;
struct Registers {
union { uint16_t ax; struct { uint8_t order_lsb2(al, ah); }; };
union { uint16_t cx; struct { uint8_t order_lsb2(cl, ch); }; };
union { uint16_t dx; struct { uint8_t order_lsb2(dl, dh); }; };
union { uint16_t bx; struct { uint8_t order_lsb2(bl, bh); }; };
uint16_t sp;
uint16_t bp;
uint16_t si;
uint16_t di;
uint16_t es;
uint16_t cs;
uint16_t ss;
uint16_t ds;
uint16_t ip;
uint8_t* b[8]{&al, &cl, &dl, &bl, &ah, &ch, &dh, &bh};
uint16_t* w[8]{&ax, &cx, &dx, &bx, &sp, &bp, &si, &di};
uint16_t* s[8]{&es, &cs, &ss, &ds, &es, &cs, &ss, &ds};
struct Flags {
Update to v098r19 release. byuu says: Changelog: - added nall/bit-field.hpp - updated all CPU cores (sans LR35902 due to some complexities) to use BitFields instead of bools - updated as many CPU cores as I could to use BitFields instead of union { struct { uint8_t ... }; }; pairs The speed changes are mostly a wash for this. In some instances, I noticed a ~2-3% speedup (eg SNES emulation), and in others a 2-3% slowdown (eg Famicom emulation.) It's within the margin of error, so it's safe to say it has no impact. This does give us a lot of new useful things, however: - no more manual reconstruction of flag values from lots of left shifts and ORs - no more manual deconstruction of flag values from lots of ANDs - ability to get completely free aliases to flag groups (eg GSU can provide alt2, alt1 and also alt (which is alt2,alt1 combined) - removes the need for the nasty order_lsbN macro hack (eventually will make higan 100% endian independent) - saves us from insane compilers that try and do nasty things with alignment on union-structs - saves us from insane compilers that try to store bit-field bits in reverse order - will allow some really novel new use cases (I'm planning an instant-decode ARM opcode function, for instance.) - reduces code size (we can serialize flag registers in one line instead of one for each flag) However, I probably won't use it for super critical code that's constantly reading out register values (eg PPU MMIO registers.) I think there we would end up with a performance penalty.
2016-06-08 22:26:35 +00:00
union {
uint16_t data = 0;
BooleanBitField<uint16_t, 15> m; //mode
BooleanBitField<uint16_t, 11> v; //overflow
BooleanBitField<uint16_t, 10> d; //direction
BooleanBitField<uint16_t, 9> i; //interrupt
BooleanBitField<uint16_t, 8> b; //break
BooleanBitField<uint16_t, 7> s; //sign
BooleanBitField<uint16_t, 6> z; //zero
BooleanBitField<uint16_t, 4> h; //half-carry
BooleanBitField<uint16_t, 2> p; //parity
BooleanBitField<uint16_t, 0> c; //carry
Update to v098r19 release. byuu says: Changelog: - added nall/bit-field.hpp - updated all CPU cores (sans LR35902 due to some complexities) to use BitFields instead of bools - updated as many CPU cores as I could to use BitFields instead of union { struct { uint8_t ... }; }; pairs The speed changes are mostly a wash for this. In some instances, I noticed a ~2-3% speedup (eg SNES emulation), and in others a 2-3% slowdown (eg Famicom emulation.) It's within the margin of error, so it's safe to say it has no impact. This does give us a lot of new useful things, however: - no more manual reconstruction of flag values from lots of left shifts and ORs - no more manual deconstruction of flag values from lots of ANDs - ability to get completely free aliases to flag groups (eg GSU can provide alt2, alt1 and also alt (which is alt2,alt1 combined) - removes the need for the nasty order_lsbN macro hack (eventually will make higan 100% endian independent) - saves us from insane compilers that try and do nasty things with alignment on union-structs - saves us from insane compilers that try to store bit-field bits in reverse order - will allow some really novel new use cases (I'm planning an instant-decode ARM opcode function, for instance.) - reduces code size (we can serialize flag registers in one line instead of one for each flag) However, I probably won't use it for super critical code that's constantly reading out register values (eg PPU MMIO registers.) I think there we would end up with a performance penalty.
2016-06-08 22:26:35 +00:00
};
operator uint() const { return data & 0x8fd5 | 0x7002; }
auto& operator =(uint value) { return data = value, *this; }
auto& operator&=(uint value) { return data &= value, *this; }
auto& operator|=(uint value) { return data |= value, *this; }
auto& operator^=(uint value) { return data ^= value, *this; }
} f;
} r;
};
}