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bsnes/sfc/ppu/mmio/mmio.hpp

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Update to v074r06 release. byuu says: This WIP uses the 16MB+64MB memory tables for 1:1 mapping of the S-CPU bus. Minimum RAM requirement goes up to 128MB, dare I be bold here and recommend you have 256MB. I also hooked up the basic bindings for making pseudo-fullscreen windows in phoenix/Windows and phoenix/GTK+, but both have some serious issues. - GTK+ won't resize my form container, even though it's the same code I used successfully in bsnes v039 and prior with hiro - Windows scale selection breaks the faux-fullscreen effects - I am intending to write off the menu/status bars and just auto-size the video to fill the screen, nice and simple
2011-01-18 10:17:48 +00:00
public:
uint8 mmio_read(unsigned addr);
void mmio_write(unsigned addr, uint8 data);
Update to v092r09 release. byuu says: This will be another massive diff from the previous version. All of higan was updated to use the new foo& bar syntax, and I also updated switch statements to be consistent as well (but not in the disassemblers, was starting to get an RSI just from what I already did.) phoenix/{windows, cocoa, qt} need to be updated to use "string foo" instead of "const string& foo", and after that, the major diffs should be finished. This archive is the first time I'm posting my copy-on-write, size+capacity nall::string class, so any feedback on that is welcome as well.
2013-05-05 09:21:30 +00:00
privileged:
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
struct {
uint8 ppu1_mdr;
uint8 ppu2_mdr;
uint16 vram_readbuffer;
uint8 oam_latchdata;
uint8 cgram_latchdata;
uint8 bgofs_latchdata;
uint8 mode7_latchdata;
bool counters_latched;
bool latch_hcounter;
bool latch_vcounter;
Update to v068r24 release. (there was no r23 release posted to the WIP thread) byuu says: Fixes OAM latchdata for all 3 cores and CGRAM address invalidation for the accuracy core (the only one that really does it because it needs cycle PPU timing.) Also removes the OAM/CGRAM read/write functions to put them inside the actual MMIO functions. Easier to handle all the special cases that way. VRAM is a bit more annoying since there's two read and two write functions. This should fix battletech/mechwarrior 3050 palette at least.
2010-09-24 13:15:21 +00:00
uint10 oam_iaddr;
uint9 cgram_iaddr;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
//$2100 INIDISP
Update to v068r12 release. (there was no r11 release posted to the WIP thread) byuu says: This took ten hours of mind boggling insanity to pull off. It upgrades the S-PPU dot-based renderer to fetch one tile, and then output all of its pixels before fetching again. It sounds easy enough, but it's insanely difficult. I ended up taking one small shortcut, in that rather than fetch at -7, I fetch at the first instance where a tile is needed to plot to x=0. So if you have {-3 to +4 } as a tile, it fetches at -3. That won't work so well on hardware, if two BGs fetch at the same X offset, they won't have time. I have had no luck staggering the reads at BG1=-7, BG3=-5, etc. While I can shift and fetch just fine, what happens is that when a new tile is fetched in, that gives a new palette, priority, etc; and this ends up happening between two tiles which results in the right-most edges of the screen ending up with the wrong colors and such. Offset-per-tile is cheap as always. Although looking at it, I'm not sure how BG3 could pre-fetch, especially with the way one or two OPT modes can fetch two tiles. There's no magic in Hoffset caching yet, so the SMW1 pixel issue is still there. Mode 7 got a bugfix, it was off-by-one horizontally from the mosaic code. After re-designing the BG mosaic, I ended up needing a separate mosaic for Mode7, and in the process I fixed that bug. The obvious change is that the Chrono Trigger Mode7->Mode2 transition doesn't cause the pendulum to jump anymore. Windows were simplified just a tad. The range testing is shared for all modes now. Ironically, it's a bit slower, but I'll take less code over more speed for the accuracy core. Speaking of speed, because there's so much less calculations per pixel for BGs, performance for the entire emulator has gone up by 30% in the accuracy core. Pretty neat overall, I can maintain 60fps in all but, yeah you can guess can't you?
2010-09-04 03:36:03 +00:00
bool display_disable;
Update to v077r05 release. byuu says: Changelog: - fixed .nec and both .rtc file extensions (thanks krom) - randomized most S-PPU registers, should trip up some broken homebrew that does not initialize all registers - randomization is now seeded with time(0) rather than 'byuu' - SNES::interface.video_refresh() now always receives {256,512}x{240,480} - PPU/accuracy scanline 0 does not render the screen back color anymore, fixes strange coloring look on first scanline in PAL TV mode in non-overscan games - disabled hires blending in PPU/compatibility; all three cores act the same now
2011-04-27 08:57:31 +00:00
uint4 display_brightness;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
//$2102 OAMADDL
//$2103 OAMADDH
Update to v068r24 release. (there was no r23 release posted to the WIP thread) byuu says: Fixes OAM latchdata for all 3 cores and CGRAM address invalidation for the accuracy core (the only one that really does it because it needs cycle PPU timing.) Also removes the OAM/CGRAM read/write functions to put them inside the actual MMIO functions. Easier to handle all the special cases that way. VRAM is a bit more annoying since there's two read and two write functions. This should fix battletech/mechwarrior 3050 palette at least.
2010-09-24 13:15:21 +00:00
uint10 oam_baseaddr;
uint10 oam_addr;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
bool oam_priority;
//$2105 BGMODE
bool bg3_priority;
uint8 bgmode;
//$210d BG1HOFS
uint16 mode7_hoffset;
//$210e BG1VOFS
uint16 mode7_voffset;
//$2115 VMAIN
bool vram_incmode;
Update to v077r05 release. byuu says: Changelog: - fixed .nec and both .rtc file extensions (thanks krom) - randomized most S-PPU registers, should trip up some broken homebrew that does not initialize all registers - randomization is now seeded with time(0) rather than 'byuu' - SNES::interface.video_refresh() now always receives {256,512}x{240,480} - PPU/accuracy scanline 0 does not render the screen back color anymore, fixes strange coloring look on first scanline in PAL TV mode in non-overscan games - disabled hires blending in PPU/compatibility; all three cores act the same now
2011-04-27 08:57:31 +00:00
uint2 vram_mapping;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
uint8 vram_incsize;
//$2116 VMADDL
//$2117 VMADDH
uint16 vram_addr;
//$211a M7SEL
Update to v077r05 release. byuu says: Changelog: - fixed .nec and both .rtc file extensions (thanks krom) - randomized most S-PPU registers, should trip up some broken homebrew that does not initialize all registers - randomization is now seeded with time(0) rather than 'byuu' - SNES::interface.video_refresh() now always receives {256,512}x{240,480} - PPU/accuracy scanline 0 does not render the screen back color anymore, fixes strange coloring look on first scanline in PAL TV mode in non-overscan games - disabled hires blending in PPU/compatibility; all three cores act the same now
2011-04-27 08:57:31 +00:00
uint2 mode7_repeat;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
bool mode7_vflip;
bool mode7_hflip;
//$211b M7A
uint16 m7a;
//$211c M7B
uint16 m7b;
//$211d M7C
uint16 m7c;
//$211e M7D
uint16 m7d;
//$211f M7X
uint16 m7x;
//$2120 M7Y
uint16 m7y;
//$2121 CGADD
Update to v068r24 release. (there was no r23 release posted to the WIP thread) byuu says: Fixes OAM latchdata for all 3 cores and CGRAM address invalidation for the accuracy core (the only one that really does it because it needs cycle PPU timing.) Also removes the OAM/CGRAM read/write functions to put them inside the actual MMIO functions. Easier to handle all the special cases that way. VRAM is a bit more annoying since there's two read and two write functions. This should fix battletech/mechwarrior 3050 palette at least.
2010-09-24 13:15:21 +00:00
uint9 cgram_addr;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
//$2133 SETINI
bool mode7_extbg;
bool pseudo_hires;
bool overscan;
bool interlace;
//$213c OPHCT
uint16 hcounter;
//$213d OPVCT
uint16 vcounter;
} regs;
Update to v094r17 release. byuu says: This updates higan to use the new Markup::Node changes. This is a really big change, and one slight typo anywhere could break certain classes of games from playing. I don't have ananke hooked up again yet, so I don't have the ability to test this much. If anyone with some v094 game folders wouldn't mind testing, I'd help out a great deal. I'm most concerned about testing one of each SNES special chip game. Most notably, systems like the SA-1, HitachiDSP and NEC-DSP were using the fancier lookups, eg node["rom[0]/name"], which I had to convert to a rather ugly node["rom"].at(0)["name"], which I'm fairly confident won't work. I'm going to blame that on the fumes from the shelves I just stained >.> Might work with node.find("rom[0]/name")(0) though ...? But so ugly ... ugh. That aside, this WIP adds the accuracy-PPU inlining, so the accuracy profile should run around 7.5% faster than before.
2015-05-02 13:05:46 +00:00
alwaysinline uint16 get_vram_address();
alwaysinline uint8 vram_read(unsigned addr);
alwaysinline void vram_write(unsigned addr, uint8 data);
alwaysinline uint8 oam_read(unsigned addr);
alwaysinline void oam_write(unsigned addr, uint8 data);
alwaysinline uint8 cgram_read(unsigned addr);
alwaysinline void cgram_write(unsigned addr, uint8 data);
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
void mmio_update_video_mode();
void mmio_w2100(uint8); //INIDISP
void mmio_w2101(uint8); //OBSEL
void mmio_w2102(uint8); //OAMADDL
void mmio_w2103(uint8); //OAMADDH
void mmio_w2104(uint8); //OAMDATA
void mmio_w2105(uint8); //BGMODE
void mmio_w2106(uint8); //MOSAIC
void mmio_w2107(uint8); //BG1SC
void mmio_w2108(uint8); //BG2SC
void mmio_w2109(uint8); //BG3SC
void mmio_w210a(uint8); //BG4SC
void mmio_w210b(uint8); //BG12NBA
void mmio_w210c(uint8); //BG34NBA
void mmio_w210d(uint8); //BG1HOFS
void mmio_w210e(uint8); //BG1VOFS
void mmio_w210f(uint8); //BG2HOFS
void mmio_w2110(uint8); //BG2VOFS
void mmio_w2111(uint8); //BG3HOFS
void mmio_w2112(uint8); //BG3VOFS
void mmio_w2113(uint8); //BG4HOFS
void mmio_w2114(uint8); //BG4VOFS
void mmio_w2115(uint8); //VMAIN
void mmio_w2116(uint8); //VMADDL
void mmio_w2117(uint8); //VMADDH
void mmio_w2118(uint8); //VMDATAL
void mmio_w2119(uint8); //VMDATAH
void mmio_w211a(uint8); //M7SEL
void mmio_w211b(uint8); //M7A
void mmio_w211c(uint8); //M7B
void mmio_w211d(uint8); //M7C
void mmio_w211e(uint8); //M7D
void mmio_w211f(uint8); //M7X
void mmio_w2120(uint8); //M7Y
void mmio_w2121(uint8); //CGADD
void mmio_w2122(uint8); //CGDATA
void mmio_w2123(uint8); //W12SEL
void mmio_w2124(uint8); //W34SEL
void mmio_w2125(uint8); //WOBJSEL
void mmio_w2126(uint8); //WH0
void mmio_w2127(uint8); //WH1
void mmio_w2128(uint8); //WH2
void mmio_w2129(uint8); //WH3
void mmio_w212a(uint8); //WBGLOG
void mmio_w212b(uint8); //WOBJLOG
void mmio_w212c(uint8); //TM
void mmio_w212d(uint8); //TS
void mmio_w212e(uint8); //TMW
void mmio_w212f(uint8); //TSW
void mmio_w2130(uint8); //CGWSEL
void mmio_w2131(uint8); //CGADDSUB
void mmio_w2132(uint8); //COLDATA
void mmio_w2133(uint8); //SETINI
uint8 mmio_r2134(); //MPYL
uint8 mmio_r2135(); //MPYM
uint8 mmio_r2136(); //MPYH
uint8 mmio_r2137(); //SLHV
uint8 mmio_r2138(); //OAMDATAREAD
uint8 mmio_r2139(); //VMDATALREAD
uint8 mmio_r213a(); //VMDATAHREAD
uint8 mmio_r213b(); //CGDATAREAD
uint8 mmio_r213c(); //OPHCT
uint8 mmio_r213d(); //OPVCT
uint8 mmio_r213e(); //STAT77
uint8 mmio_r213f(); //STAT78
void mmio_reset();