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bsnes/higan/processor/lr35902/instruction.cpp

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Update to v102r27 release. byuu says: Changelog: - processor/gsu: minor code cleanup - processor/hg51b: renamed reg(Read,Write) to register(Read,Write) - processor/lr35902: minor code cleanup - processor/spc700: completed code cleanup (sans disassembler) - no longer uses internal global state inside instructions - processor/spc700: will no longer hang the emulator if stuck in a WAI (SLEEP) or STP (STOP) instruction - processor/spc700: fixed bug in handling of OR1 and AND1 instructions - processor/z80: minor code cleanup - sfc/dsp: revert to initializing registers to 0x00; save for ENDX=random(), FLG=0xe0 [Jonas Quinn] Major testing of the SNES game library would be appreciated, now that its CPU cores have all been revised. We know the DSP registers read back as randomized data ... mostly, but there are apparently internal latches, which we can't emulate with the current DSP design. So until we know which registers have separate internal state that actually *is* initialized, I'm going to play it safe and not break more games. Thanks again to Jonas Quinn for the continued research into this issue. EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance that the game will work. That seems pretty unlikely that the odds of it working are that low, given hardware testing by others in the past :/ I thought if worked if `PITCH != 0` before, which would have been way more likely. The two remaining CPU cores that need major cleanup efforts are the LR35902 and ARM cores. Both are very large, complicated, annoying cores that will probably be better off as full rewrites from scratch. I don't think I want to delay v103 in trying to accomplish that, however. So I think it'll be best to focus on allowing the Mega Drive core to not lock when processors are frozen waiting on a response from other processors during a save state operation. Then we should be good for a new release.
2017-06-19 02:07:54 +00:00
auto LR35902::interrupt(uint16 vector) -> void {
}
Update to v103r25 release. byuu says: Changelog: - gb/cpu: force STAT mode to 0 when LCD is disabled (fixes Pokemon Pinball, etc) - gb/ppu: when LCD is disabled, require at least one-frame wait to re-enable, display white during this time - todo: should step by a scanline at a time: worst-case is an extra 99% of a frame to enable again - gba/ppu: cache tilemap lookups and attribute parsing - it's more accurate because the GBA wouldn't read this for every pixel - but unfortunately, this didn't provide any speedup at all ... sigh - ruby/audio/alsa: fixed const issue with free() - ruby/video/cgl: removed `glDisable(GL_ALPHA_TEST)` [deprecated] - ruby/video/cgl: removed `glEnable(GL_TEXTURE_2D)` [unnecessary as we use shaders] - processor/lr35902: started rewrite¹ ¹: so, the Game Boy and Game Boy Color cores will be completely broken for at least the next two or three WIPs. The old LR35902 was complete garbage, written in early 2011. So I'm rewriting it to provide a massive cleanup and consistency with other processor cores, especially the Z80 core. I've got about 85% of the main instructions implemented, and then I have to do the CB instructions. The CB instructions are easier because they're mostly just a small number of opcodes in many small variations, but it'll still be tedious.
2017-08-04 12:53:59 +00:00
#define op(id, name, ...) case id: return instruction##name(__VA_ARGS__);
Update to v102r27 release. byuu says: Changelog: - processor/gsu: minor code cleanup - processor/hg51b: renamed reg(Read,Write) to register(Read,Write) - processor/lr35902: minor code cleanup - processor/spc700: completed code cleanup (sans disassembler) - no longer uses internal global state inside instructions - processor/spc700: will no longer hang the emulator if stuck in a WAI (SLEEP) or STP (STOP) instruction - processor/spc700: fixed bug in handling of OR1 and AND1 instructions - processor/z80: minor code cleanup - sfc/dsp: revert to initializing registers to 0x00; save for ENDX=random(), FLG=0xe0 [Jonas Quinn] Major testing of the SNES game library would be appreciated, now that its CPU cores have all been revised. We know the DSP registers read back as randomized data ... mostly, but there are apparently internal latches, which we can't emulate with the current DSP design. So until we know which registers have separate internal state that actually *is* initialized, I'm going to play it safe and not break more games. Thanks again to Jonas Quinn for the continued research into this issue. EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance that the game will work. That seems pretty unlikely that the odds of it working are that low, given hardware testing by others in the past :/ I thought if worked if `PITCH != 0` before, which would have been way more likely. The two remaining CPU cores that need major cleanup efforts are the LR35902 and ARM cores. Both are very large, complicated, annoying cores that will probably be better off as full rewrites from scratch. I don't think I want to delay v103 in trying to accomplish that, however. So I think it'll be best to focus on allowing the Mega Drive core to not lock when processors are frozen waiting on a response from other processors during a save state operation. Then we should be good for a new release.
2017-06-19 02:07:54 +00:00
auto LR35902::instruction() -> void {
Update to v103r25 release. byuu says: Changelog: - gb/cpu: force STAT mode to 0 when LCD is disabled (fixes Pokemon Pinball, etc) - gb/ppu: when LCD is disabled, require at least one-frame wait to re-enable, display white during this time - todo: should step by a scanline at a time: worst-case is an extra 99% of a frame to enable again - gba/ppu: cache tilemap lookups and attribute parsing - it's more accurate because the GBA wouldn't read this for every pixel - but unfortunately, this didn't provide any speedup at all ... sigh - ruby/audio/alsa: fixed const issue with free() - ruby/video/cgl: removed `glDisable(GL_ALPHA_TEST)` [deprecated] - ruby/video/cgl: removed `glEnable(GL_TEXTURE_2D)` [unnecessary as we use shaders] - processor/lr35902: started rewrite¹ ¹: so, the Game Boy and Game Boy Color cores will be completely broken for at least the next two or three WIPs. The old LR35902 was complete garbage, written in early 2011. So I'm rewriting it to provide a massive cleanup and consistency with other processor cores, especially the Z80 core. I've got about 85% of the main instructions implemented, and then I have to do the CB instructions. The CB instructions are easier because they're mostly just a small number of opcodes in many small variations, but it'll still be tedious.
2017-08-04 12:53:59 +00:00
switch(auto opcode = operand()) {
op(0x00, NOP)
op(0x01, LD_Direct_Data, BC)
op(0x02, LD_Indirect_Direct, BC, A)
op(0x03, INC_Direct, BC)
op(0x04, INC_Direct, B)
op(0x05, DEC_Direct, B)
op(0x06, LD_Direct_Data, B)
op(0x07, RLC_Direct, A)
op(0x08, LD_Address_Direct, SP)
op(0x09, ADD_Direct_Direct, HL, BC)
op(0x0a, LD_Direct_Indirect, A, BC)
op(0x0b, DEC_Direct, BC)
op(0x0c, INC_Direct, C)
op(0x0d, DEC_Direct, C)
op(0x0e, LD_Direct_Data, C)
op(0x0f, RRC_Direct, A)
op(0x10, STOP)
op(0x11, LD_Direct_Data, DE)
op(0x12, LD_Indirect_Direct, DE, A)
op(0x13, INC_Direct, DE)
op(0x14, INC_Direct, D)
op(0x15, DEC_Direct, D)
op(0x16, LD_Direct_Data, D)
op(0x17, RL_Direct, A)
op(0x18, JR_Condition_Relative, 1)
op(0x19, ADD_Direct_Direct, HL, DE)
op(0x1a, LD_Direct_Indirect, A, DE)
op(0x1b, DEC_Direct, DE)
op(0x1c, INC_Direct, E)
op(0x1d, DEC_Direct, E)
op(0x1e, LD_Direct_Data, E)
op(0x1f, RR_Direct, A)
op(0x20, JR_Condition_Relative, ZF == 0)
op(0x21, LD_Direct_Data, HL)
op(0x22, LD_IndirectIncrement_Direct, HL, A)
op(0x23, INC_Direct, HL)
op(0x24, INC_Direct, H)
op(0x25, DEC_Direct, H)
op(0x26, LD_Direct_Data, H)
op(0x27, DAA)
op(0x28, JR_Condition_Relative, ZF == 1)
op(0x29, ADD_Direct_Direct, HL, HL)
op(0x2a, LD_Direct_IndirectIncrement, A, HL)
op(0x2b, DEC_Direct, HL)
op(0x2c, INC_Direct, L)
op(0x2d, DEC_Direct, L)
op(0x2e, LD_Direct_Data, L)
op(0x2f, CPL)
op(0x30, JR_Condition_Relative, CF == 0)
op(0x31, LD_Direct_Data, SP)
op(0x32, LD_IndirectDecrement_Direct, HL, A)
op(0x33, INC_Direct, SP)
op(0x34, INC_Indirect, HL)
op(0x35, DEC_Indirect, HL)
op(0x36, LD_Indirect_Data, HL)
op(0x37, SCF)
op(0x38, JR_Condition_Relative, CF == 1)
op(0x39, ADD_Direct_Direct, HL, SP)
op(0x3a, LD_Direct_IndirectDecrement, A, HL)
op(0x3b, DEC_Direct, SP)
op(0x3c, INC_Direct, A)
op(0x3d, DEC_Direct, A)
op(0x3e, LD_Direct_Data, A)
op(0x3f, CCF)
op(0x40, LD_Direct_Direct, B, B)
op(0x41, LD_Direct_Direct, B, C)
op(0x42, LD_Direct_Direct, B, D)
op(0x43, LD_Direct_Direct, B, E)
op(0x44, LD_Direct_Direct, B, H)
op(0x45, LD_Direct_Direct, B, L)
op(0x46, LD_Direct_Indirect, B, HL)
op(0x47, LD_Direct_Direct, B, A)
op(0x48, LD_Direct_Direct, C, B)
op(0x49, LD_Direct_Direct, C, C)
op(0x4a, LD_Direct_Direct, C, D)
op(0x4b, LD_Direct_Direct, C, E)
op(0x4c, LD_Direct_Direct, C, H)
op(0x4d, LD_Direct_Direct, C, L)
op(0x4e, LD_Direct_Indirect, C, HL)
op(0x4f, LD_Direct_Direct, C, A)
op(0x50, LD_Direct_Direct, D, B)
op(0x51, LD_Direct_Direct, D, C)
op(0x52, LD_Direct_Direct, D, D)
op(0x53, LD_Direct_Direct, D, E)
op(0x54, LD_Direct_Direct, D, H)
op(0x55, LD_Direct_Direct, D, L)
op(0x56, LD_Direct_Indirect, D, HL)
op(0x57, LD_Direct_Direct, D, A)
op(0x58, LD_Direct_Direct, E, B)
op(0x59, LD_Direct_Direct, E, C)
op(0x5a, LD_Direct_Direct, E, D)
op(0x5b, LD_Direct_Direct, E, E)
op(0x5c, LD_Direct_Direct, E, H)
op(0x5d, LD_Direct_Direct, E, L)
op(0x5e, LD_Direct_Indirect, E, HL)
op(0x5f, LD_Direct_Direct, E, A)
op(0x60, LD_Direct_Direct, H, B)
op(0x61, LD_Direct_Direct, H, C)
op(0x62, LD_Direct_Direct, H, D)
op(0x63, LD_Direct_Direct, H, E)
op(0x64, LD_Direct_Direct, H, H)
op(0x65, LD_Direct_Direct, H, L)
op(0x66, LD_Direct_Indirect, H, HL)
op(0x67, LD_Direct_Direct, H, A)
op(0x68, LD_Direct_Direct, L, B)
op(0x69, LD_Direct_Direct, L, C)
op(0x6a, LD_Direct_Direct, L, D)
op(0x6b, LD_Direct_Direct, L, E)
op(0x6c, LD_Direct_Direct, L, H)
op(0x6d, LD_Direct_Direct, L, L)
op(0x6e, LD_Direct_Indirect, L, HL)
op(0x6f, LD_Direct_Direct, L, A)
op(0x70, LD_Indirect_Direct, HL, B)
op(0x71, LD_Indirect_Direct, HL, C)
op(0x72, LD_Indirect_Direct, HL, D)
op(0x73, LD_Indirect_Direct, HL, E)
op(0x74, LD_Indirect_Direct, HL, H)
op(0x75, LD_Indirect_Direct, HL, L)
op(0x76, HALT)
op(0x77, LD_Indirect_Direct, HL, A)
op(0x78, LD_Direct_Direct, A, B)
op(0x79, LD_Direct_Direct, A, C)
op(0x7a, LD_Direct_Direct, A, D)
op(0x7b, LD_Direct_Direct, A, E)
op(0x7c, LD_Direct_Direct, A, H)
op(0x7d, LD_Direct_Direct, A, L)
op(0x7e, LD_Direct_Indirect, A, HL)
op(0x7f, LD_Direct_Direct, A, A)
op(0x80, ADD_Direct_Direct, A, B)
op(0x81, ADD_Direct_Direct, A, C)
op(0x82, ADD_Direct_Direct, A, D)
op(0x83, ADD_Direct_Direct, A, E)
op(0x84, ADD_Direct_Direct, A, H)
op(0x85, ADD_Direct_Direct, A, L)
op(0x86, ADD_Direct_Indirect, A, HL)
op(0x87, ADD_Direct_Direct, A, A)
op(0x88, ADC_Direct_Direct, A, B)
op(0x89, ADC_Direct_Direct, A, C)
op(0x8a, ADC_Direct_Direct, A, D)
op(0x8b, ADC_Direct_Direct, A, E)
op(0x8c, ADC_Direct_Direct, A, H)
op(0x8d, ADC_Direct_Direct, A, L)
op(0x8e, ADC_Direct_Indirect, A, HL)
op(0x8f, ADC_Direct_Direct, A, A)
op(0x90, SUB_Direct_Direct, A, B)
op(0x91, SUB_Direct_Direct, A, C)
op(0x92, SUB_Direct_Direct, A, D)
op(0x93, SUB_Direct_Direct, A, E)
op(0x94, SUB_Direct_Direct, A, H)
op(0x95, SUB_Direct_Direct, A, L)
op(0x96, SUB_Direct_Indirect, A, HL)
op(0x97, SUB_Direct_Direct, A, A)
op(0x98, SBC_Direct_Direct, A, B)
op(0x99, SBC_Direct_Direct, A, C)
op(0x9a, SBC_Direct_Direct, A, D)
op(0x9b, SBC_Direct_Direct, A, E)
op(0x9c, SBC_Direct_Direct, A, H)
op(0x9d, SBC_Direct_Direct, A, L)
op(0x9e, SBC_Direct_Indirect, A, HL)
op(0x9f, SBC_Direct_Direct, A, A)
op(0xa0, AND_Direct_Direct, A, B)
op(0xa1, AND_Direct_Direct, A, C)
op(0xa2, AND_Direct_Direct, A, D)
op(0xa3, AND_Direct_Direct, A, E)
op(0xa4, AND_Direct_Direct, A, H)
op(0xa5, AND_Direct_Direct, A, L)
op(0xa6, AND_Direct_Indirect, A, HL)
op(0xa7, AND_Direct_Direct, A, A)
op(0xa8, XOR_Direct_Direct, A, B)
op(0xa9, XOR_Direct_Direct, A, C)
op(0xaa, XOR_Direct_Direct, A, D)
op(0xab, XOR_Direct_Direct, A, E)
op(0xac, XOR_Direct_Direct, A, H)
op(0xad, XOR_Direct_Direct, A, L)
op(0xae, XOR_Direct_Indirect, A, HL)
op(0xaf, XOR_Direct_Direct, A, A)
op(0xb0, OR_Direct_Direct, A, B)
op(0xb1, OR_Direct_Direct, A, C)
op(0xb2, OR_Direct_Direct, A, D)
op(0xb3, OR_Direct_Direct, A, E)
op(0xb4, OR_Direct_Direct, A, H)
op(0xb5, OR_Direct_Direct, A, L)
op(0xb6, OR_Direct_Indirect, A, HL)
op(0xb7, OR_Direct_Direct, A, A)
op(0xb8, CP_Direct_Direct, A, B)
op(0xb9, CP_Direct_Direct, A, C)
op(0xba, CP_Direct_Direct, A, D)
op(0xbb, CP_Direct_Direct, A, E)
op(0xbc, CP_Direct_Direct, A, H)
op(0xbd, CP_Direct_Direct, A, L)
op(0xbe, CP_Direct_Indirect, A, HL)
op(0xbf, CP_Direct_Direct, A, A)
op(0xc0, RET_Condition, ZF == 0)
op(0xc6, ADD_Direct_Data, A)
op(0xc8, RET_Condition, ZF == 1)
op(0xcb, CB)
op(0xce, ADC_Direct_Data, A)
op(0xd0, RET_Condition, CF == 0)
op(0xd6, SUB_Direct_Data, A)
op(0xd8, RET_Condition, CF == 1)
op(0xde, SBC_Direct_Data, A)
op(0xe2, LD_Indirect_Direct, C, A)
op(0xe6, AND_Direct_Data, A)
op(0xee, XOR_Direct_Data, A)
op(0xf2, LD_Direct_Indirect, A, C)
op(0xf3, DI)
op(0xf6, OR_Direct_Data, A)
op(0xfb, EI)
op(0xfe, CP_Direct_Data, A)
Update to v102r27 release. byuu says: Changelog: - processor/gsu: minor code cleanup - processor/hg51b: renamed reg(Read,Write) to register(Read,Write) - processor/lr35902: minor code cleanup - processor/spc700: completed code cleanup (sans disassembler) - no longer uses internal global state inside instructions - processor/spc700: will no longer hang the emulator if stuck in a WAI (SLEEP) or STP (STOP) instruction - processor/spc700: fixed bug in handling of OR1 and AND1 instructions - processor/z80: minor code cleanup - sfc/dsp: revert to initializing registers to 0x00; save for ENDX=random(), FLG=0xe0 [Jonas Quinn] Major testing of the SNES game library would be appreciated, now that its CPU cores have all been revised. We know the DSP registers read back as randomized data ... mostly, but there are apparently internal latches, which we can't emulate with the current DSP design. So until we know which registers have separate internal state that actually *is* initialized, I'm going to play it safe and not break more games. Thanks again to Jonas Quinn for the continued research into this issue. EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance that the game will work. That seems pretty unlikely that the odds of it working are that low, given hardware testing by others in the past :/ I thought if worked if `PITCH != 0` before, which would have been way more likely. The two remaining CPU cores that need major cleanup efforts are the LR35902 and ARM cores. Both are very large, complicated, annoying cores that will probably be better off as full rewrites from scratch. I don't think I want to delay v103 in trying to accomplish that, however. So I think it'll be best to focus on allowing the Mega Drive core to not lock when processors are frozen waiting on a response from other processors during a save state operation. Then we should be good for a new release.
2017-06-19 02:07:54 +00:00
}
}
auto LR35902::instructionCB() -> void {
Update to v103r25 release. byuu says: Changelog: - gb/cpu: force STAT mode to 0 when LCD is disabled (fixes Pokemon Pinball, etc) - gb/ppu: when LCD is disabled, require at least one-frame wait to re-enable, display white during this time - todo: should step by a scanline at a time: worst-case is an extra 99% of a frame to enable again - gba/ppu: cache tilemap lookups and attribute parsing - it's more accurate because the GBA wouldn't read this for every pixel - but unfortunately, this didn't provide any speedup at all ... sigh - ruby/audio/alsa: fixed const issue with free() - ruby/video/cgl: removed `glDisable(GL_ALPHA_TEST)` [deprecated] - ruby/video/cgl: removed `glEnable(GL_TEXTURE_2D)` [unnecessary as we use shaders] - processor/lr35902: started rewrite¹ ¹: so, the Game Boy and Game Boy Color cores will be completely broken for at least the next two or three WIPs. The old LR35902 was complete garbage, written in early 2011. So I'm rewriting it to provide a massive cleanup and consistency with other processor cores, especially the Z80 core. I've got about 85% of the main instructions implemented, and then I have to do the CB instructions. The CB instructions are easier because they're mostly just a small number of opcodes in many small variations, but it'll still be tedious.
2017-08-04 12:53:59 +00:00
switch(auto opcode = operand()) {
Update to v102r27 release. byuu says: Changelog: - processor/gsu: minor code cleanup - processor/hg51b: renamed reg(Read,Write) to register(Read,Write) - processor/lr35902: minor code cleanup - processor/spc700: completed code cleanup (sans disassembler) - no longer uses internal global state inside instructions - processor/spc700: will no longer hang the emulator if stuck in a WAI (SLEEP) or STP (STOP) instruction - processor/spc700: fixed bug in handling of OR1 and AND1 instructions - processor/z80: minor code cleanup - sfc/dsp: revert to initializing registers to 0x00; save for ENDX=random(), FLG=0xe0 [Jonas Quinn] Major testing of the SNES game library would be appreciated, now that its CPU cores have all been revised. We know the DSP registers read back as randomized data ... mostly, but there are apparently internal latches, which we can't emulate with the current DSP design. So until we know which registers have separate internal state that actually *is* initialized, I'm going to play it safe and not break more games. Thanks again to Jonas Quinn for the continued research into this issue. EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance that the game will work. That seems pretty unlikely that the odds of it working are that low, given hardware testing by others in the past :/ I thought if worked if `PITCH != 0` before, which would have been way more likely. The two remaining CPU cores that need major cleanup efforts are the LR35902 and ARM cores. Both are very large, complicated, annoying cores that will probably be better off as full rewrites from scratch. I don't think I want to delay v103 in trying to accomplish that, however. So I think it'll be best to focus on allowing the Mega Drive core to not lock when processors are frozen waiting on a response from other processors during a save state operation. Then we should be good for a new release.
2017-06-19 02:07:54 +00:00
}
}
Update to v103r25 release. byuu says: Changelog: - gb/cpu: force STAT mode to 0 when LCD is disabled (fixes Pokemon Pinball, etc) - gb/ppu: when LCD is disabled, require at least one-frame wait to re-enable, display white during this time - todo: should step by a scanline at a time: worst-case is an extra 99% of a frame to enable again - gba/ppu: cache tilemap lookups and attribute parsing - it's more accurate because the GBA wouldn't read this for every pixel - but unfortunately, this didn't provide any speedup at all ... sigh - ruby/audio/alsa: fixed const issue with free() - ruby/video/cgl: removed `glDisable(GL_ALPHA_TEST)` [deprecated] - ruby/video/cgl: removed `glEnable(GL_TEXTURE_2D)` [unnecessary as we use shaders] - processor/lr35902: started rewrite¹ ¹: so, the Game Boy and Game Boy Color cores will be completely broken for at least the next two or three WIPs. The old LR35902 was complete garbage, written in early 2011. So I'm rewriting it to provide a massive cleanup and consistency with other processor cores, especially the Z80 core. I've got about 85% of the main instructions implemented, and then I have to do the CB instructions. The CB instructions are easier because they're mostly just a small number of opcodes in many small variations, but it'll still be tedious.
2017-08-04 12:53:59 +00:00
#undef op