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Update to v103r25 release. 

byuu says:

Changelog:

  - gb/cpu: force STAT mode to 0 when LCD is disabled (fixes Pokemon
    Pinball, etc)
  - gb/ppu: when LCD is disabled, require at least one-frame wait to
    re-enable, display white during this time
      - todo: should step by a scanline at a time: worst-case is an
        extra 99% of a frame to enable again
  - gba/ppu: cache tilemap lookups and attribute parsing
      - it's more accurate because the GBA wouldn't read this for every
        pixel
      - but unfortunately, this didn't provide any speedup at all ...
        sigh
  - ruby/audio/alsa: fixed const issue with free()
  - ruby/video/cgl: removed `glDisable(GL_ALPHA_TEST)` [deprecated]
  - ruby/video/cgl: removed `glEnable(GL_TEXTURE_2D)` [unnecessary as
    we use shaders]
  - processor/lr35902: started rewrite¹

¹: so, the Game Boy and Game Boy Color cores will be completely
broken for at least the next two or three WIPs.

The old LR35902 was complete garbage, written in early 2011. So I'm
rewriting it to provide a massive cleanup and consistency with other
processor cores, especially the Z80 core.

I've got about 85% of the main instructions implemented, and then I have
to do the CB instructions. The CB instructions are easier because
they're mostly just a small number of opcodes in many small variations,
but it'll still be tedious.
This commit is contained in:
Tim Allen 2017-08-04 22:53:59 +10:00
parent 571760c747
commit c2975e6898
28 changed files with 2251 additions and 1453 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
higan/emulator/emulator.hpp
View File

@ -12,7 +12,7 @@ using namespace nall;
namespace Emulator {
static const string Name = "higan";
static const string Version = "103.24";
static const string Version = "103.25";
static const string Author = "byuu";
static const string License = "GPLv3";
static const string Website = "http://byuu.org/";

7
higan/gb/cpu/cpu.cpp
View File

@ -123,13 +123,6 @@ auto CPU::power() -> void {
for(auto& n : wram) n = 0x00;
for(auto& n : hram) n = 0x00;
r[PC] = 0x0000;
r[SP] = 0x0000;
r[AF] = 0x0000;
r[BC] = 0x0000;
r[DE] = 0x0000;
r[HL] = 0x0000;
memory::fill(&status, sizeof(Status));
status.dmaCompleted = true;
status.wramBank = 1;

4
higan/gb/cpu/cpu.hpp
View File

@ -17,13 +17,13 @@ struct CPU : Processor::LR35902, Thread, MMIO {
auto writeIO(uint16 addr, uint8 data) -> void;
//memory.cpp
auto io() -> void override;
auto idle() -> void override;
auto read(uint16 addr) -> uint8 override;
auto write(uint16 addr, uint8 data) -> void override;
auto cycleEdge() -> void;
auto readDMA(uint16 addr) -> uint8;
auto writeDMA(uint16 addr, uint8 data) -> void;
auto readDebugger(uint16 addr) -> uint8;
auto readDebugger(uint16 addr) -> uint8 override;
//timing.cpp
auto step(uint clocks) -> void;

2
higan/gb/cpu/memory.cpp
View File

@ -1,4 +1,4 @@
auto CPU::io() -> void {
auto CPU::idle() -> void {
cycleEdge();
step(4);
}

1
higan/gb/ppu/io.cpp
View File

@ -114,6 +114,7 @@ auto PPU::writeIO(uint16 addr, uint8 data) -> void {
if(addr == 0xff40) { //LCDC
if(status.displayEnable && !data.bit(7)) {
status.mode = 0;
status.ly = 0;
status.lx = 0;

20
higan/gb/ppu/ppu.cpp
View File

@ -13,27 +13,33 @@ auto PPU::Enter() -> void {
}
auto PPU::main() -> void {
if(!status.displayEnable) return step(456);
if(!status.displayEnable) {
for(uint n : range(160 * 144)) screen[n] = Model::GameBoy() ? 0 : 0x7fff;
Thread::step(154 * 456);
synchronize(cpu);
scheduler.exit(Scheduler::Event::Frame);
return;
}
status.lx = 0;
if(Model::SuperGameBoy()) superGameBoy->lcdScanline();
if(status.ly <= 143) {
mode(2);
status.mode = 2;
scanline();
step(92);
mode(3);
status.mode = 3;
for(auto n : range(160)) {
run();
step(1);
}
mode(0);
status.mode = 0;
cpu.hblank();
step(204);
} else {
mode(1);
status.mode = 1;
step(456);
}
@ -49,10 +55,6 @@ auto PPU::main() -> void {
}
}
auto PPU::mode(uint mode) -> void {
status.mode = mode;
}
auto PPU::stat() -> void {
bool irq = status.irq;

1
higan/gb/ppu/ppu.hpp
View File

@ -1,7 +1,6 @@
struct PPU : Thread, MMIO {
static auto Enter() -> void;
auto main() -> void;
auto mode(uint) -> void;
auto stat() -> void;
auto coincidence() -> bool;
auto refresh() -> void;

38
higan/gba/ppu/background.cpp
View File

@ -52,32 +52,37 @@ auto PPU::Background::linear(uint x, uint y) -> void {
fy = vmosaic + io.voffset;
}
uint6 tx = fx >> 3;
uint6 ty = fy >> 3;
uint3 px = fx;
uint3 py = fy;
uint offset = (ty & 31) << 5 | (tx & 31);
if(io.screenSize.bit(0) && (tx & 32)) offset += 32 << 5;
if(io.screenSize.bit(1) && (ty & 32)) offset += 32 << 5 + io.screenSize.bit(0);
offset = (io.screenBase << 11) + (offset << 1);
if(x == 0 || px == 0) {
uint6 tx = fx >> 3;
uint6 ty = fy >> 3;
uint16 tilemap = ppu.readVRAM(Half, offset);
uint10 character = tilemap.bits( 0, 9);
uint4 palette = tilemap.bits(12,15);
if(tilemap.bit(10)) px ^= 7;
if(tilemap.bit(11)) py ^= 7;
uint offset = (ty & 31) << 5 | (tx & 31);
if(io.screenSize.bit(0) && (tx & 32)) offset += 32 << 5;
if(io.screenSize.bit(1) && (ty & 32)) offset += 32 << 5 + io.screenSize.bit(0);
offset = (io.screenBase << 11) + (offset << 1);
uint16 tilemap = ppu.readVRAM(Half, offset);
latch.character = tilemap.bits(0,9);
latch.hflip = tilemap.bit(10);
latch.vflip = tilemap.bit(11);
latch.palette = tilemap.bits(12,15);
}
if(latch.hflip) px = ~px;
if(latch.vflip) py = ~py;
if(io.colorMode == 0) {
offset = (io.characterBase << 14) + (character << 5) + (py << 2) + (px >> 1);
uint offset = (io.characterBase << 14) + (latch.character << 5) + (py << 2) + (px >> 1);
if(uint4 color = ppu.readVRAM(Byte, offset) >> (px & 1 ? 4 : 0)) {
output.enable = true;
output.priority = io.priority;
output.color = ppu.pram[palette << 4 | color];
output.color = ppu.pram[latch.palette << 4 | color];
}
} else {
offset = (io.characterBase << 14) + (character << 6) + (py << 3) + (px);
uint offset = (io.characterBase << 14) + (latch.character << 6) + (py << 3) + (px);
if(uint8 color = ppu.readVRAM(Byte, offset)) {
output.enable = true;
output.priority = io.priority;
@ -172,7 +177,8 @@ auto PPU::Background::bitmap(uint x, uint y) -> void {
auto PPU::Background::power(uint id) -> void {
this->id = id;
memory::fill(&io, sizeof(IO));
io = {};
latch = {};
output = {};
mosaic = {};
mosaicOffset = 0;

7
higan/gba/ppu/ppu.hpp
View File

@ -110,6 +110,13 @@ private:
int28 ly;
} io;
struct Latch {
uint10 character;
uint1 hflip;
uint1 vflip;
uint4 palette;
} latch;
Pixel output;
Pixel mosaic;
uint mosaicOffset;

24
higan/processor/lr35902/disassembler.cpp → higan/processor/lr35902-legacy/disassembler.cpp
View File

@ -1,6 +1,6 @@
auto LR35902::disassemble(uint16 pc) -> string {
char output[80];
memset(output, ' ', sizeof output);
memory::fill(output, sizeof output, ' ');
output[79] = 0;
string opcode = disassembleOpcode(pc);
@ -12,18 +12,18 @@ auto LR35902::disassemble(uint16 pc) -> string {
" SP:", hex(r[SP], 4L)
};
memcpy(output + 0, hex(pc, 4L).data(), 4);
memcpy(output + 6, opcode.data(), opcode.length());
memcpy(output + 23, registers.data(), registers.length());
memory::copy(output + 0, hex(pc, 4L).data(), 4);
memory::copy(output + 6, opcode.data(), opcode.length());
memory::copy(output + 23, registers.data(), registers.length());
output[63] = 0;
return output;
}
auto LR35902::disassembleOpcode(uint16 pc) -> string {
uint8 opcode = debuggerRead(pc);
uint8 p0 = debuggerRead(pc + 1);
uint8 p1 = debuggerRead(pc + 2);
uint8 p2 = debuggerRead(pc + 3);
uint8 opcode = readDebugger(pc);
uint8 p0 = readDebugger(pc + 1);
uint8 p1 = readDebugger(pc + 2);
uint8 p2 = readDebugger(pc + 3);
switch(opcode) {
case 0x00: return { "nop" };
@ -288,10 +288,10 @@ auto LR35902::disassembleOpcode(uint16 pc) -> string {
}
auto LR35902::disassembleOpcodeCB(uint16 pc) -> string {
uint8 opcode = debuggerRead(pc);
uint8 p0 = debuggerRead(pc + 1);
uint8 p1 = debuggerRead(pc + 2);
uint8 p2 = debuggerRead(pc + 3);
uint8 opcode = readDebugger(pc);
uint8 p0 = readDebugger(pc + 1);
uint8 p1 = readDebugger(pc + 2);
uint8 p2 = readDebugger(pc + 3);
switch(opcode) {
case 0x00: return { "rlc b" };

531
higan/processor/lr35902-legacy/instruction.cpp Normal file
View File

@ -0,0 +1,531 @@
auto LR35902::interrupt(uint16 vector) -> void {
io();
io();
io();
r.ime = 0;
write(--r[SP], r[PC] >> 8);
write(--r[SP], r[PC] >> 0);
r[PC] = vector;
}
auto LR35902::instruction() -> void {
switch(auto opcode = read(r[PC]++)) {
case 0x00: return op_nop();
case 0x01: return op_ld_rr_nn(BC);
case 0x02: return op_ld_rr_a(BC);
case 0x03: return op_inc_rr(BC);
case 0x04: return op_inc_r(B);
case 0x05: return op_dec_r(B);
case 0x06: return op_ld_r_n(B);
case 0x07: return op_rlca();
case 0x08: return op_ld_nn_sp();
case 0x09: return op_add_hl_rr(BC);
case 0x0a: return op_ld_a_rr(BC);
case 0x0b: return op_dec_rr(BC);
case 0x0c: return op_inc_r(C);
case 0x0d: return op_dec_r(C);
case 0x0e: return op_ld_r_n(C);
case 0x0f: return op_rrca();
case 0x10: return op_stop();
case 0x11: return op_ld_rr_nn(DE);
case 0x12: return op_ld_rr_a(DE);
case 0x13: return op_inc_rr(DE);
case 0x14: return op_inc_r(D);
case 0x15: return op_dec_r(D);
case 0x16: return op_ld_r_n(D);
case 0x17: return op_rla();
case 0x18: return op_jr_n();
case 0x19: return op_add_hl_rr(DE);
case 0x1a: return op_ld_a_rr(DE);
case 0x1b: return op_dec_rr(DE);
case 0x1c: return op_inc_r(E);
case 0x1d: return op_dec_r(E);
case 0x1e: return op_ld_r_n(E);
case 0x1f: return op_rra();
case 0x20: return op_jr_f_n(ZF, 0);
case 0x21: return op_ld_rr_nn(HL);
case 0x22: return op_ldi_hl_a();
case 0x23: return op_inc_rr(HL);
case 0x24: return op_inc_r(H);
case 0x25: return op_dec_r(H);
case 0x26: return op_ld_r_n(H);
case 0x27: return op_daa();
case 0x28: return op_jr_f_n(ZF, 1);
case 0x29: return op_add_hl_rr(HL);
case 0x2a: return op_ldi_a_hl();
case 0x2b: return op_dec_rr(HL);
case 0x2c: return op_inc_r(L);
case 0x2d: return op_dec_r(L);
case 0x2e: return op_ld_r_n(L);
case 0x2f: return op_cpl();
case 0x30: return op_jr_f_n(CF, 0);
case 0x31: return op_ld_rr_nn(SP);
case 0x32: return op_ldd_hl_a();
case 0x33: return op_inc_rr(SP);
case 0x34: return op_inc_hl();
case 0x35: return op_dec_hl();
case 0x36: return op_ld_hl_n();
case 0x37: return op_scf();
case 0x38: return op_jr_f_n(CF, 1);
case 0x39: return op_add_hl_rr(SP);
case 0x3a: return op_ldd_a_hl();
case 0x3b: return op_dec_rr(SP);
case 0x3c: return op_inc_r(A);
case 0x3d: return op_dec_r(A);
case 0x3e: return op_ld_r_n(A);
case 0x3f: return op_ccf();
case 0x40: return op_ld_r_r(B, B);
case 0x41: return op_ld_r_r(B, C);
case 0x42: return op_ld_r_r(B, D);
case 0x43: return op_ld_r_r(B, E);
case 0x44: return op_ld_r_r(B, H);
case 0x45: return op_ld_r_r(B, L);
case 0x46: return op_ld_r_hl(B);
case 0x47: return op_ld_r_r(B, A);
case 0x48: return op_ld_r_r(C, B);
case 0x49: return op_ld_r_r(C, C);
case 0x4a: return op_ld_r_r(C, D);
case 0x4b: return op_ld_r_r(C, E);
case 0x4c: return op_ld_r_r(C, H);
case 0x4d: return op_ld_r_r(C, L);
case 0x4e: return op_ld_r_hl(C);
case 0x4f: return op_ld_r_r(C, A);
case 0x50: return op_ld_r_r(D, B);
case 0x51: return op_ld_r_r(D, C);
case 0x52: return op_ld_r_r(D, D);
case 0x53: return op_ld_r_r(D, E);
case 0x54: return op_ld_r_r(D, H);
case 0x55: return op_ld_r_r(D, L);
case 0x56: return op_ld_r_hl(D);
case 0x57: return op_ld_r_r(D, A);
case 0x58: return op_ld_r_r(E, B);
case 0x59: return op_ld_r_r(E, C);
case 0x5a: return op_ld_r_r(E, D);
case 0x5b: return op_ld_r_r(E, E);
case 0x5c: return op_ld_r_r(E, H);
case 0x5d: return op_ld_r_r(E, L);
case 0x5e: return op_ld_r_hl(E);
case 0x5f: return op_ld_r_r(E, A);
case 0x60: return op_ld_r_r(H, B);
case 0x61: return op_ld_r_r(H, C);
case 0x62: return op_ld_r_r(H, D);
case 0x63: return op_ld_r_r(H, E);
case 0x64: return op_ld_r_r(H, H);
case 0x65: return op_ld_r_r(H, L);
case 0x66: return op_ld_r_hl(H);
case 0x67: return op_ld_r_r(H, A);
case 0x68: return op_ld_r_r(L, B);
case 0x69: return op_ld_r_r(L, C);
case 0x6a: return op_ld_r_r(L, D);
case 0x6b: return op_ld_r_r(L, E);
case 0x6c: return op_ld_r_r(L, H);
case 0x6d: return op_ld_r_r(L, L);
case 0x6e: return op_ld_r_hl(L);
case 0x6f: return op_ld_r_r(L, A);
case 0x70: return op_ld_hl_r(B);
case 0x71: return op_ld_hl_r(C);
case 0x72: return op_ld_hl_r(D);
case 0x73: return op_ld_hl_r(E);
case 0x74: return op_ld_hl_r(H);
case 0x75: return op_ld_hl_r(L);
case 0x76: return op_halt();
case 0x77: return op_ld_hl_r(A);
case 0x78: return op_ld_r_r(A, B);
case 0x79: return op_ld_r_r(A, C);
case 0x7a: return op_ld_r_r(A, D);
case 0x7b: return op_ld_r_r(A, E);
case 0x7c: return op_ld_r_r(A, H);
case 0x7d: return op_ld_r_r(A, L);
case 0x7e: return op_ld_r_hl(A);
case 0x7f: return op_ld_r_r(A, A);
case 0x80: return op_add_a_r(B);
case 0x81: return op_add_a_r(C);
case 0x82: return op_add_a_r(D);
case 0x83: return op_add_a_r(E);
case 0x84: return op_add_a_r(H);
case 0x85: return op_add_a_r(L);
case 0x86: return op_add_a_hl();
case 0x87: return op_add_a_r(A);
case 0x88: return op_adc_a_r(B);
case 0x89: return op_adc_a_r(C);
case 0x8a: return op_adc_a_r(D);
case 0x8b: return op_adc_a_r(E);
case 0x8c: return op_adc_a_r(H);
case 0x8d: return op_adc_a_r(L);
case 0x8e: return op_adc_a_hl();
case 0x8f: return op_adc_a_r(A);
case 0x90: return op_sub_a_r(B);
case 0x91: return op_sub_a_r(C);
case 0x92: return op_sub_a_r(D);
case 0x93: return op_sub_a_r(E);
case 0x94: return op_sub_a_r(H);
case 0x95: return op_sub_a_r(L);
case 0x96: return op_sub_a_hl();
case 0x97: return op_sub_a_r(A);
case 0x98: return op_sbc_a_r(B);
case 0x99: return op_sbc_a_r(C);
case 0x9a: return op_sbc_a_r(D);
case 0x9b: return op_sbc_a_r(E);
case 0x9c: return op_sbc_a_r(H);
case 0x9d: return op_sbc_a_r(L);
case 0x9e: return op_sbc_a_hl();
case 0x9f: return op_sbc_a_r(A);
case 0xa0: return op_and_a_r(B);
case 0xa1: return op_and_a_r(C);
case 0xa2: return op_and_a_r(D);
case 0xa3: return op_and_a_r(E);
case 0xa4: return op_and_a_r(H);
case 0xa5: return op_and_a_r(L);
case 0xa6: return op_and_a_hl();
case 0xa7: return op_and_a_r(A);
case 0xa8: return op_xor_a_r(B);
case 0xa9: return op_xor_a_r(C);
case 0xaa: return op_xor_a_r(D);
case 0xab: return op_xor_a_r(E);
case 0xac: return op_xor_a_r(H);
case 0xad: return op_xor_a_r(L);
case 0xae: return op_xor_a_hl();
case 0xaf: return op_xor_a_r(A);
case 0xb0: return op_or_a_r(B);
case 0xb1: return op_or_a_r(C);
case 0xb2: return op_or_a_r(D);
case 0xb3: return op_or_a_r(E);
case 0xb4: return op_or_a_r(H);
case 0xb5: return op_or_a_r(L);
case 0xb6: return op_or_a_hl();
case 0xb7: return op_or_a_r(A);
case 0xb8: return op_cp_a_r(B);
case 0xb9: return op_cp_a_r(C);
case 0xba: return op_cp_a_r(D);
case 0xbb: return op_cp_a_r(E);
case 0xbc: return op_cp_a_r(H);
case 0xbd: return op_cp_a_r(L);
case 0xbe: return op_cp_a_hl();
case 0xbf: return op_cp_a_r(A);
case 0xc0: return op_ret_f(ZF, 0);
case 0xc1: return op_pop_rr(BC);
case 0xc2: return op_jp_f_nn(ZF, 0);
case 0xc3: return op_jp_nn();
case 0xc4: return op_call_f_nn(ZF, 0);
case 0xc5: return op_push_rr(BC);
case 0xc6: return op_add_a_n();
case 0xc7: return op_rst_n(0x00);
case 0xc8: return op_ret_f(ZF, 1);
case 0xc9: return op_ret();
case 0xca: return op_jp_f_nn(ZF, 1);
case 0xcb: return op_cb();
case 0xcc: return op_call_f_nn(ZF, 1);
case 0xcd: return op_call_nn();
case 0xce: return op_adc_a_n();
case 0xcf: return op_rst_n(0x08);
case 0xd0: return op_ret_f(CF, 0);
case 0xd1: return op_pop_rr(DE);
case 0xd2: return op_jp_f_nn(CF, 0);
case 0xd3: return op_xx();
case 0xd4: return op_call_f_nn(CF, 0);
case 0xd5: return op_push_rr(DE);
case 0xd6: return op_sub_a_n();
case 0xd7: return op_rst_n(0x10);
case 0xd8: return op_ret_f(CF, 1);
case 0xd9: return op_reti();
case 0xda: return op_jp_f_nn(CF, 1);
case 0xdb: return op_xx();
case 0xdc: return op_call_f_nn(CF, 1);
case 0xdd: return op_xx();
case 0xde: return op_sbc_a_n();
case 0xdf: return op_rst_n(0x18);
case 0xe0: return op_ld_ffn_a();
case 0xe1: return op_pop_rr(HL);
case 0xe2: return op_ld_ffc_a();
case 0xe3: return op_xx();
case 0xe4: return op_xx();
case 0xe5: return op_push_rr(HL);
case 0xe6: return op_and_a_n();
case 0xe7: return op_rst_n(0x20);
case 0xe8: return op_add_sp_n();
case 0xe9: return op_jp_hl();
case 0xea: return op_ld_nn_a();
case 0xeb: return op_xx();
case 0xec: return op_xx();
case 0xed: return op_xx();
case 0xee: return op_xor_a_n();
case 0xef: return op_rst_n(0x28);
case 0xf0: return op_ld_a_ffn();
case 0xf1: return op_pop_rr(AF);
case 0xf2: return op_ld_a_ffc();
case 0xf3: return op_di();
case 0xf4: return op_xx();
case 0xf5: return op_push_rr(AF);
case 0xf6: return op_or_a_n();
case 0xf7: return op_rst_n(0x30);
case 0xf8: return op_ld_hl_sp_n();
case 0xf9: return op_ld_sp_hl();
case 0xfa: return op_ld_a_nn();
case 0xfb: return op_ei();
case 0xfc: return op_xx();
case 0xfd: return op_xx();
case 0xfe: return op_cp_a_n();
case 0xff: return op_rst_n(0x38);
}
}
auto LR35902::instructionCB() -> void {
switch(auto opcode = read(r[PC]++)) {
case 0x00: return op_rlc_r(B);
case 0x01: return op_rlc_r(C);
case 0x02: return op_rlc_r(D);
case 0x03: return op_rlc_r(E);
case 0x04: return op_rlc_r(H);
case 0x05: return op_rlc_r(L);
case 0x06: return op_rlc_hl();
case 0x07: return op_rlc_r(A);
case 0x08: return op_rrc_r(B);
case 0x09: return op_rrc_r(C);
case 0x0a: return op_rrc_r(D);
case 0x0b: return op_rrc_r(E);
case 0x0c: return op_rrc_r(H);
case 0x0d: return op_rrc_r(L);
case 0x0e: return op_rrc_hl();
case 0x0f: return op_rrc_r(A);
case 0x10: return op_rl_r(B);
case 0x11: return op_rl_r(C);
case 0x12: return op_rl_r(D);
case 0x13: return op_rl_r(E);
case 0x14: return op_rl_r(H);
case 0x15: return op_rl_r(L);
case 0x16: return op_rl_hl();
case 0x17: return op_rl_r(A);
case 0x18: return op_rr_r(B);
case 0x19: return op_rr_r(C);
case 0x1a: return op_rr_r(D);
case 0x1b: return op_rr_r(E);
case 0x1c: return op_rr_r(H);
case 0x1d: return op_rr_r(L);
case 0x1e: return op_rr_hl();
case 0x1f: return op_rr_r(A);
case 0x20: return op_sla_r(B);
case 0x21: return op_sla_r(C);
case 0x22: return op_sla_r(D);
case 0x23: return op_sla_r(E);
case 0x24: return op_sla_r(H);
case 0x25: return op_sla_r(L);
case 0x26: return op_sla_hl();
case 0x27: return op_sla_r(A);
case 0x28: return op_sra_r(B);
case 0x29: return op_sra_r(C);
case 0x2a: return op_sra_r(D);
case 0x2b: return op_sra_r(E);
case 0x2c: return op_sra_r(H);
case 0x2d: return op_sra_r(L);
case 0x2e: return op_sra_hl();
case 0x2f: return op_sra_r(A);
case 0x30: return op_swap_r(B);
case 0x31: return op_swap_r(C);
case 0x32: return op_swap_r(D);
case 0x33: return op_swap_r(E);
case 0x34: return op_swap_r(H);
case 0x35: return op_swap_r(L);
case 0x36: return op_swap_hl();
case 0x37: return op_swap_r(A);
case 0x38: return op_srl_r(B);
case 0x39: return op_srl_r(C);
case 0x3a: return op_srl_r(D);
case 0x3b: return op_srl_r(E);
case 0x3c: return op_srl_r(H);
case 0x3d: return op_srl_r(L);
case 0x3e: return op_srl_hl();
case 0x3f: return op_srl_r(A);
case 0x40: return op_bit_n_r(0, B);
case 0x41: return op_bit_n_r(0, C);
case 0x42: return op_bit_n_r(0, D);
case 0x43: return op_bit_n_r(0, E);
case 0x44: return op_bit_n_r(0, H);
case 0x45: return op_bit_n_r(0, L);
case 0x46: return op_bit_n_hl(0);
case 0x47: return op_bit_n_r(0, A);
case 0x48: return op_bit_n_r(1, B);
case 0x49: return op_bit_n_r(1, C);
case 0x4a: return op_bit_n_r(1, D);
case 0x4b: return op_bit_n_r(1, E);
case 0x4c: return op_bit_n_r(1, H);
case 0x4d: return op_bit_n_r(1, L);
case 0x4e: return op_bit_n_hl(1);
case 0x4f: return op_bit_n_r(1, A);
case 0x50: return op_bit_n_r(2, B);
case 0x51: return op_bit_n_r(2, C);
case 0x52: return op_bit_n_r(2, D);
case 0x53: return op_bit_n_r(2, E);
case 0x54: return op_bit_n_r(2, H);
case 0x55: return op_bit_n_r(2, L);
case 0x56: return op_bit_n_hl(2);
case 0x57: return op_bit_n_r(2, A);
case 0x58: return op_bit_n_r(3, B);
case 0x59: return op_bit_n_r(3, C);
case 0x5a: return op_bit_n_r(3, D);
case 0x5b: return op_bit_n_r(3, E);
case 0x5c: return op_bit_n_r(3, H);
case 0x5d: return op_bit_n_r(3, L);
case 0x5e: return op_bit_n_hl(3);
case 0x5f: return op_bit_n_r(3, A);
case 0x60: return op_bit_n_r(4, B);
case 0x61: return op_bit_n_r(4, C);
case 0x62: return op_bit_n_r(4, D);
case 0x63: return op_bit_n_r(4, E);
case 0x64: return op_bit_n_r(4, H);
case 0x65: return op_bit_n_r(4, L);
case 0x66: return op_bit_n_hl(4);
case 0x67: return op_bit_n_r(4, A);
case 0x68: return op_bit_n_r(5, B);
case 0x69: return op_bit_n_r(5, C);
case 0x6a: return op_bit_n_r(5, D);
case 0x6b: return op_bit_n_r(5, E);
case 0x6c: return op_bit_n_r(5, H);
case 0x6d: return op_bit_n_r(5, L);
case 0x6e: return op_bit_n_hl(5);
case 0x6f: return op_bit_n_r(5, A);
case 0x70: return op_bit_n_r(6, B);
case 0x71: return op_bit_n_r(6, C);
case 0x72: return op_bit_n_r(6, D);
case 0x73: return op_bit_n_r(6, E);
case 0x74: return op_bit_n_r(6, H);
case 0x75: return op_bit_n_r(6, L);
case 0x76: return op_bit_n_hl(6);
case 0x77: return op_bit_n_r(6, A);
case 0x78: return op_bit_n_r(7, B);
case 0x79: return op_bit_n_r(7, C);
case 0x7a: return op_bit_n_r(7, D);
case 0x7b: return op_bit_n_r(7, E);
case 0x7c: return op_bit_n_r(7, H);
case 0x7d: return op_bit_n_r(7, L);
case 0x7e: return op_bit_n_hl(7);
case 0x7f: return op_bit_n_r(7, A);
case 0x80: return op_res_n_r(0, B);
case 0x81: return op_res_n_r(0, C);
case 0x82: return op_res_n_r(0, D);
case 0x83: return op_res_n_r(0, E);
case 0x84: return op_res_n_r(0, H);
case 0x85: return op_res_n_r(0, L);
case 0x86: return op_res_n_hl(0);
case 0x87: return op_res_n_r(0, A);
case 0x88: return op_res_n_r(1, B);
case 0x89: return op_res_n_r(1, C);
case 0x8a: return op_res_n_r(1, D);
case 0x8b: return op_res_n_r(1, E);
case 0x8c: return op_res_n_r(1, H);
case 0x8d: return op_res_n_r(1, L);
case 0x8e: return op_res_n_hl(1);
case 0x8f: return op_res_n_r(1, A);
case 0x90: return op_res_n_r(2, B);
case 0x91: return op_res_n_r(2, C);
case 0x92: return op_res_n_r(2, D);
case 0x93: return op_res_n_r(2, E);
case 0x94: return op_res_n_r(2, H);
case 0x95: return op_res_n_r(2, L);
case 0x96: return op_res_n_hl(2);
case 0x97: return op_res_n_r(2, A);
case 0x98: return op_res_n_r(3, B);
case 0x99: return op_res_n_r(3, C);
case 0x9a: return op_res_n_r(3, D);
case 0x9b: return op_res_n_r(3, E);
case 0x9c: return op_res_n_r(3, H);
case 0x9d: return op_res_n_r(3, L);
case 0x9e: return op_res_n_hl(3);
case 0x9f: return op_res_n_r(3, A);
case 0xa0: return op_res_n_r(4, B);
case 0xa1: return op_res_n_r(4, C);
case 0xa2: return op_res_n_r(4, D);
case 0xa3: return op_res_n_r(4, E);
case 0xa4: return op_res_n_r(4, H);
case 0xa5: return op_res_n_r(4, L);
case 0xa6: return op_res_n_hl(4);
case 0xa7: return op_res_n_r(4, A);
case 0xa8: return op_res_n_r(5, B);
case 0xa9: return op_res_n_r(5, C);
case 0xaa: return op_res_n_r(5, D);
case 0xab: return op_res_n_r(5, E);
case 0xac: return op_res_n_r(5, H);
case 0xad: return op_res_n_r(5, L);
case 0xae: return op_res_n_hl(5);
case 0xaf: return op_res_n_r(5, A);
case 0xb0: return op_res_n_r(6, B);
case 0xb1: return op_res_n_r(6, C);
case 0xb2: return op_res_n_r(6, D);
case 0xb3: return op_res_n_r(6, E);
case 0xb4: return op_res_n_r(6, H);
case 0xb5: return op_res_n_r(6, L);
case 0xb6: return op_res_n_hl(6);
case 0xb7: return op_res_n_r(6, A);
case 0xb8: return op_res_n_r(7, B);
case 0xb9: return op_res_n_r(7, C);
case 0xba: return op_res_n_r(7, D);
case 0xbb: return op_res_n_r(7, E);
case 0xbc: return op_res_n_r(7, H);
case 0xbd: return op_res_n_r(7, L);
case 0xbe: return op_res_n_hl(7);
case 0xbf: return op_res_n_r(7, A);
case 0xc0: return op_set_n_r(0, B);
case 0xc1: return op_set_n_r(0, C);
case 0xc2: return op_set_n_r(0, D);
case 0xc3: return op_set_n_r(0, E);
case 0xc4: return op_set_n_r(0, H);
case 0xc5: return op_set_n_r(0, L);
case 0xc6: return op_set_n_hl(0);
case 0xc7: return op_set_n_r(0, A);
case 0xc8: return op_set_n_r(1, B);
case 0xc9: return op_set_n_r(1, C);
case 0xca: return op_set_n_r(1, D);
case 0xcb: return op_set_n_r(1, E);
case 0xcc: return op_set_n_r(1, H);
case 0xcd: return op_set_n_r(1, L);
case 0xce: return op_set_n_hl(1);
case 0xcf: return op_set_n_r(1, A);
case 0xd0: return op_set_n_r(2, B);
case 0xd1: return op_set_n_r(2, C);
case 0xd2: return op_set_n_r(2, D);
case 0xd3: return op_set_n_r(2, E);
case 0xd4: return op_set_n_r(2, H);
case 0xd5: return op_set_n_r(2, L);
case 0xd6: return op_set_n_hl(2);
case 0xd7: return op_set_n_r(2, A);
case 0xd8: return op_set_n_r(3, B);
case 0xd9: return op_set_n_r(3, C);
case 0xda: return op_set_n_r(3, D);
case 0xdb: return op_set_n_r(3, E);
case 0xdc: return op_set_n_r(3, H);
case 0xdd: return op_set_n_r(3, L);
case 0xde: return op_set_n_hl(3);
case 0xdf: return op_set_n_r(3, A);
case 0xe0: return op_set_n_r(4, B);
case 0xe1: return op_set_n_r(4, C);
case 0xe2: return op_set_n_r(4, D);
case 0xe3: return op_set_n_r(4, E);
case 0xe4: return op_set_n_r(4, H);
case 0xe5: return op_set_n_r(4, L);
case 0xe6: return op_set_n_hl(4);
case 0xe7: return op_set_n_r(4, A);
case 0xe8: return op_set_n_r(5, B);
case 0xe9: return op_set_n_r(5, C);
case 0xea: return op_set_n_r(5, D);
case 0xeb: return op_set_n_r(5, E);
case 0xec: return op_set_n_r(5, H);
case 0xed: return op_set_n_r(5, L);
case 0xee: return op_set_n_hl(5);
case 0xef: return op_set_n_r(5, A);
case 0xf0: return op_set_n_r(6, B);
case 0xf1: return op_set_n_r(6, C);
case 0xf2: return op_set_n_r(6, D);
case 0xf3: return op_set_n_r(6, E);
case 0xf4: return op_set_n_r(6, H);
case 0xf5: return op_set_n_r(6, L);
case 0xf6: return op_set_n_hl(6);
case 0xf7: return op_set_n_r(6, A);
case 0xf8: return op_set_n_r(7, B);
case 0xf9: return op_set_n_r(7, C);
case 0xfa: return op_set_n_r(7, D);
case 0xfb: return op_set_n_r(7, E);
case 0xfc: return op_set_n_r(7, H);
case 0xfd: return op_set_n_r(7, L);
case 0xfe: return op_set_n_hl(7);
case 0xff: return op_set_n_r(7, A);
}
}

668
higan/processor/lr35902-legacy/instructions.cpp Normal file
View File

@ -0,0 +1,668 @@
auto LR35902::op_xx() {
}
auto LR35902::op_cb() {
instructionCB();
}
//8-bit load commands
auto LR35902::op_ld_r_r(uint x, uint y) {
r[x] = r[y];
}
auto LR35902::op_ld_r_n(uint x) {
r[x] = read(r[PC]++);
}
auto LR35902::op_ld_r_hl(uint x) {
r[x] = read(r[HL]);
}
auto LR35902::op_ld_hl_r(uint x) {
write(r[HL], r[x]);
}
auto LR35902::op_ld_hl_n() {
write(r[HL], read(r[PC]++));
}
auto LR35902::op_ld_a_rr(uint x) {
r[A] = read(r[x]);
}
auto LR35902::op_ld_a_nn() {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
r[A] = read((hi << 8) | (lo << 0));
}
auto LR35902::op_ld_rr_a(uint x) {
write(r[x], r[A]);
}
auto LR35902::op_ld_nn_a() {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
write((hi << 8) | (lo << 0), r[A]);
}
auto LR35902::op_ld_a_ffn() {
r[A] = read(0xff00 + read(r[PC]++));
}
auto LR35902::op_ld_ffn_a() {
write(0xff00 + read(r[PC]++), r[A]);
}
auto LR35902::op_ld_a_ffc() {
r[A] = read(0xff00 + r[C]);
}
auto LR35902::op_ld_ffc_a() {
write(0xff00 + r[C], r[A]);
}
auto LR35902::op_ldi_hl_a() {
write(r[HL], r[A]);
r[HL]++;
}
auto LR35902::op_ldi_a_hl() {
r[A] = read(r[HL]);
r[HL]++;
}
auto LR35902::op_ldd_hl_a() {
write(r[HL], r[A]);
r[HL]--;
}
auto LR35902::op_ldd_a_hl() {
r[A] = read(r[HL]);
r[HL]--;
}
//16-bit load commands
auto LR35902::op_ld_rr_nn(uint x) {
r[x] = read(r[PC]++) << 0;
r[x] |= read(r[PC]++) << 8;
}
auto LR35902::op_ld_nn_sp() {
uint16 addr = read(r[PC]++) << 0;
addr |= read(r[PC]++) << 8;
write(addr + 0, r[SP] >> 0);
write(addr + 1, r[SP] >> 8);
}
auto LR35902::op_ld_sp_hl() {
r[SP] = r[HL];
io();
}
auto LR35902::op_push_rr(uint x) {
io();
write(--r[SP], r[x] >> 8);
write(--r[SP], r[x] >> 0);
}
auto LR35902::op_pop_rr(uint x) {
r[x] = read(r[SP]++) << 0;
r[x] |= read(r[SP]++) << 8;
}
//8-bit arithmetic commands
auto LR35902::opi_add_a(uint8 x) {
uint16 rh = r[A] + x;
uint16 rl = (r[A] & 0x0f) + (x & 0x0f);
r[A] = rh;
r.f.z = (uint8)rh == 0;
r.f.n = 0;
r.f.h = rl > 0x0f;
r.f.c = rh > 0xff;
}
auto LR35902::op_add_a_r(uint x) { opi_add_a(r[x]); }
auto LR35902::op_add_a_n() { opi_add_a(read(r[PC]++)); }
auto LR35902::op_add_a_hl() { opi_add_a(read(r[HL])); }
auto LR35902::opi_adc_a(uint8 x) {
uint16 rh = r[A] + x + r.f.c;
uint16 rl = (r[A] & 0x0f) + (x & 0x0f) + r.f.c;
r[A] = rh;
r.f.z = (uint8)rh == 0;
r.f.n = 0;
r.f.h = rl > 0x0f;
r.f.c = rh > 0xff;
}
auto LR35902::op_adc_a_r(uint x) { opi_adc_a(r[x]); }
auto LR35902::op_adc_a_n() { opi_adc_a(read(r[PC]++)); }
auto LR35902::op_adc_a_hl() { opi_adc_a(read(r[HL])); }
auto LR35902::opi_sub_a(uint8 x) {
uint16 rh = r[A] - x;
uint16 rl = (r[A] & 0x0f) - (x & 0x0f);
r[A] = rh;
r.f.z = (uint8)rh == 0;
r.f.n = 1;
r.f.h = rl > 0x0f;
r.f.c = rh > 0xff;
}
auto LR35902::op_sub_a_r(uint x) { opi_sub_a(r[x]); }
auto LR35902::op_sub_a_n() { opi_sub_a(read(r[PC]++)); }
auto LR35902::op_sub_a_hl() { opi_sub_a(read(r[HL])); }
auto LR35902::opi_sbc_a(uint8 x) {
uint16 rh = r[A] - x - r.f.c;
uint16 rl = (r[A] & 0x0f) - (x & 0x0f) - r.f.c;
r[A] = rh;
r.f.z = (uint8)rh == 0;
r.f.n = 1;
r.f.h = rl > 0x0f;
r.f.c = rh > 0xff;
}
auto LR35902::op_sbc_a_r(uint x) { opi_sbc_a(r[x]); }
auto LR35902::op_sbc_a_n() { opi_sbc_a(read(r[PC]++)); }
auto LR35902::op_sbc_a_hl() { opi_sbc_a(read(r[HL])); }
auto LR35902::opi_and_a(uint8 x) {
r[A] &= x;
r.f.z = r[A] == 0;
r.f.n = 0;
r.f.h = 1;
r.f.c = 0;
}
auto LR35902::op_and_a_r(uint x) { opi_and_a(r[x]); }
auto LR35902::op_and_a_n() { opi_and_a(read(r[PC]++)); }
auto LR35902::op_and_a_hl() { opi_and_a(read(r[HL])); }
auto LR35902::opi_xor_a(uint8 x) {
r[A] ^= x;
r.f.z = r[A] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = 0;
}
auto LR35902::op_xor_a_r(uint x) { opi_xor_a(r[x]); }
auto LR35902::op_xor_a_n() { opi_xor_a(read(r[PC]++)); }
auto LR35902::op_xor_a_hl() { opi_xor_a(read(r[HL])); }
auto LR35902::opi_or_a(uint8 x) {
r[A] |= x;
r.f.z = r[A] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = 0;
}
auto LR35902::op_or_a_r(uint x) { opi_or_a(r[x]); }
auto LR35902::op_or_a_n() { opi_or_a(read(r[PC]++)); }
auto LR35902::op_or_a_hl() { opi_or_a(read(r[HL])); }
auto LR35902::opi_cp_a(uint8 x) {
uint16 rh = r[A] - x;
uint16 rl = (r[A] & 0x0f) - (x & 0x0f);
r.f.z = (uint8)rh == 0;
r.f.n = 1;
r.f.h = rl > 0x0f;
r.f.c = rh > 0xff;
}
auto LR35902::op_cp_a_r(uint x) { opi_cp_a(r[x]); }
auto LR35902::op_cp_a_n() { opi_cp_a(read(r[PC]++)); }
auto LR35902::op_cp_a_hl() { opi_cp_a(read(r[HL])); }
auto LR35902::op_inc_r(uint x) {
r[x]++;
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = (r[x] & 0x0f) == 0x00;
}
auto LR35902::op_inc_hl() {
uint8 n = read(r[HL]);
write(r[HL], ++n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = (n & 0x0f) == 0x00;
}
auto LR35902::op_dec_r(uint x) {
r[x]--;
r.f.z = r[x] == 0;
r.f.n = 1;
r.f.h = (r[x] & 0x0f) == 0x0f;
}
auto LR35902::op_dec_hl() {
uint8 n = read(r[HL]);
write(r[HL], --n);
r.f.z = n == 0;
r.f.n = 1;
r.f.h = (n & 0x0f) == 0x0f;
}
auto LR35902::op_daa() {
uint16 a = r[A];
if(r.f.n == 0) {
if(r.f.h || (a & 0x0f) > 0x09) a += 0x06;
if(r.f.c || (a ) > 0x9f) a += 0x60;
} else {
if(r.f.h) {
a -= 0x06;
if(r.f.c == 0) a &= 0xff;
}
if(r.f.c) a -= 0x60;
}
r[A] = a;
r.f.z = r[A] == 0;
r.f.h = 0;
r.f.c |= a & 0x100;
}
auto LR35902::op_cpl() {
r[A] ^= 0xff;
r.f.n = 1;
r.f.h = 1;
}
//16-bit arithmetic commands
auto LR35902::op_add_hl_rr(uint x) {
io();
uint32 rb = (r[HL] + r[x]);
uint32 rn = (r[HL] & 0xfff) + (r[x] & 0xfff);
r[HL] = rb;
r.f.n = 0;
r.f.h = rn > 0x0fff;
r.f.c = rb > 0xffff;
}
auto LR35902::op_inc_rr(uint x) {
io();
r[x]++;
}
auto LR35902::op_dec_rr(uint x) {
io();
r[x]--;
}
auto LR35902::op_add_sp_n() {
int n = (int8)read(r[PC]++);
r.f.z = 0;
r.f.n = 0;
r.f.h = ((r[SP] & 0x0f) + (n & 0x0f)) > 0x0f;
r.f.c = ((r[SP] & 0xff) + (n & 0xff)) > 0xff;
r[SP] += n;
io();
io();
}
auto LR35902::op_ld_hl_sp_n() {
int n = (int8)read(r[PC]++);
r.f.z = 0;
r.f.n = 0;
r.f.h = ((r[SP] & 0x0f) + (n & 0x0f)) > 0x0f;
r.f.c = ((r[SP] & 0xff) + (n & 0xff)) > 0xff;
r[HL] = r[SP] + n;
io();
}
//rotate/shift commands
auto LR35902::op_rlca() {
r[A] = (r[A] << 1) | (r[A] >> 7);
r.f.z = 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = r[A] & 0x01;
}
auto LR35902::op_rla() {
bool c = r[A] & 0x80;
r[A] = (r[A] << 1) | (r.f.c << 0);
r.f.z = 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_rrca() {
r[A] = (r[A] >> 1) | (r[A] << 7);
r.f.z = 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = r[A] & 0x80;
}
auto LR35902::op_rra() {
bool c = r[A] & 0x01;
r[A] = (r[A] >> 1) | (r.f.c << 7);
r.f.z = 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_rlc_r(uint x) {
r[x] = (r[x] << 1) | (r[x] >> 7);
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = r[x] & 0x01;
}
auto LR35902::op_rlc_hl() {
uint8 n = read(r[HL]);
n = (n << 1) | (n >> 7);
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = n & 0x01;
}
auto LR35902::op_rl_r(uint x) {
bool c = r[x] & 0x80;
r[x] = (r[x] << 1) | (r.f.c << 0);
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_rl_hl() {
uint8 n = read(r[HL]);
bool c = n & 0x80;
n = (n << 1) | (r.f.c << 0);
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_rrc_r(uint x) {
r[x] = (r[x] >> 1) | (r[x] << 7);
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = r[x] & 0x80;
}
auto LR35902::op_rrc_hl() {
uint8 n = read(r[HL]);
n = (n >> 1) | (n << 7);
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = n & 0x80;
}
auto LR35902::op_rr_r(uint x) {
bool c = r[x] & 0x01;
r[x] = (r[x] >> 1) | (r.f.c << 7);
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_rr_hl() {
uint8 n = read(r[HL]);
bool c = n & 0x01;
n = (n >> 1) | (r.f.c << 7);
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_sla_r(uint x) {
bool c = r[x] & 0x80;
r[x] <<= 1;
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_sla_hl() {
uint8 n = read(r[HL]);
bool c = n & 0x80;
n <<= 1;
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_swap_r(uint x) {
r[x] = (r[x] << 4) | (r[x] >> 4);
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = 0;
}
auto LR35902::op_swap_hl() {
uint8 n = read(r[HL]);
n = (n << 4) | (n >> 4);
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = 0;
}
auto LR35902::op_sra_r(uint x) {
bool c = r[x] & 0x01;
r[x] = (int8)r[x] >> 1;
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_sra_hl() {
uint8 n = read(r[HL]);
bool c = n & 0x01;
n = (int8)n >> 1;
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_srl_r(uint x) {
bool c = r[x] & 0x01;
r[x] >>= 1;
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_srl_hl() {
uint8 n = read(r[HL]);
bool c = n & 0x01;
n >>= 1;
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
//single-bit commands
auto LR35902::op_bit_n_r(uint b, uint x) {
r.f.z = (r[x] & (1 << b)) == 0;
r.f.n = 0;
r.f.h = 1;
}
auto LR35902::op_bit_n_hl(uint b) {
uint8 n = read(r[HL]);
r.f.z = (n & (1 << b)) == 0;
r.f.n = 0;
r.f.h = 1;
}
auto LR35902::op_set_n_r(uint b, uint x) {
r[x] |= 1 << b;
}
auto LR35902::op_set_n_hl(uint b) {
uint8 n = read(r[HL]);
n |= 1 << b;
write(r[HL], n);
}
auto LR35902::op_res_n_r(uint b, uint x) {
r[x] &= ~(1 << b);
}
auto LR35902::op_res_n_hl(uint b) {
uint n = read(r[HL]);
n &= ~(1 << b);
write(r[HL], n);
}
//control commands
auto LR35902::op_ccf() {
r.f.n = 0;
r.f.h = 0;
r.f.c = !r.f.c;
}
auto LR35902::op_scf() {
r.f.n = 0;
r.f.h = 0;
r.f.c = 1;
}
auto LR35902::op_nop() {
}
auto LR35902::op_halt() {
r.halt = true;
while(r.halt) io();
}
auto LR35902::op_stop() {
if(stop()) return;
r.stop = true;
while(r.stop) io();
}
auto LR35902::op_di() {
r.ime = 0;
}
auto LR35902::op_ei() {
r.ei = true;
//r.ime = 1;
}
//jump commands
auto LR35902::op_jp_nn() {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
r[PC] = (hi << 8) | (lo << 0);
io();
}
auto LR35902::op_jp_hl() {
r[PC] = r[HL];
}
auto LR35902::op_jp_f_nn(uint x, bool y) {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
if(r.f[x] == y) {
r[PC] = (hi << 8) | (lo << 0);
io();
}
}
auto LR35902::op_jr_n() {
int8 n = read(r[PC]++);
r[PC] += n;
io();
}
auto LR35902::op_jr_f_n(uint x, bool y) {
int8 n = read(r[PC]++);
if(r.f[x] == y) {
r[PC] += n;
io();
}
}
auto LR35902::op_call_nn() {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
io();
write(--r[SP], r[PC] >> 8);
write(--r[SP], r[PC] >> 0);
r[PC] = (hi << 8) | (lo << 0);
}
auto LR35902::op_call_f_nn(uint x, bool y) {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
if(r.f[x] == y) {
io();
write(--r[SP], r[PC] >> 8);
write(--r[SP], r[PC] >> 0);
r[PC] = (hi << 8) | (lo << 0);
}
}
auto LR35902::op_ret() {
uint8 lo = read(r[SP]++);
uint8 hi = read(r[SP]++);
r[PC] = (hi << 8) | (lo << 0);
io();
}
auto LR35902::op_ret_f(uint x, bool y) {
io();
if(r.f[x] == y) {
uint8 lo = read(r[SP]++);
uint8 hi = read(r[SP]++);
r[PC] = (hi << 8) | (lo << 0);
io();
}
}
auto LR35902::op_reti() {
uint8 lo = read(r[SP]++);
uint8 hi = read(r[SP]++);
r[PC] = (hi << 8) | (lo << 0);
io();
r.ime = 1;
}
auto LR35902::op_rst_n(uint n) {
io();
write(--r[SP], r[PC] >> 8);
write(--r[SP], r[PC] >> 0);
r[PC] = n;
}

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#include <processor/processor.hpp>
#include "lr35902.hpp"
namespace Processor {
#include "instructions.cpp"
#include "instruction.cpp"
#include "serialization.cpp"
#include "disassembler.cpp"
auto LR35902::power() -> void {
r.halt = false;
r.stop = false;
r.ei = false;
r.ime = false;
}
}

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//Sharp LR35902 (Game Boy Z80-derivative)
#pragma once
namespace Processor {
struct LR35902 {
virtual auto io() -> void = 0;
virtual auto read(uint16 addr) -> uint8 = 0;
virtual auto write(uint16 addr, uint8 data) -> void = 0;
virtual auto stop() -> bool = 0;
//lr35902.cpp
auto power() -> void;
//instruction.cpp
auto interrupt(uint16 vector) -> void;
auto instruction() -> void;
auto instructionCB() -> void;
//serialization.cpp
auto serialize(serializer&) -> void;
//disassembler.cpp
virtual auto readDebugger(uint16 addr) -> uint8 { return 0; }
auto disassemble(uint16 pc) -> string;
#include "registers.hpp"
private:
auto op_xx();
auto op_cb();
//8-bit load commands
auto op_ld_r_r(uint x, uint y);
auto op_ld_r_n(uint x);
auto op_ld_r_hl(uint x);
auto op_ld_hl_r(uint x);
auto op_ld_hl_n();
auto op_ld_a_rr(uint x);
auto op_ld_a_nn();
auto op_ld_rr_a(uint x);
auto op_ld_nn_a();
auto op_ld_a_ffn();
auto op_ld_ffn_a();
auto op_ld_a_ffc();
auto op_ld_ffc_a();
auto op_ldi_hl_a();
auto op_ldi_a_hl();
auto op_ldd_hl_a();
auto op_ldd_a_hl();
//16-bit load commands
auto op_ld_rr_nn(uint x);
auto op_ld_nn_sp();
auto op_ld_sp_hl();
auto op_push_rr(uint x);
auto op_pop_rr(uint x);
//8-bit arithmetic commands
auto opi_add_a(uint8 x);
auto op_add_a_r(uint x);
auto op_add_a_n();
auto op_add_a_hl();
auto opi_adc_a(uint8 x);
auto op_adc_a_r(uint x);
auto op_adc_a_n();
auto op_adc_a_hl();
auto opi_sub_a(uint8 x);
auto op_sub_a_r(uint x);
auto op_sub_a_n();
auto op_sub_a_hl();
auto opi_sbc_a(uint8 x);
auto op_sbc_a_r(uint x);
auto op_sbc_a_n();
auto op_sbc_a_hl();
auto opi_and_a(uint8 x);
auto op_and_a_r(uint x);
auto op_and_a_n();
auto op_and_a_hl();
auto opi_xor_a(uint8 x);
auto op_xor_a_r(uint x);
auto op_xor_a_n();
auto op_xor_a_hl();
auto opi_or_a(uint8 x);
auto op_or_a_r(uint x);
auto op_or_a_n();
auto op_or_a_hl();
auto opi_cp_a(uint8 x);
auto op_cp_a_r(uint x);
auto op_cp_a_n();
auto op_cp_a_hl();
auto op_inc_r(uint x);
auto op_inc_hl();
auto op_dec_r(uint x);
auto op_dec_hl();
auto op_daa();
auto op_cpl();
//16-bit arithmetic commands
auto op_add_hl_rr(uint x);
auto op_inc_rr(uint x);
auto op_dec_rr(uint x);
auto op_add_sp_n();
auto op_ld_hl_sp_n();
//rotate/shift commands
auto op_rlca();
auto op_rla();
auto op_rrca();
auto op_rra();
auto op_rlc_r(uint x);
auto op_rlc_hl();
auto op_rl_r(uint x);
auto op_rl_hl();
auto op_rrc_r(uint x);
auto op_rrc_hl();
auto op_rr_r(uint x);
auto op_rr_hl();
auto op_sla_r(uint x);
auto op_sla_hl();
auto op_swap_r(uint x);
auto op_swap_hl();
auto op_sra_r(uint x);
auto op_sra_hl();
auto op_srl_r(uint x);
auto op_srl_hl();
//single-bit commands
auto op_bit_n_r(uint b, uint x);
auto op_bit_n_hl(uint b);
auto op_set_n_r(uint b, uint x);
auto op_set_n_hl(uint b);
auto op_res_n_r(uint b, uint x);
auto op_res_n_hl(uint b);
//control commands
auto op_ccf();
auto op_scf();
auto op_nop();
auto op_halt();
auto op_stop();
auto op_di();
auto op_ei();
//jump commands
auto op_jp_nn();
auto op_jp_hl();
auto op_jp_f_nn(uint x, bool y);
auto op_jr_n();
auto op_jr_f_n(uint x, bool y);
auto op_call_nn();
auto op_call_f_nn(uint x, bool y);
auto op_ret();
auto op_ret_f(uint x, bool y);
auto op_reti();
auto op_rst_n(uint n);
//disassembler.cpp
auto disassembleOpcode(uint16 pc) -> string;
auto disassembleOpcodeCB(uint16 pc) -> string;
};
}

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enum {
A, F, AF,
B, C, BC,
D, E, DE,
H, L, HL,
SP, PC,
};
enum {
ZF, NF, HF, CF,
};
//register base class
//the idea here is to have all registers derive from a single base class.
//this allows construction of opcodes that can take any register as input or output,
//despite the fact that behind-the-scenes, special handling is done for eg: F, AF, HL, etc.
//registers can also be chained together: eg af = 0x0000 writes both a and f.
struct Register {
virtual operator uint() const = 0;
virtual auto operator=(uint x) -> uint = 0;
auto operator=(const Register& x) -> Register& { operator=((uint)x); return *this; }
auto operator++(int) -> uint { uint r = *this; operator=(*this + 1); return r; }
auto operator--(int) -> uint { uint r = *this; operator=(*this - 1); return r; }
auto operator++() -> uint { return operator=(*this + 1); }
auto operator--() -> uint { return operator=(*this - 1); }
auto operator |=(uint x) -> uint { return operator=(*this | x); }
auto operator ^=(uint x) -> uint { return operator=(*this ^ x); }
auto operator &=(uint x) -> uint { return operator=(*this & x); }
auto operator<<=(uint x) -> uint { return operator=(*this << x); }
auto operator>>=(uint x) -> uint { return operator=(*this >> x); }
auto operator +=(uint x) -> uint { return operator=(*this + x); }
auto operator -=(uint x) -> uint { return operator=(*this - x); }
auto operator *=(uint x) -> uint { return operator=(*this * x); }
auto operator /=(uint x) -> uint { return operator=(*this / x); }
auto operator %=(uint x) -> uint { return operator=(*this % x); }
};
struct Register8 : Register {
uint8 data;
operator uint() const { return data; }
auto operator=(uint x) -> uint { return data = x; }
};
struct RegisterF : Register {
bool z, n, h, c;
operator uint() const { return (z << 7) | (n << 6) | (h << 5) | (c << 4); }
auto operator=(uint x) -> uint { z = x & 0x80; n = x & 0x40; h = x & 0x20; c = x & 0x10; return *this; }
bool& operator[](uint r) {
static bool* table[] = {&z, &n, &h, &c};
return *table[r];
}
};
struct Register16 : Register {
uint16 data;
operator uint() const { return data; }
auto operator=(uint x) -> uint { return data = x; }
};
struct RegisterAF : Register {
Register8& hi;
RegisterF& lo;
operator uint() const { return (hi << 8) | (lo << 0); }
auto operator=(uint x) -> uint { hi = x >> 8; lo = x >> 0; return *this; }
RegisterAF(Register8& hi, RegisterF& lo) : hi(hi), lo(lo) {}
};
struct RegisterW : Register {
Register8& hi;
Register8& lo;
operator uint() const { return (hi << 8) | (lo << 0); }
auto operator=(uint x) -> uint { hi = x >> 8; lo = x >> 0; return *this; }
RegisterW(Register8& hi, Register8& lo) : hi(hi), lo(lo) {}
};
struct Registers {
Register8 a;
RegisterF f;
RegisterAF af;
Register8 b;
Register8 c;
RegisterW bc;
Register8 d;
Register8 e;
RegisterW de;
Register8 h;
Register8 l;
RegisterW hl;
Register16 sp;
Register16 pc;
bool halt;
bool stop;
bool ei;
bool ime;
Register& operator[](uint r) {
static Register* const table[] = {&a, &f, &af, &b, &c, &bc, &d, &e, &de, &h, &l, &hl, &sp, &pc};
return *table[r];
}
Registers() : af(a, f), bc(b, c), de(d, e), hl(h, l) {}
} r;

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higan/processor/lr35902-legacy/serialization.cpp Normal file
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auto LR35902::serialize(serializer& s) -> void {
s.integer(r.a.data);
s.integer(r.f.z);
s.integer(r.f.n);
s.integer(r.f.h);
s.integer(r.f.c);
s.integer(r.b.data);
s.integer(r.c.data);
s.integer(r.d.data);
s.integer(r.e.data);
s.integer(r.h.data);
s.integer(r.l.data);
s.integer(r.sp.data);
s.integer(r.pc.data);
s.integer(r.halt);
s.integer(r.stop);
s.integer(r.ei);
s.integer(r.ime);
}

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auto LR35902::ADC(uint8 target, uint8 source) -> uint8 {
uint16 x = target + source + CF;
uint16 y = (uint4)target + (uint4)source + CF;
CF = x > 0xff;
HF = y > 0x0f;
NF = 0;
ZF = (uint8)x == 0;
return x;
}
auto LR35902::ADD(uint8 target, uint8 source) -> uint8 {
uint16 x = target + source;
uint16 y = (uint4)target + (uint4)source;
CF = x > 0xff;
HF = y > 0x0f;
NF = 0;
ZF = (uint8)x == 0;
return x;
}
auto LR35902::AND(uint8 target, uint8 source) -> uint8 {
target &= source;
CF = HF = NF = 0;
ZF = target == 0;
return target;
}
auto LR35902::CP(uint8 target, uint8 source) -> void {
uint16 x = target - source;
uint16 y = (uint4)target - (uint4)source;
CF = x > 0xff;
HF = y > 0x0f;
NF = 1;
ZF = (uint8)x == 0;
}
auto LR35902::OR(uint8 target, uint8 source) -> uint8 {
target |= source;
CF = HF = NF = 0;
ZF = target == 0;
return target;
}
auto LR35902::SBC(uint8 target, uint8 source) -> uint8 {
uint16 x = target - source - CF;
uint16 y = (uint4)target - (uint4)source - CF;
CF = x > 0xff;
HF = y > 0x0f;
NF = 1;
ZF = (uint8)x == 0;
return x;
}
auto LR35902::SUB(uint8 target, uint8 source) -> uint8 {
uint16 x = target - source;
uint16 y = (uint4)target - (uint4)source;
CF = x > 0xff;
HF = y > 0x0f;
NF = 1;
ZF = (uint8)x == 0;
return x;
}
auto LR35902::XOR(uint8 target, uint8 source) -> uint8 {
target ^= source;
CF = HF = NF = 0;
ZF = target == 0;
return target;
}

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auto LR35902::interrupt(uint16 vector) -> void {
io();
io();
io();
r.ime = 0;
write(--r[SP], r[PC] >> 8);
write(--r[SP], r[PC] >> 0);
r[PC] = vector;
}
#define op(id, name, ...) case id: return instruction##name(__VA_ARGS__);
auto LR35902::instruction() -> void {
switch(auto opcode = read(r[PC]++)) {
case 0x00: return op_nop();
case 0x01: return op_ld_rr_nn(BC);
case 0x02: return op_ld_rr_a(BC);
case 0x03: return op_inc_rr(BC);
case 0x04: return op_inc_r(B);
case 0x05: return op_dec_r(B);
case 0x06: return op_ld_r_n(B);
case 0x07: return op_rlca();
case 0x08: return op_ld_nn_sp();
case 0x09: return op_add_hl_rr(BC);
case 0x0a: return op_ld_a_rr(BC);
case 0x0b: return op_dec_rr(BC);
case 0x0c: return op_inc_r(C);
case 0x0d: return op_dec_r(C);
case 0x0e: return op_ld_r_n(C);
case 0x0f: return op_rrca();
case 0x10: return op_stop();
case 0x11: return op_ld_rr_nn(DE);
case 0x12: return op_ld_rr_a(DE);
case 0x13: return op_inc_rr(DE);
case 0x14: return op_inc_r(D);
case 0x15: return op_dec_r(D);
case 0x16: return op_ld_r_n(D);
case 0x17: return op_rla();
case 0x18: return op_jr_n();
case 0x19: return op_add_hl_rr(DE);
case 0x1a: return op_ld_a_rr(DE);
case 0x1b: return op_dec_rr(DE);
case 0x1c: return op_inc_r(E);
case 0x1d: return op_dec_r(E);
case 0x1e: return op_ld_r_n(E);
case 0x1f: return op_rra();
case 0x20: return op_jr_f_n(ZF, 0);
case 0x21: return op_ld_rr_nn(HL);
case 0x22: return op_ldi_hl_a();
case 0x23: return op_inc_rr(HL);
case 0x24: return op_inc_r(H);
case 0x25: return op_dec_r(H);
case 0x26: return op_ld_r_n(H);
case 0x27: return op_daa();
case 0x28: return op_jr_f_n(ZF, 1);
case 0x29: return op_add_hl_rr(HL);
case 0x2a: return op_ldi_a_hl();
case 0x2b: return op_dec_rr(HL);
case 0x2c: return op_inc_r(L);
case 0x2d: return op_dec_r(L);
case 0x2e: return op_ld_r_n(L);
case 0x2f: return op_cpl();
case 0x30: return op_jr_f_n(CF, 0);
case 0x31: return op_ld_rr_nn(SP);
case 0x32: return op_ldd_hl_a();
case 0x33: return op_inc_rr(SP);
case 0x34: return op_inc_hl();
case 0x35: return op_dec_hl();
case 0x36: return op_ld_hl_n();
case 0x37: return op_scf();
case 0x38: return op_jr_f_n(CF, 1);
case 0x39: return op_add_hl_rr(SP);
case 0x3a: return op_ldd_a_hl();
case 0x3b: return op_dec_rr(SP);
case 0x3c: return op_inc_r(A);
case 0x3d: return op_dec_r(A);
case 0x3e: return op_ld_r_n(A);
case 0x3f: return op_ccf();
case 0x40: return op_ld_r_r(B, B);
case 0x41: return op_ld_r_r(B, C);
case 0x42: return op_ld_r_r(B, D);
case 0x43: return op_ld_r_r(B, E);
case 0x44: return op_ld_r_r(B, H);
case 0x45: return op_ld_r_r(B, L);
case 0x46: return op_ld_r_hl(B);
case 0x47: return op_ld_r_r(B, A);
case 0x48: return op_ld_r_r(C, B);
case 0x49: return op_ld_r_r(C, C);
case 0x4a: return op_ld_r_r(C, D);
case 0x4b: return op_ld_r_r(C, E);
case 0x4c: return op_ld_r_r(C, H);
case 0x4d: return op_ld_r_r(C, L);
case 0x4e: return op_ld_r_hl(C);
case 0x4f: return op_ld_r_r(C, A);
case 0x50: return op_ld_r_r(D, B);
case 0x51: return op_ld_r_r(D, C);
case 0x52: return op_ld_r_r(D, D);
case 0x53: return op_ld_r_r(D, E);
case 0x54: return op_ld_r_r(D, H);
case 0x55: return op_ld_r_r(D, L);
case 0x56: return op_ld_r_hl(D);
case 0x57: return op_ld_r_r(D, A);
case 0x58: return op_ld_r_r(E, B);
case 0x59: return op_ld_r_r(E, C);
case 0x5a: return op_ld_r_r(E, D);
case 0x5b: return op_ld_r_r(E, E);
case 0x5c: return op_ld_r_r(E, H);
case 0x5d: return op_ld_r_r(E, L);
case 0x5e: return op_ld_r_hl(E);
case 0x5f: return op_ld_r_r(E, A);
case 0x60: return op_ld_r_r(H, B);
case 0x61: return op_ld_r_r(H, C);
case 0x62: return op_ld_r_r(H, D);
case 0x63: return op_ld_r_r(H, E);
case 0x64: return op_ld_r_r(H, H);
case 0x65: return op_ld_r_r(H, L);
case 0x66: return op_ld_r_hl(H);
case 0x67: return op_ld_r_r(H, A);
case 0x68: return op_ld_r_r(L, B);
case 0x69: return op_ld_r_r(L, C);
case 0x6a: return op_ld_r_r(L, D);
case 0x6b: return op_ld_r_r(L, E);
case 0x6c: return op_ld_r_r(L, H);
case 0x6d: return op_ld_r_r(L, L);
case 0x6e: return op_ld_r_hl(L);
case 0x6f: return op_ld_r_r(L, A);
case 0x70: return op_ld_hl_r(B);
case 0x71: return op_ld_hl_r(C);
case 0x72: return op_ld_hl_r(D);
case 0x73: return op_ld_hl_r(E);
case 0x74: return op_ld_hl_r(H);
case 0x75: return op_ld_hl_r(L);
case 0x76: return op_halt();
case 0x77: return op_ld_hl_r(A);
case 0x78: return op_ld_r_r(A, B);
case 0x79: return op_ld_r_r(A, C);
case 0x7a: return op_ld_r_r(A, D);
case 0x7b: return op_ld_r_r(A, E);
case 0x7c: return op_ld_r_r(A, H);
case 0x7d: return op_ld_r_r(A, L);
case 0x7e: return op_ld_r_hl(A);
case 0x7f: return op_ld_r_r(A, A);
case 0x80: return op_add_a_r(B);
case 0x81: return op_add_a_r(C);
case 0x82: return op_add_a_r(D);
case 0x83: return op_add_a_r(E);
case 0x84: return op_add_a_r(H);
case 0x85: return op_add_a_r(L);
case 0x86: return op_add_a_hl();
case 0x87: return op_add_a_r(A);
case 0x88: return op_adc_a_r(B);
case 0x89: return op_adc_a_r(C);
case 0x8a: return op_adc_a_r(D);
case 0x8b: return op_adc_a_r(E);
case 0x8c: return op_adc_a_r(H);
case 0x8d: return op_adc_a_r(L);
case 0x8e: return op_adc_a_hl();
case 0x8f: return op_adc_a_r(A);
case 0x90: return op_sub_a_r(B);
case 0x91: return op_sub_a_r(C);
case 0x92: return op_sub_a_r(D);
case 0x93: return op_sub_a_r(E);
case 0x94: return op_sub_a_r(H);
case 0x95: return op_sub_a_r(L);
case 0x96: return op_sub_a_hl();
case 0x97: return op_sub_a_r(A);
case 0x98: return op_sbc_a_r(B);
case 0x99: return op_sbc_a_r(C);
case 0x9a: return op_sbc_a_r(D);
case 0x9b: return op_sbc_a_r(E);
case 0x9c: return op_sbc_a_r(H);
case 0x9d: return op_sbc_a_r(L);
case 0x9e: return op_sbc_a_hl();
case 0x9f: return op_sbc_a_r(A);
case 0xa0: return op_and_a_r(B);
case 0xa1: return op_and_a_r(C);
case 0xa2: return op_and_a_r(D);
case 0xa3: return op_and_a_r(E);
case 0xa4: return op_and_a_r(H);
case 0xa5: return op_and_a_r(L);
case 0xa6: return op_and_a_hl();
case 0xa7: return op_and_a_r(A);
case 0xa8: return op_xor_a_r(B);
case 0xa9: return op_xor_a_r(C);
case 0xaa: return op_xor_a_r(D);
case 0xab: return op_xor_a_r(E);
case 0xac: return op_xor_a_r(H);
case 0xad: return op_xor_a_r(L);
case 0xae: return op_xor_a_hl();
case 0xaf: return op_xor_a_r(A);
case 0xb0: return op_or_a_r(B);
case 0xb1: return op_or_a_r(C);
case 0xb2: return op_or_a_r(D);
case 0xb3: return op_or_a_r(E);
case 0xb4: return op_or_a_r(H);
case 0xb5: return op_or_a_r(L);
case 0xb6: return op_or_a_hl();
case 0xb7: return op_or_a_r(A);
case 0xb8: return op_cp_a_r(B);
case 0xb9: return op_cp_a_r(C);
case 0xba: return op_cp_a_r(D);
case 0xbb: return op_cp_a_r(E);
case 0xbc: return op_cp_a_r(H);
case 0xbd: return op_cp_a_r(L);
case 0xbe: return op_cp_a_hl();
case 0xbf: return op_cp_a_r(A);
case 0xc0: return op_ret_f(ZF, 0);
case 0xc1: return op_pop_rr(BC);
case 0xc2: return op_jp_f_nn(ZF, 0);
case 0xc3: return op_jp_nn();
case 0xc4: return op_call_f_nn(ZF, 0);
case 0xc5: return op_push_rr(BC);
case 0xc6: return op_add_a_n();
case 0xc7: return op_rst_n(0x00);
case 0xc8: return op_ret_f(ZF, 1);
case 0xc9: return op_ret();
case 0xca: return op_jp_f_nn(ZF, 1);
case 0xcb: return op_cb();
case 0xcc: return op_call_f_nn(ZF, 1);
case 0xcd: return op_call_nn();
case 0xce: return op_adc_a_n();
case 0xcf: return op_rst_n(0x08);
case 0xd0: return op_ret_f(CF, 0);
case 0xd1: return op_pop_rr(DE);
case 0xd2: return op_jp_f_nn(CF, 0);
case 0xd3: return op_xx();
case 0xd4: return op_call_f_nn(CF, 0);
case 0xd5: return op_push_rr(DE);
case 0xd6: return op_sub_a_n();
case 0xd7: return op_rst_n(0x10);
case 0xd8: return op_ret_f(CF, 1);
case 0xd9: return op_reti();
case 0xda: return op_jp_f_nn(CF, 1);
case 0xdb: return op_xx();
case 0xdc: return op_call_f_nn(CF, 1);
case 0xdd: return op_xx();
case 0xde: return op_sbc_a_n();
case 0xdf: return op_rst_n(0x18);
case 0xe0: return op_ld_ffn_a();
case 0xe1: return op_pop_rr(HL);
case 0xe2: return op_ld_ffc_a();
case 0xe3: return op_xx();
case 0xe4: return op_xx();
case 0xe5: return op_push_rr(HL);
case 0xe6: return op_and_a_n();
case 0xe7: return op_rst_n(0x20);
case 0xe8: return op_add_sp_n();
case 0xe9: return op_jp_hl();
case 0xea: return op_ld_nn_a();
case 0xeb: return op_xx();
case 0xec: return op_xx();
case 0xed: return op_xx();
case 0xee: return op_xor_a_n();
case 0xef: return op_rst_n(0x28);
case 0xf0: return op_ld_a_ffn();
case 0xf1: return op_pop_rr(AF);
case 0xf2: return op_ld_a_ffc();
case 0xf3: return op_di();
case 0xf4: return op_xx();
case 0xf5: return op_push_rr(AF);
case 0xf6: return op_or_a_n();
case 0xf7: return op_rst_n(0x30);
case 0xf8: return op_ld_hl_sp_n();
case 0xf9: return op_ld_sp_hl();
case 0xfa: return op_ld_a_nn();
case 0xfb: return op_ei();
case 0xfc: return op_xx();
case 0xfd: return op_xx();
case 0xfe: return op_cp_a_n();
case 0xff: return op_rst_n(0x38);
switch(auto opcode = operand()) {
op(0x00, NOP)
op(0x01, LD_Direct_Data, BC)
op(0x02, LD_Indirect_Direct, BC, A)
op(0x03, INC_Direct, BC)
op(0x04, INC_Direct, B)
op(0x05, DEC_Direct, B)
op(0x06, LD_Direct_Data, B)
op(0x07, RLC_Direct, A)
op(0x08, LD_Address_Direct, SP)
op(0x09, ADD_Direct_Direct, HL, BC)
op(0x0a, LD_Direct_Indirect, A, BC)
op(0x0b, DEC_Direct, BC)
op(0x0c, INC_Direct, C)
op(0x0d, DEC_Direct, C)
op(0x0e, LD_Direct_Data, C)
op(0x0f, RRC_Direct, A)
op(0x10, STOP)
op(0x11, LD_Direct_Data, DE)
op(0x12, LD_Indirect_Direct, DE, A)
op(0x13, INC_Direct, DE)
op(0x14, INC_Direct, D)
op(0x15, DEC_Direct, D)
op(0x16, LD_Direct_Data, D)
op(0x17, RL_Direct, A)
op(0x18, JR_Condition_Relative, 1)
op(0x19, ADD_Direct_Direct, HL, DE)
op(0x1a, LD_Direct_Indirect, A, DE)
op(0x1b, DEC_Direct, DE)
op(0x1c, INC_Direct, E)
op(0x1d, DEC_Direct, E)
op(0x1e, LD_Direct_Data, E)
op(0x1f, RR_Direct, A)
op(0x20, JR_Condition_Relative, ZF == 0)
op(0x21, LD_Direct_Data, HL)
op(0x22, LD_IndirectIncrement_Direct, HL, A)
op(0x23, INC_Direct, HL)
op(0x24, INC_Direct, H)
op(0x25, DEC_Direct, H)
op(0x26, LD_Direct_Data, H)
op(0x27, DAA)
op(0x28, JR_Condition_Relative, ZF == 1)
op(0x29, ADD_Direct_Direct, HL, HL)
op(0x2a, LD_Direct_IndirectIncrement, A, HL)
op(0x2b, DEC_Direct, HL)
op(0x2c, INC_Direct, L)
op(0x2d, DEC_Direct, L)
op(0x2e, LD_Direct_Data, L)
op(0x2f, CPL)
op(0x30, JR_Condition_Relative, CF == 0)
op(0x31, LD_Direct_Data, SP)
op(0x32, LD_IndirectDecrement_Direct, HL, A)
op(0x33, INC_Direct, SP)
op(0x34, INC_Indirect, HL)
op(0x35, DEC_Indirect, HL)
op(0x36, LD_Indirect_Data, HL)
op(0x37, SCF)
op(0x38, JR_Condition_Relative, CF == 1)
op(0x39, ADD_Direct_Direct, HL, SP)
op(0x3a, LD_Direct_IndirectDecrement, A, HL)
op(0x3b, DEC_Direct, SP)
op(0x3c, INC_Direct, A)
op(0x3d, DEC_Direct, A)
op(0x3e, LD_Direct_Data, A)
op(0x3f, CCF)
op(0x40, LD_Direct_Direct, B, B)
op(0x41, LD_Direct_Direct, B, C)
op(0x42, LD_Direct_Direct, B, D)
op(0x43, LD_Direct_Direct, B, E)
op(0x44, LD_Direct_Direct, B, H)
op(0x45, LD_Direct_Direct, B, L)
op(0x46, LD_Direct_Indirect, B, HL)
op(0x47, LD_Direct_Direct, B, A)
op(0x48, LD_Direct_Direct, C, B)
op(0x49, LD_Direct_Direct, C, C)
op(0x4a, LD_Direct_Direct, C, D)
op(0x4b, LD_Direct_Direct, C, E)
op(0x4c, LD_Direct_Direct, C, H)
op(0x4d, LD_Direct_Direct, C, L)
op(0x4e, LD_Direct_Indirect, C, HL)
op(0x4f, LD_Direct_Direct, C, A)
op(0x50, LD_Direct_Direct, D, B)
op(0x51, LD_Direct_Direct, D, C)
op(0x52, LD_Direct_Direct, D, D)
op(0x53, LD_Direct_Direct, D, E)
op(0x54, LD_Direct_Direct, D, H)
op(0x55, LD_Direct_Direct, D, L)
op(0x56, LD_Direct_Indirect, D, HL)
op(0x57, LD_Direct_Direct, D, A)
op(0x58, LD_Direct_Direct, E, B)
op(0x59, LD_Direct_Direct, E, C)
op(0x5a, LD_Direct_Direct, E, D)
op(0x5b, LD_Direct_Direct, E, E)
op(0x5c, LD_Direct_Direct, E, H)
op(0x5d, LD_Direct_Direct, E, L)
op(0x5e, LD_Direct_Indirect, E, HL)
op(0x5f, LD_Direct_Direct, E, A)
op(0x60, LD_Direct_Direct, H, B)
op(0x61, LD_Direct_Direct, H, C)
op(0x62, LD_Direct_Direct, H, D)
op(0x63, LD_Direct_Direct, H, E)
op(0x64, LD_Direct_Direct, H, H)
op(0x65, LD_Direct_Direct, H, L)
op(0x66, LD_Direct_Indirect, H, HL)
op(0x67, LD_Direct_Direct, H, A)
op(0x68, LD_Direct_Direct, L, B)
op(0x69, LD_Direct_Direct, L, C)
op(0x6a, LD_Direct_Direct, L, D)
op(0x6b, LD_Direct_Direct, L, E)
op(0x6c, LD_Direct_Direct, L, H)
op(0x6d, LD_Direct_Direct, L, L)
op(0x6e, LD_Direct_Indirect, L, HL)
op(0x6f, LD_Direct_Direct, L, A)
op(0x70, LD_Indirect_Direct, HL, B)
op(0x71, LD_Indirect_Direct, HL, C)
op(0x72, LD_Indirect_Direct, HL, D)
op(0x73, LD_Indirect_Direct, HL, E)
op(0x74, LD_Indirect_Direct, HL, H)
op(0x75, LD_Indirect_Direct, HL, L)
op(0x76, HALT)
op(0x77, LD_Indirect_Direct, HL, A)
op(0x78, LD_Direct_Direct, A, B)
op(0x79, LD_Direct_Direct, A, C)
op(0x7a, LD_Direct_Direct, A, D)
op(0x7b, LD_Direct_Direct, A, E)
op(0x7c, LD_Direct_Direct, A, H)
op(0x7d, LD_Direct_Direct, A, L)
op(0x7e, LD_Direct_Indirect, A, HL)
op(0x7f, LD_Direct_Direct, A, A)
op(0x80, ADD_Direct_Direct, A, B)
op(0x81, ADD_Direct_Direct, A, C)
op(0x82, ADD_Direct_Direct, A, D)
op(0x83, ADD_Direct_Direct, A, E)
op(0x84, ADD_Direct_Direct, A, H)
op(0x85, ADD_Direct_Direct, A, L)
op(0x86, ADD_Direct_Indirect, A, HL)
op(0x87, ADD_Direct_Direct, A, A)
op(0x88, ADC_Direct_Direct, A, B)
op(0x89, ADC_Direct_Direct, A, C)
op(0x8a, ADC_Direct_Direct, A, D)
op(0x8b, ADC_Direct_Direct, A, E)
op(0x8c, ADC_Direct_Direct, A, H)
op(0x8d, ADC_Direct_Direct, A, L)
op(0x8e, ADC_Direct_Indirect, A, HL)
op(0x8f, ADC_Direct_Direct, A, A)
op(0x90, SUB_Direct_Direct, A, B)
op(0x91, SUB_Direct_Direct, A, C)
op(0x92, SUB_Direct_Direct, A, D)
op(0x93, SUB_Direct_Direct, A, E)
op(0x94, SUB_Direct_Direct, A, H)
op(0x95, SUB_Direct_Direct, A, L)
op(0x96, SUB_Direct_Indirect, A, HL)
op(0x97, SUB_Direct_Direct, A, A)
op(0x98, SBC_Direct_Direct, A, B)
op(0x99, SBC_Direct_Direct, A, C)
op(0x9a, SBC_Direct_Direct, A, D)
op(0x9b, SBC_Direct_Direct, A, E)
op(0x9c, SBC_Direct_Direct, A, H)
op(0x9d, SBC_Direct_Direct, A, L)
op(0x9e, SBC_Direct_Indirect, A, HL)
op(0x9f, SBC_Direct_Direct, A, A)
op(0xa0, AND_Direct_Direct, A, B)
op(0xa1, AND_Direct_Direct, A, C)
op(0xa2, AND_Direct_Direct, A, D)
op(0xa3, AND_Direct_Direct, A, E)
op(0xa4, AND_Direct_Direct, A, H)
op(0xa5, AND_Direct_Direct, A, L)
op(0xa6, AND_Direct_Indirect, A, HL)
op(0xa7, AND_Direct_Direct, A, A)
op(0xa8, XOR_Direct_Direct, A, B)
op(0xa9, XOR_Direct_Direct, A, C)
op(0xaa, XOR_Direct_Direct, A, D)
op(0xab, XOR_Direct_Direct, A, E)
op(0xac, XOR_Direct_Direct, A, H)
op(0xad, XOR_Direct_Direct, A, L)
op(0xae, XOR_Direct_Indirect, A, HL)
op(0xaf, XOR_Direct_Direct, A, A)
op(0xb0, OR_Direct_Direct, A, B)
op(0xb1, OR_Direct_Direct, A, C)
op(0xb2, OR_Direct_Direct, A, D)
op(0xb3, OR_Direct_Direct, A, E)
op(0xb4, OR_Direct_Direct, A, H)
op(0xb5, OR_Direct_Direct, A, L)
op(0xb6, OR_Direct_Indirect, A, HL)
op(0xb7, OR_Direct_Direct, A, A)
op(0xb8, CP_Direct_Direct, A, B)
op(0xb9, CP_Direct_Direct, A, C)
op(0xba, CP_Direct_Direct, A, D)
op(0xbb, CP_Direct_Direct, A, E)
op(0xbc, CP_Direct_Direct, A, H)
op(0xbd, CP_Direct_Direct, A, L)
op(0xbe, CP_Direct_Indirect, A, HL)
op(0xbf, CP_Direct_Direct, A, A)
op(0xc0, RET_Condition, ZF == 0)
op(0xc6, ADD_Direct_Data, A)
op(0xc8, RET_Condition, ZF == 1)
op(0xcb, CB)
op(0xce, ADC_Direct_Data, A)
op(0xd0, RET_Condition, CF == 0)
op(0xd6, SUB_Direct_Data, A)
op(0xd8, RET_Condition, CF == 1)
op(0xde, SBC_Direct_Data, A)
op(0xe2, LD_Indirect_Direct, C, A)
op(0xe6, AND_Direct_Data, A)
op(0xee, XOR_Direct_Data, A)
op(0xf2, LD_Direct_Indirect, A, C)
op(0xf3, DI)
op(0xf6, OR_Direct_Data, A)
op(0xfb, EI)
op(0xfe, CP_Direct_Data, A)
}
}
auto LR35902::instructionCB() -> void {
switch(auto opcode = read(r[PC]++)) {
case 0x00: return op_rlc_r(B);
case 0x01: return op_rlc_r(C);
case 0x02: return op_rlc_r(D);
case 0x03: return op_rlc_r(E);
case 0x04: return op_rlc_r(H);
case 0x05: return op_rlc_r(L);
case 0x06: return op_rlc_hl();
case 0x07: return op_rlc_r(A);
case 0x08: return op_rrc_r(B);
case 0x09: return op_rrc_r(C);
case 0x0a: return op_rrc_r(D);
case 0x0b: return op_rrc_r(E);
case 0x0c: return op_rrc_r(H);
case 0x0d: return op_rrc_r(L);
case 0x0e: return op_rrc_hl();
case 0x0f: return op_rrc_r(A);
case 0x10: return op_rl_r(B);
case 0x11: return op_rl_r(C);
case 0x12: return op_rl_r(D);
case 0x13: return op_rl_r(E);
case 0x14: return op_rl_r(H);
case 0x15: return op_rl_r(L);
case 0x16: return op_rl_hl();
case 0x17: return op_rl_r(A);
case 0x18: return op_rr_r(B);
case 0x19: return op_rr_r(C);
case 0x1a: return op_rr_r(D);
case 0x1b: return op_rr_r(E);
case 0x1c: return op_rr_r(H);
case 0x1d: return op_rr_r(L);
case 0x1e: return op_rr_hl();
case 0x1f: return op_rr_r(A);
case 0x20: return op_sla_r(B);
case 0x21: return op_sla_r(C);
case 0x22: return op_sla_r(D);
case 0x23: return op_sla_r(E);
case 0x24: return op_sla_r(H);
case 0x25: return op_sla_r(L);
case 0x26: return op_sla_hl();
case 0x27: return op_sla_r(A);
case 0x28: return op_sra_r(B);
case 0x29: return op_sra_r(C);
case 0x2a: return op_sra_r(D);
case 0x2b: return op_sra_r(E);
case 0x2c: return op_sra_r(H);
case 0x2d: return op_sra_r(L);
case 0x2e: return op_sra_hl();
case 0x2f: return op_sra_r(A);
case 0x30: return op_swap_r(B);
case 0x31: return op_swap_r(C);
case 0x32: return op_swap_r(D);
case 0x33: return op_swap_r(E);
case 0x34: return op_swap_r(H);
case 0x35: return op_swap_r(L);
case 0x36: return op_swap_hl();
case 0x37: return op_swap_r(A);
case 0x38: return op_srl_r(B);
case 0x39: return op_srl_r(C);
case 0x3a: return op_srl_r(D);
case 0x3b: return op_srl_r(E);
case 0x3c: return op_srl_r(H);
case 0x3d: return op_srl_r(L);
case 0x3e: return op_srl_hl();
case 0x3f: return op_srl_r(A);
case 0x40: return op_bit_n_r(0, B);
case 0x41: return op_bit_n_r(0, C);
case 0x42: return op_bit_n_r(0, D);
case 0x43: return op_bit_n_r(0, E);
case 0x44: return op_bit_n_r(0, H);
case 0x45: return op_bit_n_r(0, L);
case 0x46: return op_bit_n_hl(0);
case 0x47: return op_bit_n_r(0, A);
case 0x48: return op_bit_n_r(1, B);
case 0x49: return op_bit_n_r(1, C);
case 0x4a: return op_bit_n_r(1, D);
case 0x4b: return op_bit_n_r(1, E);
case 0x4c: return op_bit_n_r(1, H);
case 0x4d: return op_bit_n_r(1, L);
case 0x4e: return op_bit_n_hl(1);
case 0x4f: return op_bit_n_r(1, A);
case 0x50: return op_bit_n_r(2, B);
case 0x51: return op_bit_n_r(2, C);
case 0x52: return op_bit_n_r(2, D);
case 0x53: return op_bit_n_r(2, E);
case 0x54: return op_bit_n_r(2, H);
case 0x55: return op_bit_n_r(2, L);
case 0x56: return op_bit_n_hl(2);
case 0x57: return op_bit_n_r(2, A);
case 0x58: return op_bit_n_r(3, B);
case 0x59: return op_bit_n_r(3, C);
case 0x5a: return op_bit_n_r(3, D);
case 0x5b: return op_bit_n_r(3, E);
case 0x5c: return op_bit_n_r(3, H);
case 0x5d: return op_bit_n_r(3, L);
case 0x5e: return op_bit_n_hl(3);
case 0x5f: return op_bit_n_r(3, A);
case 0x60: return op_bit_n_r(4, B);
case 0x61: return op_bit_n_r(4, C);
case 0x62: return op_bit_n_r(4, D);
case 0x63: return op_bit_n_r(4, E);
case 0x64: return op_bit_n_r(4, H);
case 0x65: return op_bit_n_r(4, L);
case 0x66: return op_bit_n_hl(4);
case 0x67: return op_bit_n_r(4, A);
case 0x68: return op_bit_n_r(5, B);
case 0x69: return op_bit_n_r(5, C);
case 0x6a: return op_bit_n_r(5, D);
case 0x6b: return op_bit_n_r(5, E);
case 0x6c: return op_bit_n_r(5, H);
case 0x6d: return op_bit_n_r(5, L);
case 0x6e: return op_bit_n_hl(5);
case 0x6f: return op_bit_n_r(5, A);
case 0x70: return op_bit_n_r(6, B);
case 0x71: return op_bit_n_r(6, C);
case 0x72: return op_bit_n_r(6, D);
case 0x73: return op_bit_n_r(6, E);
case 0x74: return op_bit_n_r(6, H);
case 0x75: return op_bit_n_r(6, L);
case 0x76: return op_bit_n_hl(6);
case 0x77: return op_bit_n_r(6, A);
case 0x78: return op_bit_n_r(7, B);
case 0x79: return op_bit_n_r(7, C);
case 0x7a: return op_bit_n_r(7, D);
case 0x7b: return op_bit_n_r(7, E);
case 0x7c: return op_bit_n_r(7, H);
case 0x7d: return op_bit_n_r(7, L);
case 0x7e: return op_bit_n_hl(7);
case 0x7f: return op_bit_n_r(7, A);
case 0x80: return op_res_n_r(0, B);
case 0x81: return op_res_n_r(0, C);
case 0x82: return op_res_n_r(0, D);
case 0x83: return op_res_n_r(0, E);
case 0x84: return op_res_n_r(0, H);
case 0x85: return op_res_n_r(0, L);
case 0x86: return op_res_n_hl(0);
case 0x87: return op_res_n_r(0, A);
case 0x88: return op_res_n_r(1, B);
case 0x89: return op_res_n_r(1, C);
case 0x8a: return op_res_n_r(1, D);
case 0x8b: return op_res_n_r(1, E);
case 0x8c: return op_res_n_r(1, H);
case 0x8d: return op_res_n_r(1, L);
case 0x8e: return op_res_n_hl(1);
case 0x8f: return op_res_n_r(1, A);
case 0x90: return op_res_n_r(2, B);
case 0x91: return op_res_n_r(2, C);
case 0x92: return op_res_n_r(2, D);
case 0x93: return op_res_n_r(2, E);
case 0x94: return op_res_n_r(2, H);
case 0x95: return op_res_n_r(2, L);
case 0x96: return op_res_n_hl(2);
case 0x97: return op_res_n_r(2, A);
case 0x98: return op_res_n_r(3, B);
case 0x99: return op_res_n_r(3, C);
case 0x9a: return op_res_n_r(3, D);
case 0x9b: return op_res_n_r(3, E);
case 0x9c: return op_res_n_r(3, H);
case 0x9d: return op_res_n_r(3, L);
case 0x9e: return op_res_n_hl(3);
case 0x9f: return op_res_n_r(3, A);
case 0xa0: return op_res_n_r(4, B);
case 0xa1: return op_res_n_r(4, C);
case 0xa2: return op_res_n_r(4, D);
case 0xa3: return op_res_n_r(4, E);
case 0xa4: return op_res_n_r(4, H);
case 0xa5: return op_res_n_r(4, L);
case 0xa6: return op_res_n_hl(4);
case 0xa7: return op_res_n_r(4, A);
case 0xa8: return op_res_n_r(5, B);
case 0xa9: return op_res_n_r(5, C);
case 0xaa: return op_res_n_r(5, D);
case 0xab: return op_res_n_r(5, E);
case 0xac: return op_res_n_r(5, H);
case 0xad: return op_res_n_r(5, L);
case 0xae: return op_res_n_hl(5);
case 0xaf: return op_res_n_r(5, A);
case 0xb0: return op_res_n_r(6, B);
case 0xb1: return op_res_n_r(6, C);
case 0xb2: return op_res_n_r(6, D);
case 0xb3: return op_res_n_r(6, E);
case 0xb4: return op_res_n_r(6, H);
case 0xb5: return op_res_n_r(6, L);
case 0xb6: return op_res_n_hl(6);
case 0xb7: return op_res_n_r(6, A);
case 0xb8: return op_res_n_r(7, B);
case 0xb9: return op_res_n_r(7, C);
case 0xba: return op_res_n_r(7, D);
case 0xbb: return op_res_n_r(7, E);
case 0xbc: return op_res_n_r(7, H);
case 0xbd: return op_res_n_r(7, L);
case 0xbe: return op_res_n_hl(7);
case 0xbf: return op_res_n_r(7, A);
case 0xc0: return op_set_n_r(0, B);
case 0xc1: return op_set_n_r(0, C);
case 0xc2: return op_set_n_r(0, D);
case 0xc3: return op_set_n_r(0, E);
case 0xc4: return op_set_n_r(0, H);
case 0xc5: return op_set_n_r(0, L);
case 0xc6: return op_set_n_hl(0);
case 0xc7: return op_set_n_r(0, A);
case 0xc8: return op_set_n_r(1, B);
case 0xc9: return op_set_n_r(1, C);
case 0xca: return op_set_n_r(1, D);
case 0xcb: return op_set_n_r(1, E);
case 0xcc: return op_set_n_r(1, H);
case 0xcd: return op_set_n_r(1, L);
case 0xce: return op_set_n_hl(1);
case 0xcf: return op_set_n_r(1, A);
case 0xd0: return op_set_n_r(2, B);
case 0xd1: return op_set_n_r(2, C);
case 0xd2: return op_set_n_r(2, D);
case 0xd3: return op_set_n_r(2, E);
case 0xd4: return op_set_n_r(2, H);
case 0xd5: return op_set_n_r(2, L);
case 0xd6: return op_set_n_hl(2);
case 0xd7: return op_set_n_r(2, A);
case 0xd8: return op_set_n_r(3, B);
case 0xd9: return op_set_n_r(3, C);
case 0xda: return op_set_n_r(3, D);
case 0xdb: return op_set_n_r(3, E);
case 0xdc: return op_set_n_r(3, H);
case 0xdd: return op_set_n_r(3, L);
case 0xde: return op_set_n_hl(3);
case 0xdf: return op_set_n_r(3, A);
case 0xe0: return op_set_n_r(4, B);
case 0xe1: return op_set_n_r(4, C);
case 0xe2: return op_set_n_r(4, D);
case 0xe3: return op_set_n_r(4, E);
case 0xe4: return op_set_n_r(4, H);
case 0xe5: return op_set_n_r(4, L);
case 0xe6: return op_set_n_hl(4);
case 0xe7: return op_set_n_r(4, A);
case 0xe8: return op_set_n_r(5, B);
case 0xe9: return op_set_n_r(5, C);
case 0xea: return op_set_n_r(5, D);
case 0xeb: return op_set_n_r(5, E);
case 0xec: return op_set_n_r(5, H);
case 0xed: return op_set_n_r(5, L);
case 0xee: return op_set_n_hl(5);
case 0xef: return op_set_n_r(5, A);
case 0xf0: return op_set_n_r(6, B);
case 0xf1: return op_set_n_r(6, C);
case 0xf2: return op_set_n_r(6, D);
case 0xf3: return op_set_n_r(6, E);
case 0xf4: return op_set_n_r(6, H);
case 0xf5: return op_set_n_r(6, L);
case 0xf6: return op_set_n_hl(6);
case 0xf7: return op_set_n_r(6, A);
case 0xf8: return op_set_n_r(7, B);
case 0xf9: return op_set_n_r(7, C);
case 0xfa: return op_set_n_r(7, D);
case 0xfb: return op_set_n_r(7, E);
case 0xfc: return op_set_n_r(7, H);
case 0xfd: return op_set_n_r(7, L);
case 0xfe: return op_set_n_hl(7);
case 0xff: return op_set_n_r(7, A);
switch(auto opcode = operand()) {
}
}
#undef op

824
higan/processor/lr35902/instructions.cpp
View File

@ -1,668 +1,292 @@
auto LR35902::op_xx() {
auto LR35902::instructionADC_Direct_Data(uint8& target) -> void {
target = ADC(target, operand());
}
auto LR35902::op_cb() {
instructionCB();
auto LR35902::instructionADC_Direct_Direct(uint8& target, uint8& source) -> void {
target = ADC(target, source);
}
//8-bit load commands
auto LR35902::op_ld_r_r(uint x, uint y) {
r[x] = r[y];
auto LR35902::instructionADC_Direct_Indirect(uint8& target, uint16& source) -> void {
target = ADC(target, read(source));
}
auto LR35902::op_ld_r_n(uint x) {
r[x] = read(r[PC]++);
auto LR35902::instructionADD_Direct_Data(uint8& target) -> void {
target = ADD(target, operand());
}
auto LR35902::op_ld_r_hl(uint x) {
r[x] = read(r[HL]);
auto LR35902::instructionADD_Direct_Direct(uint8& target, uint8& source) -> void {
target = ADD(target, source);
}
auto LR35902::op_ld_hl_r(uint x) {
write(r[HL], r[x]);
auto LR35902::instructionADD_Direct_Direct(uint16& target, uint16& source) -> void {
idle();
uint32 x = target + source;
uint32 y = (uint12)target + (uint12)source;
target = x;
CF = x > 0xffff;
HF = y > 0x0fff;
NF = 0;
}
auto LR35902::op_ld_hl_n() {
write(r[HL], read(r[PC]++));
auto LR35902::instructionADD_Direct_Indirect(uint8& target, uint16& source) -> void {
target = ADD(target, read(source));
}
auto LR35902::op_ld_a_rr(uint x) {
r[A] = read(r[x]);
auto LR35902::instructionAND_Direct_Data(uint8& target) -> void {
target = AND(target, operand());
}
auto LR35902::op_ld_a_nn() {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
r[A] = read((hi << 8) | (lo << 0));
auto LR35902::instructionAND_Direct_Direct(uint8& target, uint8& source) -> void {
target = AND(target, source);
}
auto LR35902::op_ld_rr_a(uint x) {
write(r[x], r[A]);
auto LR35902::instructionAND_Direct_Indirect(uint8& target, uint16& source) -> void {
target = AND(target, read(source));
}
auto LR35902::op_ld_nn_a() {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
write((hi << 8) | (lo << 0), r[A]);
auto LR35902::instructionCCF() -> void {
CF = !CF;
HF = NF = 0;
}
auto LR35902::op_ld_a_ffn() {
r[A] = read(0xff00 + read(r[PC]++));
auto LR35902::instructionCP_Direct_Data(uint8& target) -> void {
CP(target, operand());
}
auto LR35902::op_ld_ffn_a() {
write(0xff00 + read(r[PC]++), r[A]);
auto LR35902::instructionCP_Direct_Direct(uint8& target, uint8& source) -> void {
CP(target, source);
}
auto LR35902::op_ld_a_ffc() {
r[A] = read(0xff00 + r[C]);
auto LR35902::instructionCP_Direct_Indirect(uint8& target, uint16& source) -> void {
CP(target, read(source));
}
auto LR35902::op_ld_ffc_a() {
write(0xff00 + r[C], r[A]);
auto LR35902::instructionCPL() -> void {
A = ~A;
HF = NF = 1;
}
auto LR35902::op_ldi_hl_a() {
write(r[HL], r[A]);
r[HL]++;
}
auto LR35902::op_ldi_a_hl() {
r[A] = read(r[HL]);
r[HL]++;
}
auto LR35902::op_ldd_hl_a() {
write(r[HL], r[A]);
r[HL]--;
}
auto LR35902::op_ldd_a_hl() {
r[A] = read(r[HL]);
r[HL]--;
}
//16-bit load commands
auto LR35902::op_ld_rr_nn(uint x) {
r[x] = read(r[PC]++) << 0;
r[x] |= read(r[PC]++) << 8;
}
auto LR35902::op_ld_nn_sp() {
uint16 addr = read(r[PC]++) << 0;
addr |= read(r[PC]++) << 8;
write(addr + 0, r[SP] >> 0);
write(addr + 1, r[SP] >> 8);
}
auto LR35902::op_ld_sp_hl() {
r[SP] = r[HL];
io();
}
auto LR35902::op_push_rr(uint x) {
io();
write(--r[SP], r[x] >> 8);
write(--r[SP], r[x] >> 0);
}
auto LR35902::op_pop_rr(uint x) {
r[x] = read(r[SP]++) << 0;
r[x] |= read(r[SP]++) << 8;
}
//8-bit arithmetic commands
auto LR35902::opi_add_a(uint8 x) {
uint16 rh = r[A] + x;
uint16 rl = (r[A] & 0x0f) + (x & 0x0f);
r[A] = rh;
r.f.z = (uint8)rh == 0;
r.f.n = 0;
r.f.h = rl > 0x0f;
r.f.c = rh > 0xff;
}
auto LR35902::op_add_a_r(uint x) { opi_add_a(r[x]); }
auto LR35902::op_add_a_n() { opi_add_a(read(r[PC]++)); }
auto LR35902::op_add_a_hl() { opi_add_a(read(r[HL])); }
auto LR35902::opi_adc_a(uint8 x) {
uint16 rh = r[A] + x + r.f.c;
uint16 rl = (r[A] & 0x0f) + (x & 0x0f) + r.f.c;
r[A] = rh;
r.f.z = (uint8)rh == 0;
r.f.n = 0;
r.f.h = rl > 0x0f;
r.f.c = rh > 0xff;
}
auto LR35902::op_adc_a_r(uint x) { opi_adc_a(r[x]); }
auto LR35902::op_adc_a_n() { opi_adc_a(read(r[PC]++)); }
auto LR35902::op_adc_a_hl() { opi_adc_a(read(r[HL])); }
auto LR35902::opi_sub_a(uint8 x) {
uint16 rh = r[A] - x;
uint16 rl = (r[A] & 0x0f) - (x & 0x0f);
r[A] = rh;
r.f.z = (uint8)rh == 0;
r.f.n = 1;
r.f.h = rl > 0x0f;
r.f.c = rh > 0xff;
}
auto LR35902::op_sub_a_r(uint x) { opi_sub_a(r[x]); }
auto LR35902::op_sub_a_n() { opi_sub_a(read(r[PC]++)); }
auto LR35902::op_sub_a_hl() { opi_sub_a(read(r[HL])); }
auto LR35902::opi_sbc_a(uint8 x) {
uint16 rh = r[A] - x - r.f.c;
uint16 rl = (r[A] & 0x0f) - (x & 0x0f) - r.f.c;
r[A] = rh;
r.f.z = (uint8)rh == 0;
r.f.n = 1;
r.f.h = rl > 0x0f;
r.f.c = rh > 0xff;
}
auto LR35902::op_sbc_a_r(uint x) { opi_sbc_a(r[x]); }
auto LR35902::op_sbc_a_n() { opi_sbc_a(read(r[PC]++)); }
auto LR35902::op_sbc_a_hl() { opi_sbc_a(read(r[HL])); }
auto LR35902::opi_and_a(uint8 x) {
r[A] &= x;
r.f.z = r[A] == 0;
r.f.n = 0;
r.f.h = 1;
r.f.c = 0;
}
auto LR35902::op_and_a_r(uint x) { opi_and_a(r[x]); }
auto LR35902::op_and_a_n() { opi_and_a(read(r[PC]++)); }
auto LR35902::op_and_a_hl() { opi_and_a(read(r[HL])); }
auto LR35902::opi_xor_a(uint8 x) {
r[A] ^= x;
r.f.z = r[A] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = 0;
}
auto LR35902::op_xor_a_r(uint x) { opi_xor_a(r[x]); }
auto LR35902::op_xor_a_n() { opi_xor_a(read(r[PC]++)); }
auto LR35902::op_xor_a_hl() { opi_xor_a(read(r[HL])); }
auto LR35902::opi_or_a(uint8 x) {
r[A] |= x;
r.f.z = r[A] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = 0;
}
auto LR35902::op_or_a_r(uint x) { opi_or_a(r[x]); }
auto LR35902::op_or_a_n() { opi_or_a(read(r[PC]++)); }
auto LR35902::op_or_a_hl() { opi_or_a(read(r[HL])); }
auto LR35902::opi_cp_a(uint8 x) {
uint16 rh = r[A] - x;
uint16 rl = (r[A] & 0x0f) - (x & 0x0f);
r.f.z = (uint8)rh == 0;
r.f.n = 1;
r.f.h = rl > 0x0f;
r.f.c = rh > 0xff;
}
auto LR35902::op_cp_a_r(uint x) { opi_cp_a(r[x]); }
auto LR35902::op_cp_a_n() { opi_cp_a(read(r[PC]++)); }
auto LR35902::op_cp_a_hl() { opi_cp_a(read(r[HL])); }
auto LR35902::op_inc_r(uint x) {
r[x]++;
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = (r[x] & 0x0f) == 0x00;
}
auto LR35902::op_inc_hl() {
uint8 n = read(r[HL]);
write(r[HL], ++n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = (n & 0x0f) == 0x00;
}
auto LR35902::op_dec_r(uint x) {
r[x]--;
r.f.z = r[x] == 0;
r.f.n = 1;
r.f.h = (r[x] & 0x0f) == 0x0f;
}
auto LR35902::op_dec_hl() {
uint8 n = read(r[HL]);
write(r[HL], --n);
r.f.z = n == 0;
r.f.n = 1;
r.f.h = (n & 0x0f) == 0x0f;
}
auto LR35902::op_daa() {
uint16 a = r[A];
if(r.f.n == 0) {
if(r.f.h || (a & 0x0f) > 0x09) a += 0x06;
if(r.f.c || (a ) > 0x9f) a += 0x60;
auto LR35902::instructionDAA() -> void {
uint16 a = A;
if(!NF) {
if(HF || (uint4)a > 0x09) a += 0x06;
if(CF || (uint8)a > 0x9f) a += 0x60;
} else {
if(r.f.h) {
if(HF) {
a -= 0x06;
if(r.f.c == 0) a &= 0xff;
if(!CF) a &= 0xff;
}
if(r.f.c) a -= 0x60;
if(CF) a -= 0x60;
}
r[A] = a;
r.f.z = r[A] == 0;
r.f.h = 0;
r.f.c |= a & 0x100;
A = a;
CF |= a.bit(8);
HF = 0;
ZF = A == 0;
}
auto LR35902::op_cpl() {
r[A] ^= 0xff;
r.f.n = 1;
r.f.h = 1;
auto LR35902::instructionDEC_Direct(uint8& target) -> void {
target--;
HF = (uint4)target == 15;
NF = 0;
ZF = target == 0;
}
//16-bit arithmetic commands
auto LR35902::op_add_hl_rr(uint x) {
io();
uint32 rb = (r[HL] + r[x]);
uint32 rn = (r[HL] & 0xfff) + (r[x] & 0xfff);
r[HL] = rb;
r.f.n = 0;
r.f.h = rn > 0x0fff;
r.f.c = rb > 0xffff;
auto LR35902::instructionDEC_Direct(uint16& target) -> void {
idle();
target--;
}
auto LR35902::op_inc_rr(uint x) {
io();
r[x]++;
auto LR35902::instructionDEC_Indirect(uint16& target) -> void {
auto data = read(target);
write(target, ++data);
HF = (uint4)data == 15;
NF = 0;
ZF = data == 0;
}
auto LR35902::op_dec_rr(uint x) {
io();
r[x]--;
}
auto LR35902::op_add_sp_n() {
int n = (int8)read(r[PC]++);
r.f.z = 0;
r.f.n = 0;
r.f.h = ((r[SP] & 0x0f) + (n & 0x0f)) > 0x0f;
r.f.c = ((r[SP] & 0xff) + (n & 0xff)) > 0xff;
r[SP] += n;
io();
io();
}
auto LR35902::op_ld_hl_sp_n() {
int n = (int8)read(r[PC]++);
r.f.z = 0;
r.f.n = 0;
r.f.h = ((r[SP] & 0x0f) + (n & 0x0f)) > 0x0f;
r.f.c = ((r[SP] & 0xff) + (n & 0xff)) > 0xff;
r[HL] = r[SP] + n;
io();
}
//rotate/shift commands
auto LR35902::op_rlca() {
r[A] = (r[A] << 1) | (r[A] >> 7);
r.f.z = 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = r[A] & 0x01;
}
auto LR35902::op_rla() {
bool c = r[A] & 0x80;
r[A] = (r[A] << 1) | (r.f.c << 0);
r.f.z = 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_rrca() {
r[A] = (r[A] >> 1) | (r[A] << 7);
r.f.z = 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = r[A] & 0x80;
}
auto LR35902::op_rra() {
bool c = r[A] & 0x01;
r[A] = (r[A] >> 1) | (r.f.c << 7);
r.f.z = 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_rlc_r(uint x) {
r[x] = (r[x] << 1) | (r[x] >> 7);
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = r[x] & 0x01;
}
auto LR35902::op_rlc_hl() {
uint8 n = read(r[HL]);
n = (n << 1) | (n >> 7);
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = n & 0x01;
}
auto LR35902::op_rl_r(uint x) {
bool c = r[x] & 0x80;
r[x] = (r[x] << 1) | (r.f.c << 0);
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_rl_hl() {
uint8 n = read(r[HL]);
bool c = n & 0x80;
n = (n << 1) | (r.f.c << 0);
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_rrc_r(uint x) {
r[x] = (r[x] >> 1) | (r[x] << 7);
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = r[x] & 0x80;
}
auto LR35902::op_rrc_hl() {
uint8 n = read(r[HL]);
n = (n >> 1) | (n << 7);
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = n & 0x80;
}
auto LR35902::op_rr_r(uint x) {
bool c = r[x] & 0x01;
r[x] = (r[x] >> 1) | (r.f.c << 7);
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_rr_hl() {
uint8 n = read(r[HL]);
bool c = n & 0x01;
n = (n >> 1) | (r.f.c << 7);
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_sla_r(uint x) {
bool c = r[x] & 0x80;
r[x] <<= 1;
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_sla_hl() {
uint8 n = read(r[HL]);
bool c = n & 0x80;
n <<= 1;
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_swap_r(uint x) {
r[x] = (r[x] << 4) | (r[x] >> 4);
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = 0;
}
auto LR35902::op_swap_hl() {
uint8 n = read(r[HL]);
n = (n << 4) | (n >> 4);
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = 0;
}
auto LR35902::op_sra_r(uint x) {
bool c = r[x] & 0x01;
r[x] = (int8)r[x] >> 1;
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_sra_hl() {
uint8 n = read(r[HL]);
bool c = n & 0x01;
n = (int8)n >> 1;
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_srl_r(uint x) {
bool c = r[x] & 0x01;
r[x] >>= 1;
r.f.z = r[x] == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
auto LR35902::op_srl_hl() {
uint8 n = read(r[HL]);
bool c = n & 0x01;
n >>= 1;
write(r[HL], n);
r.f.z = n == 0;
r.f.n = 0;
r.f.h = 0;
r.f.c = c;
}
//single-bit commands
auto LR35902::op_bit_n_r(uint b, uint x) {
r.f.z = (r[x] & (1 << b)) == 0;
r.f.n = 0;
r.f.h = 1;
}
auto LR35902::op_bit_n_hl(uint b) {
uint8 n = read(r[HL]);
r.f.z = (n & (1 << b)) == 0;
r.f.n = 0;
r.f.h = 1;
}
auto LR35902::op_set_n_r(uint b, uint x) {
r[x] |= 1 << b;
}
auto LR35902::op_set_n_hl(uint b) {
uint8 n = read(r[HL]);
n |= 1 << b;
write(r[HL], n);
}
auto LR35902::op_res_n_r(uint b, uint x) {
r[x] &= ~(1 << b);
}
auto LR35902::op_res_n_hl(uint b) {
uint n = read(r[HL]);
n &= ~(1 << b);
write(r[HL], n);
}
//control commands
auto LR35902::op_ccf() {
r.f.n = 0;
r.f.h = 0;
r.f.c = !r.f.c;
}
auto LR35902::op_scf() {
r.f.n = 0;
r.f.h = 0;
r.f.c = 1;
}
auto LR35902::op_nop() {
}
auto LR35902::op_halt() {
r.halt = true;
while(r.halt) io();
}
auto LR35902::op_stop() {
if(stop()) return;
r.stop = true;
while(r.stop) io();
}
auto LR35902::op_di() {
auto LR35902::instructionDI() -> void {
r.ime = 0;
}
auto LR35902::op_ei() {
r.ei = true;
//r.ime = 1;
auto LR35902::instructionEI() -> void {
r.ei = 1;
}
//jump commands
auto LR35902::op_jp_nn() {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
r[PC] = (hi << 8) | (lo << 0);
io();
auto LR35902::instructionHALT() -> void {
r.halt = 1;
while(r.halt) idle();
}
auto LR35902::op_jp_hl() {
r[PC] = r[HL];
auto LR35902::instructionINC_Direct(uint8& target) -> void {
target++;
HF = (uint4)target == 0;
NF = 0;
ZF = target == 0;
}
auto LR35902::op_jp_f_nn(uint x, bool y) {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
if(r.f[x] == y) {
r[PC] = (hi << 8) | (lo << 0);
io();
}
auto LR35902::instructionINC_Direct(uint16& target) -> void {
idle();
target++;
}
auto LR35902::op_jr_n() {
int8 n = read(r[PC]++);
r[PC] += n;
io();
auto LR35902::instructionINC_Indirect(uint16& target) -> void {
auto data = read(target);
write(target, ++data);
HF = (uint4)data == 0;
NF = 0;
ZF = data == 0;
}
auto LR35902::op_jr_f_n(uint x, bool y) {
int8 n = read(r[PC]++);
if(r.f[x] == y) {
r[PC] += n;
io();
}
auto LR35902::instructionJR_Condition_Relative(bool take) -> void {
auto data = operand();
if(!take) return;
idle();
PC += (int8)data;
}
auto LR35902::op_call_nn() {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
io();
write(--r[SP], r[PC] >> 8);
write(--r[SP], r[PC] >> 0);
r[PC] = (hi << 8) | (lo << 0);
auto LR35902::instructionLD_Address_Direct(uint16& data) -> void {
store(operands(), data);
}
auto LR35902::op_call_f_nn(uint x, bool y) {
uint8 lo = read(r[PC]++);
uint8 hi = read(r[PC]++);
if(r.f[x] == y) {
io();
write(--r[SP], r[PC] >> 8);
write(--r[SP], r[PC] >> 0);
r[PC] = (hi << 8) | (lo << 0);
}
auto LR35902::instructionLD_Direct_Data(uint8& target) -> void {
target = operand();
}
auto LR35902::op_ret() {
uint8 lo = read(r[SP]++);
uint8 hi = read(r[SP]++);
r[PC] = (hi << 8) | (lo << 0);
io();
auto LR35902::instructionLD_Direct_Data(uint16& target) -> void {
target = operands();
}
auto LR35902::op_ret_f(uint x, bool y) {
io();
if(r.f[x] == y) {
uint8 lo = read(r[SP]++);
uint8 hi = read(r[SP]++);
r[PC] = (hi << 8) | (lo << 0);
io();
}
auto LR35902::instructionLD_Direct_Direct(uint8& target, uint8& source) -> void {
target = source;
}
auto LR35902::op_reti() {
uint8 lo = read(r[SP]++);
uint8 hi = read(r[SP]++);
r[PC] = (hi << 8) | (lo << 0);
io();
r.ime = 1;
auto LR35902::instructionLD_Direct_Indirect(uint8& target, uint8& source) -> void {
target = read(0xff00 | source);
}
auto LR35902::op_rst_n(uint n) {
io();
write(--r[SP], r[PC] >> 8);
write(--r[SP], r[PC] >> 0);
r[PC] = n;
auto LR35902::instructionLD_Direct_Indirect(uint8& target, uint16& source) -> void {
target = read(source);
}
auto LR35902::instructionLD_Direct_IndirectDecrement(uint8& target, uint16& source) -> void {
target = read(source--);
}
auto LR35902::instructionLD_Direct_IndirectIncrement(uint8& target, uint16& source) -> void {
target = read(source++);
}
auto LR35902::instructionLD_Indirect_Data(uint16& target) -> void {
write(target, operand());
}
auto LR35902::instructionLD_Indirect_Direct(uint8& target, uint8& source) -> void {
write(0xff00 | target, source);
}
auto LR35902::instructionLD_Indirect_Direct(uint16& target, uint8& source) -> void {
write(target, source);
}
auto LR35902::instructionLD_IndirectDecrement_Direct(uint16& target, uint8& source) -> void {
write(target--, source);
}
auto LR35902::instructionLD_IndirectIncrement_Direct(uint16& target, uint8& source) -> void {
write(target++, source);
}
auto LR35902::instructionNOP() -> void {
}
auto LR35902::instructionOR_Direct_Data(uint8& target) -> void {
target = OR(target, operand());
}
auto LR35902::instructionOR_Direct_Direct(uint8& target, uint8& source) -> void {
target = OR(target, source);
}
auto LR35902::instructionOR_Direct_Indirect(uint8& target, uint16& source) -> void {
target = OR(target, read(source));
}
auto LR35902::instructionRET_Condition(bool take) -> void {
idle();
if(!take) return;
PC = pop();
idle();
}
auto LR35902::instructionRL_Direct(uint8& data) -> void {
bool carry = data.bit(7);
data = data << 1 | CF;
CF = carry;
HF = NF = ZF = 0;
}
auto LR35902::instructionRLC_Direct(uint8& data) -> void {
data = data << 1 | data >> 7;
CF = data.bit(0);
HF = NF = ZF = 0;
}
auto LR35902::instructionRR_Direct(uint8& data) -> void {
bool carry = data.bit(0);
data = data >> 1 | CF << 7;
CF = carry;
HF = NF = ZF = 0;
}
auto LR35902::instructionRRC_Direct(uint8& data) -> void {
data = data >> 1 | data << 7;
CF = data.bit(7);
HF = NF = ZF = 0;
}
auto LR35902::instructionSBC_Direct_Data(uint8& target) -> void {
target = SBC(target, operand());
}
auto LR35902::instructionSBC_Direct_Direct(uint8& target, uint8& source) -> void {
target = SBC(target, source);
}
auto LR35902::instructionSBC_Direct_Indirect(uint8& target, uint16& source) -> void {
target = SBC(target, read(source));
}
auto LR35902::instructionSCF() -> void {
CF = 1;
HF = NF = 0;
}
auto LR35902::instructionSTOP() -> void {
if(stop()) return;
r.stop = 1;
while(r.stop) idle();
}
auto LR35902::instructionSUB_Direct_Data(uint8& target) -> void {
target = SUB(target, operand());
}
auto LR35902::instructionSUB_Direct_Direct(uint8& target, uint8& source) -> void {
target = SUB(target, source);
}
auto LR35902::instructionSUB_Direct_Indirect(uint8& target, uint16& source) -> void {
target = SUB(target, read(source));
}
auto LR35902::instructionXOR_Direct_Data(uint8& target) -> void {
target = XOR(target, operand());
}
auto LR35902::instructionXOR_Direct_Direct(uint8& target, uint8& source) -> void {
target = XOR(target, source);
}
auto LR35902::instructionXOR_Direct_Indirect(uint8& target, uint16& source) -> void {
target = XOR(target, read(source));
}

11
higan/processor/lr35902/lr35902.cpp
View File

@ -3,16 +3,15 @@
namespace Processor {
#include "instructions.cpp"
#include "registers.cpp"
#include "memory.cpp"
#include "algorithms.cpp"
#include "instruction.cpp"
#include "instructions.cpp"
#include "serialization.cpp"
#include "disassembler.cpp"
auto LR35902::power() -> void {
r.halt = false;
r.stop = false;
r.ei = false;
r.ime = false;
r = {};
}
}

252
higan/processor/lr35902/lr35902.hpp
View File

@ -1,15 +1,14 @@
//Sharp LR35902 (Game Boy Z80-derivative)
//Sharp LR35902
#pragma once
namespace Processor {
struct LR35902 {
virtual auto io() -> void = 0;
virtual auto read(uint16 addr) -> uint8 = 0;
virtual auto write(uint16 addr, uint8 data) -> void = 0;
virtual auto idle() -> void = 0;
virtual auto read(uint16 address) -> uint8 = 0;
virtual auto write(uint16 address, uint8 data) -> void = 0;
virtual auto stop() -> bool = 0;
virtual auto debuggerRead(uint16 addr) -> uint8 { return 0; }
//lr35902.cpp
auto power() -> void;
@ -22,149 +21,108 @@ struct LR35902 {
//serialization.cpp
auto serialize(serializer&) -> void;
#include "registers.hpp"
private:
auto op_xx();
auto op_cb();
//8-bit load commands
auto op_ld_r_r(uint x, uint y);
auto op_ld_r_n(uint x);
auto op_ld_r_hl(uint x);
auto op_ld_hl_r(uint x);
auto op_ld_hl_n();
auto op_ld_a_rr(uint x);
auto op_ld_a_nn();
auto op_ld_rr_a(uint x);
auto op_ld_nn_a();
auto op_ld_a_ffn();
auto op_ld_ffn_a();
auto op_ld_a_ffc();
auto op_ld_ffc_a();
auto op_ldi_hl_a();
auto op_ldi_a_hl();
auto op_ldd_hl_a();
auto op_ldd_a_hl();
//16-bit load commands
auto op_ld_rr_nn(uint x);
auto op_ld_nn_sp();
auto op_ld_sp_hl();
auto op_push_rr(uint x);
auto op_pop_rr(uint x);
//8-bit arithmetic commands
auto opi_add_a(uint8 x);
auto op_add_a_r(uint x);
auto op_add_a_n();
auto op_add_a_hl();
auto opi_adc_a(uint8 x);
auto op_adc_a_r(uint x);
auto op_adc_a_n();
auto op_adc_a_hl();
auto opi_sub_a(uint8 x);
auto op_sub_a_r(uint x);
auto op_sub_a_n();
auto op_sub_a_hl();
auto opi_sbc_a(uint8 x);
auto op_sbc_a_r(uint x);
auto op_sbc_a_n();
auto op_sbc_a_hl();
auto opi_and_a(uint8 x);
auto op_and_a_r(uint x);
auto op_and_a_n();
auto op_and_a_hl();
auto opi_xor_a(uint8 x);
auto op_xor_a_r(uint x);
auto op_xor_a_n();
auto op_xor_a_hl();
auto opi_or_a(uint8 x);
auto op_or_a_r(uint x);
auto op_or_a_n();
auto op_or_a_hl();
auto opi_cp_a(uint8 x);
auto op_cp_a_r(uint x);
auto op_cp_a_n();
auto op_cp_a_hl();
auto op_inc_r(uint x);
auto op_inc_hl();
auto op_dec_r(uint x);
auto op_dec_hl();
auto op_daa();
auto op_cpl();
//16-bit arithmetic commands
auto op_add_hl_rr(uint x);
auto op_inc_rr(uint x);
auto op_dec_rr(uint x);
auto op_add_sp_n();
auto op_ld_hl_sp_n();
//rotate/shift commands
auto op_rlca();
auto op_rla();
auto op_rrca();
auto op_rra();
auto op_rlc_r(uint x);
auto op_rlc_hl();
auto op_rl_r(uint x);
auto op_rl_hl();
auto op_rrc_r(uint x);
auto op_rrc_hl();
auto op_rr_r(uint x);
auto op_rr_hl();
auto op_sla_r(uint x);
auto op_sla_hl();
auto op_swap_r(uint x);
auto op_swap_hl();
auto op_sra_r(uint x);
auto op_sra_hl();
auto op_srl_r(uint x);
auto op_srl_hl();
//single-bit commands
auto op_bit_n_r(uint b, uint x);
auto op_bit_n_hl(uint b);
auto op_set_n_r(uint b, uint x);
auto op_set_n_hl(uint b);
auto op_res_n_r(uint b, uint x);
auto op_res_n_hl(uint b);
//control commands
auto op_ccf();
auto op_scf();
auto op_nop();
auto op_halt();
auto op_stop();
auto op_di();
auto op_ei();
//jump commands
auto op_jp_nn();
auto op_jp_hl();
auto op_jp_f_nn(uint x, bool y);
auto op_jr_n();
auto op_jr_f_n(uint x, bool y);
auto op_call_nn();
auto op_call_f_nn(uint x, bool y);
auto op_ret();
auto op_ret_f(uint x, bool y);
auto op_reti();
auto op_rst_n(uint n);
//disassembler.cpp
auto disassemble(uint16 pc) -> string;
auto disassembleOpcode(uint16 pc) -> string;
auto disassembleOpcodeCB(uint16 pc) -> string;
virtual auto readDebugger(uint16 address) -> uint8 { return 0; }
auto disassemble() -> string { return ""; }
//memory.cpp
auto operand() -> uint8;
auto operands() -> uint16;
auto load(uint16 address) -> uint16;
auto store(uint16 address, uint16 data) -> void;
auto pop() -> uint16;
auto push(uint16 data) -> void;
//algorithms.cpp
auto ADC(uint8, uint8) -> uint8;
auto ADD(uint8, uint8) -> uint8;
auto AND(uint8, uint8) -> uint8;
auto CP(uint8, uint8) -> void;
auto OR(uint8, uint8) -> uint8;
auto SBC(uint8, uint8) -> uint8;
auto SUB(uint8, uint8) -> uint8;
auto XOR(uint8, uint8) -> uint8;
//instructions.cpp
auto instructionADC_Direct_Data(uint8&) -> void;
auto instructionADC_Direct_Direct(uint8&, uint8&) -> void;
auto instructionADC_Direct_Indirect(uint8&, uint16&) -> void;
auto instructionADD_Direct_Data(uint8&) -> void;
auto instructionADD_Direct_Direct(uint8&, uint8&) -> void;
auto instructionADD_Direct_Direct(uint16&, uint16&) -> void;
auto instructionADD_Direct_Indirect(uint8&, uint16&) -> void;
auto instructionAND_Direct_Data(uint8&) -> void;
auto instructionAND_Direct_Direct(uint8&, uint8&) -> void;
auto instructionAND_Direct_Indirect(uint8&, uint16&) -> void;
auto instructionCCF() -> void;
auto instructionCP_Direct_Data(uint8&) -> void;
auto instructionCP_Direct_Direct(uint8&, uint8&) -> void;
auto instructionCP_Direct_Indirect(uint8&, uint16&) -> void;
auto instructionCPL() -> void;
auto instructionDAA() -> void;
auto instructionDEC_Direct(uint8&) -> void;
auto instructionDEC_Direct(uint16&) -> void;
auto instructionDEC_Indirect(uint16&) -> void;
auto instructionDI() -> void;
auto instructionEI() -> void;
auto instructionHALT() -> void;
auto instructionINC_Direct(uint8&) -> void;
auto instructionINC_Direct(uint16&) -> void;
auto instructionINC_Indirect(uint16&) -> void;
auto instructionJR_Condition_Relative(bool) -> void;
auto instructionLD_Address_Direct(uint16&) -> void;
auto instructionLD_Direct_Data(uint8&) -> void;
auto instructionLD_Direct_Data(uint16&) -> void;
auto instructionLD_Direct_Direct(uint8&, uint8&) -> void;
auto instructionLD_Direct_Indirect(uint8&, uint8&) -> void;
auto instructionLD_Direct_Indirect(uint8&, uint16&) -> void;
auto instructionLD_Direct_IndirectDecrement(uint8&, uint16&) -> void;
auto instructionLD_Direct_IndirectIncrement(uint8&, uint16&) -> void;
auto instructionLD_Indirect_Data(uint16&) -> void;
auto instructionLD_Indirect_Direct(uint8&, uint8&) -> void;
auto instructionLD_Indirect_Direct(uint16&, uint8&) -> void;
auto instructionLD_IndirectDecrement_Direct(uint16&, uint8&) -> void;
auto instructionLD_IndirectIncrement_Direct(uint16&, uint8&) -> void;
auto instructionNOP() -> void;
auto instructionOR_Direct_Data(uint8&) -> void;
auto instructionOR_Direct_Direct(uint8&, uint8&) -> void;
auto instructionOR_Direct_Indirect(uint8&, uint16&) -> void;
auto instructionRET_Condition(bool) -> void;
auto instructionRL_Direct(uint8&) -> void;
auto instructionRLC_Direct(uint8&) -> void;
auto instructionRR_Direct(uint8&) -> void;
auto instructionRRC_Direct(uint8&) -> void;
auto instructionSBC_Direct_Data(uint8&) -> void;
auto instructionSBC_Direct_Direct(uint8&, uint8&) -> void;
auto instructionSBC_Direct_Indirect(uint8&, uint16&) -> void;
auto instructionSCF() -> void;
auto instructionSUB_Direct_Data(uint8&) -> void;
auto instructionSUB_Direct_Direct(uint8&, uint8&) -> void;
auto instructionSUB_Direct_Indirect(uint8&, uint16&) -> void;
auto instructionSTOP() -> void;
auto instructionXOR_Direct_Data(uint8&) -> void;
auto instructionXOR_Direct_Direct(uint8&, uint8&) -> void;
auto instructionXOR_Direct_Indirect(uint8&, uint16&) -> void;
struct Registers {
union Pair {
Pair() : word(0) {}
uint16 word;
struct Byte { uint8 order_msb2(hi, lo); } byte;
};
Pair af;
Pair bc;
Pair de;
Pair hl;
Pair sp;
Pair pc;
uint1 ei;
uint1 halt;
uint1 stop;
uint1 ime;
} r;
};
}

28
higan/processor/lr35902/memory.cpp Normal file
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@ -0,0 +1,28 @@
auto LR35902::operand() -> uint8 {
return read(PC++);
}
auto LR35902::operands() -> uint16 {
uint16 data = read(PC++) << 0;
return data | read(PC++) << 8;
}
auto LR35902::load(uint16 address) -> uint16 {
uint16 data = read(address++) << 0;
return data | read(address++) << 8;
}
auto LR35902::store(uint16 address, uint16 data) -> void {
write(address++, data >> 0);
write(address++, data >> 8);
}
auto LR35902::pop() -> uint16 {
uint16 data = read(SP++) << 0;
return data | read(SP++) << 8;
}
auto LR35902::push(uint16 data) -> void {
write(--SP, data >> 8);
write(--SP, data >> 0);
}

20
higan/processor/lr35902/registers.cpp Normal file
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@ -0,0 +1,20 @@
#define AF r.af.word
#define BC r.bc.word
#define DE r.de.word
#define HL r.hl.word
#define SP r.sp.word
#define PC r.pc.word
#define A r.af.byte.hi
#define F r.af.byte.lo
#define B r.bc.byte.hi
#define C r.bc.byte.lo
#define D r.de.byte.hi
#define E r.de.byte.lo
#define H r.hl.byte.hi
#define L r.hl.byte.lo
#define CF r.af.byte.lo.bit(4)
#define HF r.af.byte.lo.bit(5)
#define NF r.af.byte.lo.bit(6)
#define ZF r.af.byte.lo.bit(7)

107
higan/processor/lr35902/registers.hpp
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@ -1,107 +0,0 @@
enum {
A, F, AF,
B, C, BC,
D, E, DE,
H, L, HL,
SP, PC,
};
enum {
ZF, NF, HF, CF,
};
//register base class
//the idea here is to have all registers derive from a single base class.
//this allows construction of opcodes that can take any register as input or output,
//despite the fact that behind-the-scenes, special handling is done for eg: F, AF, HL, etc.
//registers can also be chained together: eg af = 0x0000 writes both a and f.
struct Register {
virtual operator unsigned() const = 0;
virtual unsigned operator=(unsigned x) = 0;
Register& operator=(const Register& x) { operator=((unsigned)x); return *this; }
unsigned operator++(int) { unsigned r = *this; operator=(*this + 1); return r; }
unsigned operator--(int) { unsigned r = *this; operator=(*this - 1); return r; }
unsigned operator++() { return operator=(*this + 1); }
unsigned operator--() { return operator=(*this - 1); }
unsigned operator |=(unsigned x) { return operator=(*this | x); }
unsigned operator ^=(unsigned x) { return operator=(*this ^ x); }
unsigned operator &=(unsigned x) { return operator=(*this & x); }
unsigned operator<<=(unsigned x) { return operator=(*this << x); }
unsigned operator>>=(unsigned x) { return operator=(*this >> x); }
unsigned operator +=(unsigned x) { return operator=(*this + x); }
unsigned operator -=(unsigned x) { return operator=(*this - x); }
unsigned operator *=(unsigned x) { return operator=(*this * x); }
unsigned operator /=(unsigned x) { return operator=(*this / x); }
unsigned operator %=(unsigned x) { return operator=(*this % x); }
};
struct Register8 : Register {
uint8 data;
operator unsigned() const { return data; }
unsigned operator=(unsigned x) { return data = x; }
};
struct RegisterF : Register {
bool z, n, h, c;
operator unsigned() const { return (z << 7) | (n << 6) | (h << 5) | (c << 4); }
unsigned operator=(unsigned x) { z = x & 0x80; n = x & 0x40; h = x & 0x20; c = x & 0x10; return *this; }
bool& operator[](unsigned r) {
static bool* table[] = {&z, &n, &h, &c};
return *table[r];
}
};
struct Register16 : Register {
uint16 data;
operator unsigned() const { return data; }
unsigned operator=(unsigned x) { return data = x; }
};
struct RegisterAF : Register {
Register8& hi;
RegisterF& lo;
operator unsigned() const { return (hi << 8) | (lo << 0); }
unsigned operator=(unsigned x) { hi = x >> 8; lo = x >> 0; return *this; }
RegisterAF(Register8& hi, RegisterF& lo) : hi(hi), lo(lo) {}
};
struct RegisterW : Register {
Register8& hi;
Register8& lo;
operator unsigned() const { return (hi << 8) | (lo << 0); }
unsigned operator=(unsigned x) { hi = x >> 8; lo = x >> 0; return *this; }
RegisterW(Register8& hi, Register8& lo) : hi(hi), lo(lo) {}
};
struct Registers {
Register8 a;
RegisterF f;
RegisterAF af;
Register8 b;
Register8 c;
RegisterW bc;
Register8 d;
Register8 e;
RegisterW de;
Register8 h;
Register8 l;
RegisterW hl;
Register16 sp;
Register16 pc;
bool halt;
bool stop;
bool ei;
bool ime;
Register& operator[](unsigned r) {
static Register* const table[] = {&a, &f, &af, &b, &c, &bc, &d, &e, &de, &h, &l, &hl, &sp, &pc};
return *table[r];
}
Registers() : af(a, f), bc(b, c), de(d, e), hl(h, l) {}
} r;

22
higan/processor/lr35902/serialization.cpp
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@ -1,20 +1,12 @@
auto LR35902::serialize(serializer& s) -> void {
s.integer(r.a.data);
s.integer(r.f.z);
s.integer(r.f.n);
s.integer(r.f.h);
s.integer(r.f.c);
s.integer(r.b.data);
s.integer(r.c.data);
s.integer(r.d.data);
s.integer(r.e.data);
s.integer(r.h.data);
s.integer(r.l.data);
s.integer(r.sp.data);
s.integer(r.pc.data);
s.integer(r.af.word);
s.integer(r.bc.word);
s.integer(r.de.word);
s.integer(r.hl.word);
s.integer(r.sp.word);
s.integer(r.pc.word);
s.integer(r.ei);
s.integer(r.halt);
s.integer(r.stop);
s.integer(r.ei);
s.integer(r.ime);
}

4
ruby/audio/alsa.cpp
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@ -146,11 +146,11 @@ private:
auto queryDevices() -> string_vector {
string_vector devices;
const char** list;
char** list;
if(snd_device_name_hint(-1, "pcm", (void***)&list) == 0) {
uint index = 0;
while(list[index]) {
const char* deviceName = snd_device_name_get_hint(list[index], "NAME");
char* deviceName = snd_device_name_get_hint(list[index], "NAME");
if(deviceName) devices.append(deviceName);
free(deviceName);
index++;

3
ruby/video/opengl/main.hpp
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@ -183,14 +183,11 @@ auto OpenGL::output() -> void {
auto OpenGL::initialize() -> bool {
if(!OpenGLBind()) return false;
glDisable(GL_ALPHA_TEST);
glDisable(GL_BLEND);
glDisable(GL_DEPTH_TEST);
glDisable(GL_POLYGON_SMOOTH);
glDisable(GL_STENCIL_TEST);
glEnable(GL_DITHER);
glEnable(GL_TEXTURE_2D);
program = glCreateProgram();
vertex = glrCreateShader(program, GL_VERTEX_SHADER, OpenGLOutputVertexShader);

6
ruby/video/opengl/surface.hpp
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@ -89,19 +89,19 @@ auto OpenGLSurface::render(uint sourceWidth, uint sourceHeight, uint targetWidth
glBindBuffer(GL_ARRAY_BUFFER, vbo[0]);
glBufferData(GL_ARRAY_BUFFER, 16 * sizeof(GLfloat), vertices, GL_STATIC_DRAW);
GLuint locationVertex = glGetAttribLocation(program, "vertex");
GLint locationVertex = glGetAttribLocation(program, "vertex");
glEnableVertexAttribArray(locationVertex);
glVertexAttribPointer(locationVertex, 4, GL_FLOAT, GL_FALSE, 0, 0);
glBindBuffer(GL_ARRAY_BUFFER, vbo[1]);
glBufferData(GL_ARRAY_BUFFER, 16 * sizeof(GLfloat), positions, GL_STATIC_DRAW);
GLuint locationPosition = glGetAttribLocation(program, "position");
GLint locationPosition = glGetAttribLocation(program, "position");
glEnableVertexAttribArray(locationPosition);
glVertexAttribPointer(locationPosition, 4, GL_FLOAT, GL_FALSE, 0, 0);
glBindBuffer(GL_ARRAY_BUFFER, vbo[2]);
glBufferData(GL_ARRAY_BUFFER, 8 * sizeof(GLfloat), texCoords, GL_STATIC_DRAW);
GLuint locationTexCoord = glGetAttribLocation(program, "texCoord");
GLint locationTexCoord = glGetAttribLocation(program, "texCoord");
glEnableVertexAttribArray(locationTexCoord);
glVertexAttribPointer(locationTexCoord, 2, GL_FLOAT, GL_FALSE, 0, 0);