bsnes/higan/processor/spc700/spc700.hpp

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#pragma once
namespace Processor {
struct SPC700 {
Update to v099r14 release. byuu says: Changelog: - (u)int(max,ptr) abbreviations removed; use _t suffix now [didn't feel like they were contributing enough to be worth it] - cleaned up nall::integer,natural,real functionality - toInteger, toNatural, toReal for parsing strings to numbers - fromInteger, fromNatural, fromReal for creating strings from numbers - (string,Markup::Node,SQL-based-classes)::(integer,natural,real) left unchanged - template<typename T> numeral(T value, long padding, char padchar) -> string for print() formatting - deduces integer,natural,real based on T ... cast the value if you want to override - there still exists binary,octal,hex,pointer for explicit print() formatting - lstring -> string_vector [but using lstring = string_vector; is declared] - would be nice to remove the using lstring eventually ... but that'd probably require 10,000 lines of changes >_> - format -> string_format [no using here; format was too ambiguous] - using integer = Integer<sizeof(int)*8>; and using natural = Natural<sizeof(uint)*8>; declared - for consistency with boolean. These three are meant for creating zero-initialized values implicitly (various uses) - R65816::io() -> idle() and SPC700::io() -> idle() [more clear; frees up struct IO {} io; naming] - SFC CPU, PPU, SMP use struct IO {} io; over struct (Status,Registers) {} (status,registers); now - still some CPU::Status status values ... they didn't really fit into IO functionality ... will have to think about this more - SFC CPU, PPU, SMP now use step() exclusively instead of addClocks() calling into step() - SFC CPU joypad1_bits, joypad2_bits were unused; killed them - SFC PPU CGRAM moved into PPU::Screen; since nothing else uses it - SFC PPU OAM moved into PPU::Object; since nothing else uses it - the raw uint8[544] array is gone. OAM::read() constructs values from the OAM::Object[512] table now - this avoids having to determine how we want to sub-divide the two OAM memory sections - this also eliminates the OAM::synchronize() functionality - probably more I'm forgetting The FPS fluctuations are driving me insane. This WIP went from 128fps to 137fps. Settled on 133.5fps for the final build. But nothing I changed should have affected performance at all. This level of fluctuation makes it damn near impossible to know whether I'm speeding things up or slowing things down with changes.
2016-07-01 11:50:32 +00:00
virtual auto idle() -> void = 0;
virtual auto read(uint16 addr) -> uint8 = 0;
virtual auto write(uint16 addr, uint8 data) -> void = 0;
Update to v102r27 release. byuu says: Changelog: - processor/gsu: minor code cleanup - processor/hg51b: renamed reg(Read,Write) to register(Read,Write) - processor/lr35902: minor code cleanup - processor/spc700: completed code cleanup (sans disassembler) - no longer uses internal global state inside instructions - processor/spc700: will no longer hang the emulator if stuck in a WAI (SLEEP) or STP (STOP) instruction - processor/spc700: fixed bug in handling of OR1 and AND1 instructions - processor/z80: minor code cleanup - sfc/dsp: revert to initializing registers to 0x00; save for ENDX=random(), FLG=0xe0 [Jonas Quinn] Major testing of the SNES game library would be appreciated, now that its CPU cores have all been revised. We know the DSP registers read back as randomized data ... mostly, but there are apparently internal latches, which we can't emulate with the current DSP design. So until we know which registers have separate internal state that actually *is* initialized, I'm going to play it safe and not break more games. Thanks again to Jonas Quinn for the continued research into this issue. EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance that the game will work. That seems pretty unlikely that the odds of it working are that low, given hardware testing by others in the past :/ I thought if worked if `PITCH != 0` before, which would have been way more likely. The two remaining CPU cores that need major cleanup efforts are the LR35902 and ARM cores. Both are very large, complicated, annoying cores that will probably be better off as full rewrites from scratch. I don't think I want to delay v103 in trying to accomplish that, however. So I think it'll be best to focus on allowing the Mega Drive core to not lock when processors are frozen waiting on a response from other processors during a save state operation. Then we should be good for a new release.
2017-06-19 02:07:54 +00:00
virtual auto synchronizing() const -> bool = 0;
virtual auto readDisassembler(uint16 addr) -> uint8 { return 0; }
2011-11-17 12:05:35 +00:00
//spc700.cpp
auto power() -> void;
//instruction.cpp
auto instruction() -> void;
//memory.cpp
auto fetch() -> uint8;
auto pull() -> uint8;
auto push(uint8 data) -> void;
auto load(uint8 addr) -> uint8;
auto store(uint8 addr, uint8 data) -> void;
//algorithms.cpp
auto algorithmADC(uint8, uint8) -> uint8;
auto algorithmAND(uint8, uint8) -> uint8;
auto algorithmASL(uint8) -> uint8;
auto algorithmCMP(uint8, uint8) -> uint8;
auto algorithmDEC(uint8) -> uint8;
auto algorithmEOR(uint8, uint8) -> uint8;
auto algorithmINC(uint8) -> uint8;
auto algorithmLD (uint8, uint8) -> uint8;
auto algorithmLSR(uint8) -> uint8;
auto algorithmOR (uint8, uint8) -> uint8;
auto algorithmROL(uint8) -> uint8;
auto algorithmROR(uint8) -> uint8;
auto algorithmSBC(uint8, uint8) -> uint8;
auto algorithmST (uint8, uint8) -> uint8;
auto algorithmADW(uint16, uint16) -> uint16;
auto algorithmCPW(uint16, uint16) -> uint16;
auto algorithmLDW(uint16, uint16) -> uint16;
auto algorithmSBW(uint16, uint16) -> uint16;
//instructions.cpp
using fps = auto (SPC700::*)(uint8) -> uint8;
using fpb = auto (SPC700::*)(uint8, uint8) -> uint8;
using fpw = auto (SPC700::*)(uint16, uint16) -> uint16;
auto instructionImpliedModify(fps, uint8&) -> void;
auto instructionAbsoluteModify(fps) -> void;
auto instructionDirectPageModify(fps) -> void;
auto instructionDirectPageModifyWord(int) -> void;
auto instructionDirectPageXModify(fps) -> void;
auto instructionBranch(bool) -> void;
auto instructionPull(uint8&) -> void;
auto instructionPush(uint8) -> void;
auto instructionAbsoluteRead(fpb, uint8&) -> void;
auto instructionAbsoluteIndexedRead(fpb, uint8&) -> void;
auto instructionImmediateRead(fpb, uint8&) -> void;
auto instructionDirectPageRead(fpb, uint8&) -> void;
auto instructionDirectPageIndexedRead(fpb, uint8&, uint8&) -> void;
auto instructionDirectPageReadWord(fpw) -> void;
auto instructionIndirectPageXRead(fpb) -> void;
auto instructionIndirectPageYRead(fpb) -> void;
auto instructionIndirectXRead(fpb) -> void;
Update to v102r27 release. byuu says: Changelog: - processor/gsu: minor code cleanup - processor/hg51b: renamed reg(Read,Write) to register(Read,Write) - processor/lr35902: minor code cleanup - processor/spc700: completed code cleanup (sans disassembler) - no longer uses internal global state inside instructions - processor/spc700: will no longer hang the emulator if stuck in a WAI (SLEEP) or STP (STOP) instruction - processor/spc700: fixed bug in handling of OR1 and AND1 instructions - processor/z80: minor code cleanup - sfc/dsp: revert to initializing registers to 0x00; save for ENDX=random(), FLG=0xe0 [Jonas Quinn] Major testing of the SNES game library would be appreciated, now that its CPU cores have all been revised. We know the DSP registers read back as randomized data ... mostly, but there are apparently internal latches, which we can't emulate with the current DSP design. So until we know which registers have separate internal state that actually *is* initialized, I'm going to play it safe and not break more games. Thanks again to Jonas Quinn for the continued research into this issue. EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance that the game will work. That seems pretty unlikely that the odds of it working are that low, given hardware testing by others in the past :/ I thought if worked if `PITCH != 0` before, which would have been way more likely. The two remaining CPU cores that need major cleanup efforts are the LR35902 and ARM cores. Both are very large, complicated, annoying cores that will probably be better off as full rewrites from scratch. I don't think I want to delay v103 in trying to accomplish that, however. So I think it'll be best to focus on allowing the Mega Drive core to not lock when processors are frozen waiting on a response from other processors during a save state operation. Then we should be good for a new release.
2017-06-19 02:07:54 +00:00
auto instructionAbsoluteModifyBit(uint3) -> void;
auto instructionFlagClear(bool&) -> void;
auto instructionFlagSet(bool&) -> void;
auto instructionTransfer(uint8&, uint8&) -> void;
auto instructionAbsoluteWrite(uint8&) -> void;
auto instructionAbsoluteIndexedWrite(uint8&) -> void;
auto instructionDirectPageWrite(uint8&) -> void;
auto instructionDirectPageIndexedWrite(uint8&, uint8&) -> void;
auto instructionDirectPageWriteImmediate(fpb) -> void;
auto instructionDirectPageWriteDirectPage(fpb) -> void;
auto instructionIndirectXWriteIndirectY(fpb) -> void;
auto instructionBBC(uint3) -> void;
auto instructionBBS(uint3) -> void;
auto instructionBNEDirectPage() -> void;
auto instructionBNEDirectPageDecrement() -> void;
auto instructionBNEDirectPageX() -> void;
auto instructionBNEYDecrement() -> void;
auto instructionBRK() -> void;
auto instructionCLR(uint3) -> void;
auto instructionCLV() -> void;
auto instructionCMC() -> void;
auto instructionDAA() -> void;
auto instructionDAS() -> void;
auto instructionDIV() -> void;
auto instructionJMPAbsolute() -> void;
auto instructionJMPIndirectAbsoluteX() -> void;
auto instructionJSPDirectPage() -> void;
auto instructionJSRAbsolute() -> void;
auto instructionJST(uint4) -> void;
auto instructionLDAIndirectXIncrement() -> void;
auto instructionMUL() -> void;
auto instructionNOP() -> void;
auto instructionPLP() -> void;
auto instructionRTI() -> void;
auto instructionRTS() -> void;
auto instructionSET(uint3) -> void;
auto instructionSTAIndirectPageX() -> void;
auto instructionSTAIndirectPageY() -> void;
auto instructionSTAIndirectX() -> void;
auto instructionSTAIndirectXIncrement() -> void;
auto instructionSTP() -> void;
auto instructionSTWDirectPage() -> void;
auto instructionTRBAbsolute() -> void;
auto instructionTSBAbsolute() -> void;
auto instructionWAI() -> void;
auto instructionXCN() -> void;
//serialization.cpp
auto serialize(serializer&) -> void;
//disassembler.cpp
auto disassemble(uint16 addr, bool p) -> string;
struct Flags {
bool c; //carry
bool z; //zero
bool i; //interrupt disable
bool h; //half-carry
bool b; //break
bool p; //page
bool v; //overflow
bool n; //negative
inline operator uint() const {
return c << 0 | z << 1 | i << 2 | h << 3 | b << 4 | p << 5 | v << 6 | n << 7;
}
inline auto& operator=(uint8 data) {
c = data.bit(0);
z = data.bit(1);
i = data.bit(2);
h = data.bit(3);
b = data.bit(4);
p = data.bit(5);
v = data.bit(6);
n = data.bit(7);
return *this;
}
};
struct Registers {
union Pair {
Pair() : w(0) {}
uint16 w;
struct Byte { uint8 order_lsb2(l, h); } byte;
} pc, ya;
uint8 x, s;
Flags p;
Update to v102r27 release. byuu says: Changelog: - processor/gsu: minor code cleanup - processor/hg51b: renamed reg(Read,Write) to register(Read,Write) - processor/lr35902: minor code cleanup - processor/spc700: completed code cleanup (sans disassembler) - no longer uses internal global state inside instructions - processor/spc700: will no longer hang the emulator if stuck in a WAI (SLEEP) or STP (STOP) instruction - processor/spc700: fixed bug in handling of OR1 and AND1 instructions - processor/z80: minor code cleanup - sfc/dsp: revert to initializing registers to 0x00; save for ENDX=random(), FLG=0xe0 [Jonas Quinn] Major testing of the SNES game library would be appreciated, now that its CPU cores have all been revised. We know the DSP registers read back as randomized data ... mostly, but there are apparently internal latches, which we can't emulate with the current DSP design. So until we know which registers have separate internal state that actually *is* initialized, I'm going to play it safe and not break more games. Thanks again to Jonas Quinn for the continued research into this issue. EDIT: that said ... `MD works if((ENDX&0x30) > 0)` is only a 3:4 chance that the game will work. That seems pretty unlikely that the odds of it working are that low, given hardware testing by others in the past :/ I thought if worked if `PITCH != 0` before, which would have been way more likely. The two remaining CPU cores that need major cleanup efforts are the LR35902 and ARM cores. Both are very large, complicated, annoying cores that will probably be better off as full rewrites from scratch. I don't think I want to delay v103 in trying to accomplish that, however. So I think it'll be best to focus on allowing the Mega Drive core to not lock when processors are frozen waiting on a response from other processors during a save state operation. Then we should be good for a new release.
2017-06-19 02:07:54 +00:00
bool wai = false;
bool stp = false;
} r;
};
}