2015-07-01 10:58:42 +00:00
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auto CPU::prefetch_sync(uint32 addr) -> void {
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if(addr == prefetch.addr) return;
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2015-06-27 02:38:08 +00:00
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2015-07-01 10:58:42 +00:00
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prefetch.addr = addr;
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prefetch.load = addr;
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prefetch.wait = bus_wait(Half | Nonsequential, prefetch.load);
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2015-06-28 08:44:56 +00:00
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}
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2015-11-16 08:38:05 +00:00
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auto CPU::prefetch_step(uint clocks) -> void {
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2015-07-01 10:58:42 +00:00
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step(clocks);
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if(!regs.wait.control.prefetch || active.dma) return;
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2015-06-28 08:44:56 +00:00
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2015-07-02 10:22:24 +00:00
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while(!prefetch.full() && clocks--) {
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if(--prefetch.wait) continue;
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Update to v095r03 release and icarus 20151107.
byuu says:
Note: you will need the new icarus (and please use the "no manifest"
system) to run GBA games with this WIP.
Changelog:
- fixed caching of r(d) to pass armwrestler tests [Jonas Quinn]
- DMA to/from GBA BIOS should fail [Cydrak]
- fixed sign-extend and rotate on ldrs instructions [Cydrak]
- fixed 8-bit SRAM reading/writing [byuu]
- refactored GBA/cartridge
- cartridge/rom,ram.type is now cartridge/mrom,sram,eeprom,flash
- things won't crash horribly if you specify a RAM size larger than
the largest legal size in the manifest
- specialized MROM / SRAM classes replace all the shared read/write
functions that didn't work right anyway
- there's a new ruby/video.glx2 driver, which is not enabled by default
- use this if you are running Linux/BSD, but don't have OpenGL 3.2 yet
- I'm not going to support OpenGL2 on Windows/OS X, because these OSes
don't ship ancient video card drivers
- probably more. What am I, clairvoyant? :P
For endrift's tests, this gets us to 1348/1552 memory and 1016/1260
timing. Overall, this puts us back in second place. Only no$ is ahead
on memory, but bgba is even more ahead on timing.
2015-11-08 09:09:18 +00:00
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prefetch.slot[prefetch.load >> 1 & 7] = cartridge.read(Half, prefetch.load);
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2015-07-01 10:58:42 +00:00
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prefetch.load += 2;
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2015-07-02 10:22:24 +00:00
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prefetch.wait = bus_wait(Half | Sequential, prefetch.load);
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2015-06-27 02:38:08 +00:00
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}
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2015-06-28 08:44:56 +00:00
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}
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auto CPU::prefetch_wait() -> void {
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2015-07-02 10:22:24 +00:00
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if(!regs.wait.control.prefetch || active.dma || prefetch.full()) return;
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2015-07-01 10:58:42 +00:00
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2015-06-28 08:44:56 +00:00
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prefetch_step(prefetch.wait);
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2015-07-01 10:58:42 +00:00
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prefetch.wait = bus_wait(Half | Nonsequential, prefetch.load);
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2015-06-27 02:38:08 +00:00
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}
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2015-07-01 10:58:42 +00:00
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auto CPU::prefetch_read() -> uint16 {
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if(prefetch.empty()) prefetch_step(prefetch.wait);
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else prefetch_step(1);
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if(prefetch.full()) prefetch.wait = bus_wait(Half | Sequential, prefetch.load);
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2015-06-28 08:44:56 +00:00
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2015-07-01 10:58:42 +00:00
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uint16 half = prefetch.slot[prefetch.addr >> 1 & 7];
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prefetch.addr += 2;
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return half;
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2015-06-27 02:38:08 +00:00
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}
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