2010-08-09 13:28:56 +00:00
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#ifdef SMP_CPP
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alwaysinline uint8 SMP::ram_read(uint16 addr) {
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2011-05-02 13:53:16 +00:00
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if(addr >= 0xffc0 && status.iplrom_enable) return iplrom[addr & 0x3f];
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if(status.ram_disable) return 0x5a; //0xff on mini-SNES
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Update to v074r11 release.
byuu says:
Changelog:
- debugger compiles on all three profiles
- libsnes compiles on all three platforms (no API changes to libsnes)
- memory.cpp : namespace memory removed (wram -> cpu, apuram -> smp,
vram, oam, cgram -> ppu)
- sa1.cpp : namespace memory removed (SA-1 specific functions merged
inline to SA1::bus_read,write)
- GameBoy: added serial link support with interrupts and proper 8192hz
timing, but obviously it acts as if no other GB is connected to it
- GameBoy: added STAT OAM interrupt, and better STAT d1,d0 mode values
- UI: since Qt is dead, I've renamed the config files back to bsnes.cfg
and bsnes-geometry.cfg
- SA1: IRAM was not syncing to CPU on SA-1 side
- PPU/Accuracy and PPU/Performance needed Sprite oam renamed to Sprite
sprite; so that I could add uint8 oam[544]
- makes more sense anyway, OAM = object attribute memory, obj or
sprite are better names for Sprite rendering class
- more cleanup
2011-01-24 09:03:17 +00:00
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return apuram[addr];
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2010-08-09 13:28:56 +00:00
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}
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alwaysinline void SMP::ram_write(uint16 addr, uint8 data) {
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//writes to $ffc0-$ffff always go to apuram, even if the iplrom is enabled
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2011-05-02 13:53:16 +00:00
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if(status.ram_writable && !status.ram_disable) apuram[addr] = data;
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2010-08-09 13:28:56 +00:00
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}
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Updated to v067r23 release.
byuu says:
Added missing $4200 IRQ lock, which fixes Chou Aniki on the fast CPU
core, so slower PCs can get their brotherly love on.
Added range-based controller IOBit latching to the fast CPU core, which
enables Super Scope and Justifier support. Uses the priority queue as
well, so there is zero speed-hit. Given the way range-testing works, the
trigger point may vary by 1-2 pixels when firing at the same spot. Not
really a big deal when it avoids a massive speed penalty.
Fixed PAL and interlace-mode HVIRQs at V=0,H<2 on the fast CPU core.
Added the dot-renderer's sprite list update-on-OAM-write functionality
to the scanline-based PPU renderer. Unfortunately it looks like all the
speed gain was already taken from the global dirty flag I was using
before, but this certainly won't hurt speed any, so whatever.
Added #ifdef to stop CoInitialize(0) on non-Windows ports.
Added #ifdefs to stop gradient fade on Windows port. Not going to fuck
over the Linux port aesthetic because of Qt bug #47,326,927. If there's
a way to tell what Qt theme is being used, I can leave it enabled for
XP/Vista themes.
Moved HDMA trigger from 1104 to 1112, and reduced channel overhead from
24 to 16, to better simulate one-cycle DMA->CPU sync.
Code clarity: I've re-added my varint.hpp classes, and am actively using
them in the accuracy cores. So far, I haven't done anything that would
detriment speed, but it is certainly cool. The APU ports exposed by the
CPU and SMP now take uint2 address arguments, the CPU WRAM address
register is a uint17, and the IRQ H/VTIME values are uint10. This
basically allows the source to clearly convey the data sizes, and
eliminates the need to manually mask values when writing to registers or
reading from memory. I'm going to be doing this everywhere, and it will
have a speed impact eventually, because the automation means we can't
skip masks when we know the data is already masked off.
Source: archive contains the launcher code, so that I can look into why
it's crashing on XP tomorrow.
It doesn't look like Circuit USA's flags are going to work too well with
this new CPU core. Still not sure what the hell Robocop vs The
Terminator is doing, I'll read through the mega SNES thread for clues
tomorrow. Speedy Gonzales is definitely broken, as modifying the MDR was
breaking things with my current core. Probably because the new CPU core
doesn't wait for a cycle edge to trigger.
I was thinking that perhaps we could keep some form of cheat codes list
to work as game-specific hacks for the performance core. Keeps the hacks
out of the emulator, but could allow the remaining bugs to be worked
around for people who have no choice but to use the performance core.
2010-08-16 09:42:20 +00:00
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uint8 SMP::port_read(uint2 port) const {
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Update to v074r11 release.
byuu says:
Changelog:
- debugger compiles on all three profiles
- libsnes compiles on all three platforms (no API changes to libsnes)
- memory.cpp : namespace memory removed (wram -> cpu, apuram -> smp,
vram, oam, cgram -> ppu)
- sa1.cpp : namespace memory removed (SA-1 specific functions merged
inline to SA1::bus_read,write)
- GameBoy: added serial link support with interrupts and proper 8192hz
timing, but obviously it acts as if no other GB is connected to it
- GameBoy: added STAT OAM interrupt, and better STAT d1,d0 mode values
- UI: since Qt is dead, I've renamed the config files back to bsnes.cfg
and bsnes-geometry.cfg
- SA1: IRAM was not syncing to CPU on SA-1 side
- PPU/Accuracy and PPU/Performance needed Sprite oam renamed to Sprite
sprite; so that I could add uint8 oam[544]
- makes more sense anyway, OAM = object attribute memory, obj or
sprite are better names for Sprite rendering class
- more cleanup
2011-01-24 09:03:17 +00:00
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return apuram[0xf4 + port];
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2010-08-09 13:28:56 +00:00
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}
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|
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|
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|
Updated to v067r23 release.
byuu says:
Added missing $4200 IRQ lock, which fixes Chou Aniki on the fast CPU
core, so slower PCs can get their brotherly love on.
Added range-based controller IOBit latching to the fast CPU core, which
enables Super Scope and Justifier support. Uses the priority queue as
well, so there is zero speed-hit. Given the way range-testing works, the
trigger point may vary by 1-2 pixels when firing at the same spot. Not
really a big deal when it avoids a massive speed penalty.
Fixed PAL and interlace-mode HVIRQs at V=0,H<2 on the fast CPU core.
Added the dot-renderer's sprite list update-on-OAM-write functionality
to the scanline-based PPU renderer. Unfortunately it looks like all the
speed gain was already taken from the global dirty flag I was using
before, but this certainly won't hurt speed any, so whatever.
Added #ifdef to stop CoInitialize(0) on non-Windows ports.
Added #ifdefs to stop gradient fade on Windows port. Not going to fuck
over the Linux port aesthetic because of Qt bug #47,326,927. If there's
a way to tell what Qt theme is being used, I can leave it enabled for
XP/Vista themes.
Moved HDMA trigger from 1104 to 1112, and reduced channel overhead from
24 to 16, to better simulate one-cycle DMA->CPU sync.
Code clarity: I've re-added my varint.hpp classes, and am actively using
them in the accuracy cores. So far, I haven't done anything that would
detriment speed, but it is certainly cool. The APU ports exposed by the
CPU and SMP now take uint2 address arguments, the CPU WRAM address
register is a uint17, and the IRQ H/VTIME values are uint10. This
basically allows the source to clearly convey the data sizes, and
eliminates the need to manually mask values when writing to registers or
reading from memory. I'm going to be doing this everywhere, and it will
have a speed impact eventually, because the automation means we can't
skip masks when we know the data is already masked off.
Source: archive contains the launcher code, so that I can look into why
it's crashing on XP tomorrow.
It doesn't look like Circuit USA's flags are going to work too well with
this new CPU core. Still not sure what the hell Robocop vs The
Terminator is doing, I'll read through the mega SNES thread for clues
tomorrow. Speedy Gonzales is definitely broken, as modifying the MDR was
breaking things with my current core. Probably because the new CPU core
doesn't wait for a cycle edge to trigger.
I was thinking that perhaps we could keep some form of cheat codes list
to work as game-specific hacks for the performance core. Keeps the hacks
out of the emulator, but could allow the remaining bugs to be worked
around for people who have no choice but to use the performance core.
2010-08-16 09:42:20 +00:00
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void SMP::port_write(uint2 port, uint8 data) {
|
Update to v074r11 release.
byuu says:
Changelog:
- debugger compiles on all three profiles
- libsnes compiles on all three platforms (no API changes to libsnes)
- memory.cpp : namespace memory removed (wram -> cpu, apuram -> smp,
vram, oam, cgram -> ppu)
- sa1.cpp : namespace memory removed (SA-1 specific functions merged
inline to SA1::bus_read,write)
- GameBoy: added serial link support with interrupts and proper 8192hz
timing, but obviously it acts as if no other GB is connected to it
- GameBoy: added STAT OAM interrupt, and better STAT d1,d0 mode values
- UI: since Qt is dead, I've renamed the config files back to bsnes.cfg
and bsnes-geometry.cfg
- SA1: IRAM was not syncing to CPU on SA-1 side
- PPU/Accuracy and PPU/Performance needed Sprite oam renamed to Sprite
sprite; so that I could add uint8 oam[544]
- makes more sense anyway, OAM = object attribute memory, obj or
sprite are better names for Sprite rendering class
- more cleanup
2011-01-24 09:03:17 +00:00
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apuram[0xf4 + port] = data;
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2010-08-09 13:28:56 +00:00
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}
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Update to v085r08 release.
byuu says:
Changelog:
- follow the Laevateinn topic to get most of it
- also added NMI, IRQ step buttons to CPU debugger
- also added trace masking + trace mask reset
- also added memory export
- cartridge loading is entirely folder-based now
FitzRoy, I'll go ahead and make a second compromise with you for v086:
I'll match the following:
/path/to/SNES.sfc/*.sfc
/path/to/NES.fc/*.prg, *.chr (split format)
/path/to/NES.fc/*.fc (merged format)
/path/to/GB.gb/*.gb
/path/to/GBC.gbc/*.gbc
Condition will be that there can only be one of each file. If there's
more than one, it'll abort. That lets me name my ROMs as
"Game.fc/Game.fc", and you can name yours as "Game.fc/cartridge.prg,
cartridge.chr". Or whatever you want.
We'll just go with that, see what fares out as the most popular, and
then restrict it back to that method.
The folder must have the .fc, etc extension though. That will be how we
avoid false-positive folder matches.
[Editor's note - the Laevateinn topic mentions these changes for
v085r08:
Added SMP/PPU breakpoints, SMP debugger, SMP stepping / tracing,
memory editing on APU-bus / VRAM / OAM / CGRAM, save state menu,
WRAM mirroring on breakpoints, protected MMIO memory regions
(otherwise, viewing $002100 could crash your game.)
Major missing components:
- trace mask
- trace mask clear / usage map clear
- window geometry caching / sizing improvements
- VRAM viewer
- properties viewer
- working memory export button
The rest will most likely appear after v086 is released.
]
2012-02-12 05:35:40 +00:00
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uint8 SMP::op_busread(uint16 addr) {
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2011-05-05 11:40:22 +00:00
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unsigned result;
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switch(addr) {
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case 0xf0: //TEST -- write-only register
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return 0x00;
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case 0xf1: //CONTROL -- write-only register
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return 0x00;
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case 0xf2: //DSPADDR
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return status.dsp_addr;
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case 0xf3: //DSPDATA
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//0x80-0xff are read-only mirrors of 0x00-0x7f
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return dsp.read(status.dsp_addr & 0x7f);
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case 0xf4: //CPUIO0
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case 0xf5: //CPUIO1
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case 0xf6: //CPUIO2
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case 0xf7: //CPUIO3
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synchronize_cpu();
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return cpu.port_read(addr);
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case 0xf8: //RAM0
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return status.ram00f8;
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case 0xf9: //RAM1
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return status.ram00f9;
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case 0xfa: //T0TARGET
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case 0xfb: //T1TARGET
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case 0xfc: //T2TARGET -- write-only registers
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return 0x00;
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case 0xfd: //T0OUT -- 4-bit counter value
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2011-06-11 09:14:47 +00:00
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result = timer0.stage3_ticks;
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2011-05-05 11:40:22 +00:00
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timer0.stage3_ticks = 0;
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return result;
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case 0xfe: //T1OUT -- 4-bit counter value
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2011-06-11 09:14:47 +00:00
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result = timer1.stage3_ticks;
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2011-05-05 11:40:22 +00:00
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timer1.stage3_ticks = 0;
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return result;
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case 0xff: //T2OUT -- 4-bit counter value
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2011-06-11 09:14:47 +00:00
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result = timer2.stage3_ticks;
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2011-05-05 11:40:22 +00:00
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timer2.stage3_ticks = 0;
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return result;
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2010-08-09 13:28:56 +00:00
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}
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2011-06-11 09:14:47 +00:00
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return ram_read(addr);
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2010-08-09 13:28:56 +00:00
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}
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Update to v085r08 release.
byuu says:
Changelog:
- follow the Laevateinn topic to get most of it
- also added NMI, IRQ step buttons to CPU debugger
- also added trace masking + trace mask reset
- also added memory export
- cartridge loading is entirely folder-based now
FitzRoy, I'll go ahead and make a second compromise with you for v086:
I'll match the following:
/path/to/SNES.sfc/*.sfc
/path/to/NES.fc/*.prg, *.chr (split format)
/path/to/NES.fc/*.fc (merged format)
/path/to/GB.gb/*.gb
/path/to/GBC.gbc/*.gbc
Condition will be that there can only be one of each file. If there's
more than one, it'll abort. That lets me name my ROMs as
"Game.fc/Game.fc", and you can name yours as "Game.fc/cartridge.prg,
cartridge.chr". Or whatever you want.
We'll just go with that, see what fares out as the most popular, and
then restrict it back to that method.
The folder must have the .fc, etc extension though. That will be how we
avoid false-positive folder matches.
[Editor's note - the Laevateinn topic mentions these changes for
v085r08:
Added SMP/PPU breakpoints, SMP debugger, SMP stepping / tracing,
memory editing on APU-bus / VRAM / OAM / CGRAM, save state menu,
WRAM mirroring on breakpoints, protected MMIO memory regions
(otherwise, viewing $002100 could crash your game.)
Major missing components:
- trace mask
- trace mask clear / usage map clear
- window geometry caching / sizing improvements
- VRAM viewer
- properties viewer
- working memory export button
The rest will most likely appear after v086 is released.
]
2012-02-12 05:35:40 +00:00
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void SMP::op_buswrite(uint16 addr, uint8 data) {
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2011-05-05 11:40:22 +00:00
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switch(addr) {
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case 0xf0: //TEST
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if(regs.p.p) break; //writes only valid when P flag is clear
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status.clock_speed = (data >> 6) & 3;
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status.timer_speed = (data >> 4) & 3;
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status.timers_enable = data & 0x08;
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status.ram_disable = data & 0x04;
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status.ram_writable = data & 0x02;
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status.timers_disable = data & 0x01;
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status.timer_step = (1 << status.clock_speed) + (2 << status.timer_speed);
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timer0.synchronize_stage1();
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timer1.synchronize_stage1();
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timer2.synchronize_stage1();
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break;
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case 0xf1: //CONTROL
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status.iplrom_enable = data & 0x80;
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if(data & 0x30) {
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//one-time clearing of APU port read registers,
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//emulated by simulating CPU writes of 0x00
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synchronize_cpu();
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if(data & 0x20) {
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cpu.port_write(2, 0x00);
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cpu.port_write(3, 0x00);
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}
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if(data & 0x10) {
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cpu.port_write(0, 0x00);
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cpu.port_write(1, 0x00);
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}
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2010-08-09 13:28:56 +00:00
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}
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2011-05-05 11:40:22 +00:00
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//0->1 transistion resets timers
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if(timer2.enable == false && (data & 0x04)) {
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timer2.stage2_ticks = 0;
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timer2.stage3_ticks = 0;
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}
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timer2.enable = data & 0x04;
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if(timer1.enable == false && (data & 0x02)) {
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timer1.stage2_ticks = 0;
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timer1.stage3_ticks = 0;
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}
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timer1.enable = data & 0x02;
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if(timer0.enable == false && (data & 0x01)) {
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timer0.stage2_ticks = 0;
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timer0.stage3_ticks = 0;
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}
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timer0.enable = data & 0x01;
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break;
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case 0xf2: //DSPADDR
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status.dsp_addr = data;
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break;
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case 0xf3: //DSPDATA
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if(status.dsp_addr & 0x80) break; //0x80-0xff are read-only mirrors of 0x00-0x7f
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dsp.write(status.dsp_addr & 0x7f, data);
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break;
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case 0xf4: //CPUIO0
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case 0xf5: //CPUIO1
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case 0xf6: //CPUIO2
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case 0xf7: //CPUIO3
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synchronize_cpu();
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port_write(addr, data);
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break;
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case 0xf8: //RAM0
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status.ram00f8 = data;
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break;
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case 0xf9: //RAM1
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status.ram00f9 = data;
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break;
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case 0xfa: //T0TARGET
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timer0.target = data;
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break;
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case 0xfb: //T1TARGET
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timer1.target = data;
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break;
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case 0xfc: //T2TARGET
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timer2.target = data;
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break;
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case 0xfd: //T0OUT
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case 0xfe: //T1OUT
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case 0xff: //T2OUT -- read-only registers
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break;
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}
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2011-06-11 09:14:47 +00:00
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ram_write(addr, data); //all writes, even to MMIO registers, appear on bus
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2010-08-09 13:28:56 +00:00
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}
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void SMP::op_io() {
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add_clocks(24);
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cycle_edge();
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}
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uint8 SMP::op_read(uint16 addr) {
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add_clocks(12);
|
Update to v094r05 release.
byuu says:
Commands can be prefixed with: (cpu|smp|ppu|dsp|apu|vram|oam|cgram)/ to
set their source. Eg "vram/hex 0800" or "smp/breakpoints.append execute
ffc0"; default is cpu.
These overlap a little bit in odd ways, but that's just the way the SNES
works: it's not a very orthogonal system. CPU is both a processor and
the main bus (ROM, RAM, WRAM, etc), APU is the shared memory by the
SMP+DSP (eg use it to catch writes from either chip); PPU probably won't
ever be used since it's broken down into three separate buses (VRAM,
OAM, CGRAM), but DSP could be useful for tracking bugs like we found in
Koushien 2 with the DSP echo buffer corrupting SMP opcodes. Technically
the PPU memory pools are only ever tripped by the CPU poking at them, as
the PPU doesn't ever write.
I now have run.for, run.to, step.for, step.to. The difference is that
run only prints the next instruction after running, whereas step prints
all of the instructions along the way as well. run.to acts the same as
"step over" here. Although it's not quite as nice, since you have to
specify the address of the next instruction.
Logging the Field/Vcounter/Hcounter on instruction listings now, good
for timing information.
Added in the tracer mask, as well as memory export, as well as
VRAM/OAM/CGRAM/SMP read/write/execute breakpoints, as well as an APU
usage map (it tracks DSP reads/writes separately, although I don't
currently have debugger callbacks on DSP accesses just yet.)
Have not hooked up actual SMP debugging just yet, but I plan to soon.
Still thinking about how I want to allow / block interleaving of
instructions (terminal output and tracing.)
So ... remaining tasks at this point:
- full SMP debugging
- CPU+SMP interleave support
- aliases
- hotkeys
- save states (will be kind of tricky ... will have to suppress
breakpoints during synchronization, or abort a save in a break event.)
- keep track of window geometry between runs
2014-02-05 11:30:08 +00:00
|
|
|
uint8 data = op_busread(addr);
|
2010-08-09 13:28:56 +00:00
|
|
|
add_clocks(12);
|
|
|
|
|
cycle_edge();
|
Update to v094r05 release.
byuu says:
Commands can be prefixed with: (cpu|smp|ppu|dsp|apu|vram|oam|cgram)/ to
set their source. Eg "vram/hex 0800" or "smp/breakpoints.append execute
ffc0"; default is cpu.
These overlap a little bit in odd ways, but that's just the way the SNES
works: it's not a very orthogonal system. CPU is both a processor and
the main bus (ROM, RAM, WRAM, etc), APU is the shared memory by the
SMP+DSP (eg use it to catch writes from either chip); PPU probably won't
ever be used since it's broken down into three separate buses (VRAM,
OAM, CGRAM), but DSP could be useful for tracking bugs like we found in
Koushien 2 with the DSP echo buffer corrupting SMP opcodes. Technically
the PPU memory pools are only ever tripped by the CPU poking at them, as
the PPU doesn't ever write.
I now have run.for, run.to, step.for, step.to. The difference is that
run only prints the next instruction after running, whereas step prints
all of the instructions along the way as well. run.to acts the same as
"step over" here. Although it's not quite as nice, since you have to
specify the address of the next instruction.
Logging the Field/Vcounter/Hcounter on instruction listings now, good
for timing information.
Added in the tracer mask, as well as memory export, as well as
VRAM/OAM/CGRAM/SMP read/write/execute breakpoints, as well as an APU
usage map (it tracks DSP reads/writes separately, although I don't
currently have debugger callbacks on DSP accesses just yet.)
Have not hooked up actual SMP debugging just yet, but I plan to soon.
Still thinking about how I want to allow / block interleaving of
instructions (terminal output and tracing.)
So ... remaining tasks at this point:
- full SMP debugging
- CPU+SMP interleave support
- aliases
- hotkeys
- save states (will be kind of tricky ... will have to suppress
breakpoints during synchronization, or abort a save in a break event.)
- keep track of window geometry between runs
2014-02-05 11:30:08 +00:00
|
|
|
debugger.op_read(addr, data);
|
|
|
|
|
return data;
|
2010-08-09 13:28:56 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void SMP::op_write(uint16 addr, uint8 data) {
|
|
|
|
|
add_clocks(24);
|
|
|
|
|
op_buswrite(addr, data);
|
|
|
|
|
cycle_edge();
|
Update to v094r05 release.
byuu says:
Commands can be prefixed with: (cpu|smp|ppu|dsp|apu|vram|oam|cgram)/ to
set their source. Eg "vram/hex 0800" or "smp/breakpoints.append execute
ffc0"; default is cpu.
These overlap a little bit in odd ways, but that's just the way the SNES
works: it's not a very orthogonal system. CPU is both a processor and
the main bus (ROM, RAM, WRAM, etc), APU is the shared memory by the
SMP+DSP (eg use it to catch writes from either chip); PPU probably won't
ever be used since it's broken down into three separate buses (VRAM,
OAM, CGRAM), but DSP could be useful for tracking bugs like we found in
Koushien 2 with the DSP echo buffer corrupting SMP opcodes. Technically
the PPU memory pools are only ever tripped by the CPU poking at them, as
the PPU doesn't ever write.
I now have run.for, run.to, step.for, step.to. The difference is that
run only prints the next instruction after running, whereas step prints
all of the instructions along the way as well. run.to acts the same as
"step over" here. Although it's not quite as nice, since you have to
specify the address of the next instruction.
Logging the Field/Vcounter/Hcounter on instruction listings now, good
for timing information.
Added in the tracer mask, as well as memory export, as well as
VRAM/OAM/CGRAM/SMP read/write/execute breakpoints, as well as an APU
usage map (it tracks DSP reads/writes separately, although I don't
currently have debugger callbacks on DSP accesses just yet.)
Have not hooked up actual SMP debugging just yet, but I plan to soon.
Still thinking about how I want to allow / block interleaving of
instructions (terminal output and tracing.)
So ... remaining tasks at this point:
- full SMP debugging
- CPU+SMP interleave support
- aliases
- hotkeys
- save states (will be kind of tricky ... will have to suppress
breakpoints during synchronization, or abort a save in a break event.)
- keep track of window geometry between runs
2014-02-05 11:30:08 +00:00
|
|
|
debugger.op_write(addr, data);
|
2010-08-09 13:28:56 +00:00
|
|
|
}
|
|
|
|
|
|
2012-04-29 06:16:44 +00:00
|
|
|
uint8 SMP::disassembler_read(uint16 addr) {
|
|
|
|
|
if((addr & 0xfff0) == 0x00f0) return 0x00;
|
|
|
|
|
if((addr & 0xffc0) == 0xffc0 && status.iplrom_enable) return iplrom[addr & 0x3f];
|
|
|
|
|
return apuram[addr];
|
|
|
|
|
}
|
|
|
|
|
|
2010-08-09 13:28:56 +00:00
|
|
|
#endif
|