![]() -Set the pending cycles for setting Sr1 to 14934 - 3791 instead of adding it. This working makes NO sense in my opinion, and I'm sure it will break as the number of interrupts increases, but for now, it matches up. The newest issue is reading PSG registers which have not been set. Cool, expecting this to work without doing anything would be silly, so I've gotten somewhere! |
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68000 | ||
CP1610 | ||
HuC6280 | ||
MOS 6502X | ||
Native68000 | ||
Z80 | ||
Z80-GB | ||
x86 |