434 lines
8.5 KiB
C#
434 lines
8.5 KiB
C#
using BizHawk.Emulation.Common;
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/*
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$FFFF Interrupt Enable Flag
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$FF80-$FFFE Zero Page - 127 bytes
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$FF00-$FF7F Hardware I/O Registers
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$FEA0-$FEFF Unusable Memory
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$FE00-$FE9F OAM - Object Attribute Memory
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$E000-$FDFF Echo RAM - Reserved, Do Not Use
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$D000-$DFFF Internal RAM - Bank 1-7 (switchable - CGB only)
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$C000-$CFFF Internal RAM - Bank 0 (fixed)
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$A000-$BFFF Cartridge RAM (If Available)
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$9C00-$9FFF BG Map Data 2
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$9800-$9BFF BG Map Data 1
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$8000-$97FF Character RAM
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$4000-$7FFF Cartridge ROM - Switchable Banks 1-xx
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$0150-$3FFF Cartridge ROM - Bank 0 (fixed)
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$0100-$014F Cartridge Header Area
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$0000-$00FF Restart and Interrupt Vectors
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*/
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namespace BizHawk.Emulation.Cores.Nintendo.GBHawk
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{
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public partial class GBHawk
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{
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public byte ReadMemory(ushort addr)
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{
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if (MemoryCallbacks.HasReads)
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{
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uint flags = (uint)MemoryCallbackFlags.AccessRead;
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MemoryCallbacks.CallMemoryCallbacks(addr, 0, flags, "System Bus");
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}
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addr_access = addr;
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if (ppu.DMA_start)
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{
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// some of gekkio's tests require these to be accessible during DMA
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if (addr < 0x8000)
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{
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if (ppu.DMA_addr < 0x80)
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{
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return 0xFF;
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}
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return mapper.ReadMemoryLow(addr);
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}
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if (addr >= 0xA000 && addr < 0xC000 && is_GBC)
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{
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// on GBC only, cart is accessible during DMA
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return mapper.ReadMemoryHigh(addr);
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}
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if (addr >= 0xE000 && addr < 0xF000)
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{
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return RAM[addr - 0xE000];
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}
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if (addr >= 0xF000 && addr < 0xFE00)
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{
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return RAM[(RAM_Bank * 0x1000) + (addr - 0xF000)];
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}
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if (addr >= 0xFE00 && addr < 0xFEA0 && ppu.DMA_OAM_access)
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{
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return OAM[addr - 0xFE00];
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}
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if (addr >= 0xFF00 && addr < 0xFF80) // The game GOAL! Requires Hardware Regs to be accessible
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{
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return Read_Registers(addr);
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}
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if (addr >= 0xFF80)
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{
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if (addr != 0xFFFF)
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{
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return ZP_RAM[addr - 0xFF80];
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}
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else
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{
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return Read_Registers(addr);
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}
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}
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return ppu.DMA_byte;
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}
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if (addr < 0x8000)
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{
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if (addr >= 0x900)
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{
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return mapper.ReadMemoryLow(addr);
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}
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if (addr < 0x100)
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{
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// return Either BIOS ROM or Game ROM
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if ((GB_bios_register & 0x1) == 0)
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{
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return _bios[addr]; // Return BIOS
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}
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return mapper.ReadMemoryLow(addr);
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}
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if (addr >= 0x200)
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{
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// return Either BIOS ROM or Game ROM
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if (((GB_bios_register & 0x1) == 0) && is_GBC)
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{
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return _bios[addr]; // Return BIOS
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}
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return mapper.ReadMemoryLow(addr);
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}
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return mapper.ReadMemoryLow(addr);
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}
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if (addr < 0xA000)
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{
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if (ppu.VRAM_access_read)
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{
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return VRAM[VRAM_Bank * 0x2000 + (addr - 0x8000)];
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}
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return 0xFF;
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}
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if (addr < 0xC000)
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{
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return mapper.ReadMemoryHigh(addr);
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}
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if (addr < 0xFE00)
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{
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addr = (ushort)(RAM_Bank * (addr & 0x1000) + (addr & 0xFFF));
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return RAM[addr];
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}
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if (addr < 0xFEA0)
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{
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if (ppu.OAM_access_read)
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{
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return OAM[addr - 0xFE00];
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}
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return 0xFF;
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}
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if (addr < 0xFF00)
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{
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// unmapped memory, returns 0xFF
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return 0xFF;
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}
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if (addr < 0xFF80)
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{
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return Read_Registers(addr);
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}
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if (addr < 0xFFFF)
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{
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return ZP_RAM[addr - 0xFF80];
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}
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return Read_Registers(addr);
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}
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public void WriteMemory(ushort addr, byte value)
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{
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if (MemoryCallbacks.HasWrites)
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{
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uint flags = (uint)MemoryCallbackFlags.AccessWrite;
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MemoryCallbacks.CallMemoryCallbacks(addr, value, flags, "System Bus");
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}
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addr_access = addr;
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if (ppu.DMA_start)
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{
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// some of gekkio's tests require this to be accessible during DMA
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if (addr >= 0xA000 && addr < 0xC000 && is_GBC)
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{
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// on GBC only, cart is accessible during DMA
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mapper.WriteMemory(addr, value);
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}
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if (addr >= 0xE000 && addr < 0xF000)
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{
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RAM[addr - 0xE000] = value;
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}
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else if (addr >= 0xF000 && addr < 0xFE00)
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{
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RAM[RAM_Bank * 0x1000 + (addr - 0xF000)] = value;
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}
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else if (addr >= 0xFE00 && addr < 0xFEA0 && ppu.DMA_OAM_access)
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{
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OAM[addr - 0xFE00] = value;
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}
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else if (addr >= 0xFF00 && addr < 0xFF80) // The game GOAL! Requires Hardware Regs to be accessible
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{
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Write_Registers(addr, value);
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}
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else if (addr >= 0xFF80)
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{
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if (addr != 0xFFFF)
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{
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ZP_RAM[addr - 0xFF80] = value;
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}
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else
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{
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Write_Registers(addr, value);
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}
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}
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return;
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}
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// Writes are more likely from the top down
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if (addr >= 0xFF00)
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{
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if (addr < 0xFF80)
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{
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Write_Registers(addr, value);
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}
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else if (addr < 0xFFFF)
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{
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ZP_RAM[addr - 0xFF80] = value;
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}
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else
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{
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Write_Registers(addr, value);
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}
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}
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else if (addr >= 0xFE00)
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{
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if (addr < 0xFEA0 && ppu.OAM_access_write)
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{
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OAM[addr - 0xFE00] = value;
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}
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}
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else if (addr >= 0xC000)
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{
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addr = (ushort)(RAM_Bank * (addr & 0x1000) + (addr & 0xFFF));
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RAM[addr] = value;
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}
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else if (addr >= 0xA000)
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{
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mapper.WriteMemory(addr, value);
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}
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else if (addr >= 0x8000)
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{
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if (ppu.VRAM_access_write) { VRAM[(VRAM_Bank * 0x2000) + (addr - 0x8000)] = value; }
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}
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else
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{
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if (addr >= 0x900)
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{
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mapper.WriteMemory(addr, value);
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}
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else
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{
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if (addr < 0x100)
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{
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if ((GB_bios_register & 0x1) == 0)
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{
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// No Writing to BIOS
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}
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else
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{
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mapper.WriteMemory(addr, value);
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}
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}
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else if (addr >= 0x200)
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{
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if ((GB_bios_register & 0x1) == 0 && is_GBC)
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{
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// No Writing to BIOS
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}
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else
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{
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mapper.WriteMemory(addr, value);
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}
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}
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else
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{
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mapper.WriteMemory(addr, value);
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}
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}
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}
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}
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public byte PeekMemory(ushort addr)
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{
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if (ppu.DMA_start)
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{
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// some of gekkio's tests require these to be accessible during DMA
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if (addr < 0x8000)
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{
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if (ppu.DMA_addr < 0x80)
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{
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return 0xFF;
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}
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return mapper.PeekMemoryLow(addr);
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}
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if (addr >= 0xA000 && addr < 0xC000 && is_GBC)
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{
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// on GBC only, cart is accessible during DMA
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return mapper.ReadMemoryHigh(addr);
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}
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if (addr >= 0xE000 && addr < 0xF000)
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{
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return RAM[addr - 0xE000];
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}
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if (addr >= 0xF000 && addr < 0xFE00)
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{
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return RAM[(RAM_Bank * 0x1000) + (addr - 0xF000)];
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}
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if (addr >= 0xFE00 && addr < 0xFEA0 && ppu.DMA_OAM_access)
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{
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return OAM[addr - 0xFE00];
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}
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if (addr >= 0xFF00 && addr < 0xFF80) // The game GOAL! Requires Hardware Regs to be accessible
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{
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return Read_Registers(addr);
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}
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if (addr >= 0xFF80)
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{
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if (addr != 0xFFFF)
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{
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return ZP_RAM[addr - 0xFF80];
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}
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else
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{
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return Read_Registers(addr);
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}
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}
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return ppu.DMA_byte;
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}
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if (addr < 0x8000)
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{
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if (addr >= 0x900)
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{
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return mapper.PeekMemoryLow(addr);
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}
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if (addr < 0x100)
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{
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// return Either BIOS ROM or Game ROM
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if ((GB_bios_register & 0x1) == 0)
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{
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return _bios[addr]; // Return BIOS
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}
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return mapper.PeekMemoryLow(addr);
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}
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if (addr >= 0x200)
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{
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// return Either BIOS ROM or Game ROM
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if (((GB_bios_register & 0x1) == 0) && is_GBC)
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{
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return _bios[addr]; // Return BIOS
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}
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return mapper.PeekMemoryLow(addr);
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}
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return mapper.PeekMemoryLow(addr);
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}
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if (addr < 0xA000)
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{
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if (ppu.VRAM_access_read)
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{
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return VRAM[(VRAM_Bank * 0x2000) + (addr - 0x8000)];
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}
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return 0xFF;
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}
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if (addr < 0xC000)
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{
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return mapper.PeekMemoryHigh(addr);
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}
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if (addr < 0xFE00)
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{
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addr = (ushort)(RAM_Bank * (addr & 0x1000) + (addr & 0xFFF));
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return RAM[addr];
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}
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if (addr < 0xFEA0)
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{
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if (ppu.OAM_access_read)
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{
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return OAM[addr - 0xFE00];
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}
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return 0xFF;
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}
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if (addr < 0xFF00)
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{
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// unmapped memory, returns 0xFF
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return 0xFF;
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}
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if (addr < 0xFF80)
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{
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return Read_Registers(addr);
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}
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if (addr < 0xFFFF)
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{
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return ZP_RAM[addr - 0xFF80];
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}
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return Read_Registers(addr);
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}
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}
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}
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