Commit Graph

13 Commits

Author SHA1 Message Date
brandman211 26b1d06b7a -Simplified the CPU / STIC connection.
-Made FrameAdvance handle the pending cycle loop. During each iteration, it runs one instruction and ticks the STIC accordingly.
2012-08-14 03:58:11 +00:00
brandman211 9100232547 -Made connections between the signal pins on the CP1610 and the STIC.
--Not sure why the STIC has any connection to the SST, but the docs on the SST are virtually non-existent from what I could find.
--I took advantage of Func and Action instead of passing bool references to both devices. I think this makes sense.
-Added reset functions for both devices.

My comparison log for INTRM is still weird because it says it is true initially (Expected) and remains as such after the first instruction (A bit odd). I think this happens because the STIC is supposed to "tick" and shift SR1 to false immediately, but the STIC tick happens after the CPU tick, and the CPU tick is where the logging happens. I need to find a better place to put this logging, and I need to implement the STIC ticking for IntelliHawk. I'm not positive how to approach the latter issue as I assume a tick means one instruction execution, and my executions happen in a loop on the CPU, which has no reference to the STIC, so I'm not sure where this fits into the equation.
2012-08-13 08:10:15 +00:00
brandman211 c6cf18061f Scratchpad RAM, Graphics ROM, and Graphics RAM are apparently all 8-bit. 2012-08-10 20:40:34 +00:00
brandman211 5239b4f55b -Separated the STIC and PSG memory map logic into new objects.
-Foreground / Background | Color Stack Mode
--Actually made a boolean for it (FGBG).
--Reading from a write-only STIC alias of $21 does change the STIC into Color Stack mode, but it doesn't actually read.
--Color stack mode is enabled when $21 or its alias is read and it is disabled (FGBG) when written its written, both having to occur during VBlank Period 1.
---This is what I gathered from the wiki, but I'm confused as to why it says that "The STIC stays in this mode until the program accesses location $21 again." I'm assuming this doesn't mean the mode changes on every access because then I don't understand why a read would change to a different mode than a write.
--FGBG is disabled by default. I don't think it matters.
2012-08-08 23:05:55 +00:00
brandman211 0d20c133a5 -Moved the reset address to the CP1610 and made RegisterSP/PC private.
-Created helper functions for indirect ops; Indirect_Set will be needed for interrupts.
2012-08-06 15:51:35 +00:00
brandman211 b83bb1901d -When neither the cartridge nor hardware responds to a read, it now returns 0xFFFF instead of throwing an exception.
-I will now assume that 0x7000 is not mapped for the sake of continuing on. I will need to implement a mapper system shortly though.
--Did the same thing for 0x4800.
-AND@, MOVR, CMP enabled.
-Made the logging separator generate before an instruction instead of after the register states. This is quite petty, but I don't like the separator at the end of the file.

I hit an infinite loop, and I'm very very certain it's happening because I don't have an interrupt system yet. Time to stop avoiding that!
2012-08-05 05:59:55 +00:00
brandman211 80a0f8f75b -Made Intellicart its own class.
-Separated cartridge logic into a separate ICart named Cartridge.cs.
-Made WriteMemory return a bool to match ICart.Write. It currently returns true if either the cart or the core responded.

TODO: Parse the vanilla Intellivision ROM, which will hopefully include the read / writability of the data segments. adelikat seems to think that I just need to send the bytes to $5000, but I'm not convinced.
2012-07-31 06:54:20 +00:00
brandman211 9f2bcf3318 -Fixed logging.
--It now just builds a strings and writes on finalization.
-Fixed up format strings.
-As RegisterPC already increments upon reading the third decle, I now just store PC as the return address for jumping instead of PC + 1.
2012-07-22 18:08:10 +00:00
brandman211 60c5a1ce58 Added logging for the CP1610. Not working for some reason. 2012-07-22 17:18:11 +00:00
brandman211 e73c48219a -Loaded EROM / GROM.
-Fixed disassembly for JMP:
--Now it uses the parameter pc, not RegisterPC.
--I was loading both the second and third value from the second's address.
--Casting the calculated addresses to bytes when addresses are 16-bit was a bad idea.
--Removed a closing parenthesis I accidentally stuck in the formatting.

It seems that I've gotten far enough to use the Executive ROM as a test case! Now to go instruction by instruction and see if they work as planned and hope this will all eventually make something.
2012-07-19 00:05:08 +00:00
brandman211 4f9539b73c -Made Executive ROM and Graphics ROM read-only. I still haven't made the memory map accessibility limited by the VBlank Period, but I'm assuming that should come way later.
-Initialized the memory devices with a tentative size that ignores the unofficial ranges.
-Masked addresses to match those sizes (That's my understanding of what the memory map needs to do based on other examples).
-Added the ICart interface.
-Started the Intellicart parser; got far enough to know that the files I'm working with are not Intellicarts. ^_^
2012-07-15 08:38:50 +00:00
brandman211 104511c5b7 -Intellivision.cs' constructor initializes the PC to 0x1000.
-Set up the "official" memory map - see http://wiki.intellivision.us/index.php?title=Memory_Map
--Things I didn't do:
---Accessibility.
---Additional Occupied Memory Ranges.
---Addresses Available to Cartridges
---Initialize any of the byte arrays.
--Not sure which of these I need to do, but clearly the byte arrays have to be initialized somewhere to something and there's a lot of gaps in this memory map.
2012-07-09 05:29:45 +00:00
beirich 36ba018ae0 basic wire-up of Intellivision core 2012-07-08 04:20:53 +00:00