saxxonpike
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c0bad5eccb
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Commodore64: Rewrote the character graphics generator as a shift register like real equipment. Roughly 10% performance increase and looks great. Sprites need work yet.
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2013-08-25 00:31:52 +00:00 |
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saxxonpike
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1c18da52b3
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Commodore64: Border unit implemented fully, timing is much better now and works for both PAL and NTSC.
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2013-08-24 20:13:16 +00:00 |
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saxxonpike
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4ef73eb676
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Fix some compiler warnings. Border is still odd, needs the other half of the border unit logic. Also, a marginal performance boost from sealing classes.
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2013-08-24 17:30:46 +00:00 |
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saxxonpike
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228fa3869f
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Video chip timing in the old core now builds its timing tables dynamically instead of having them hardcoded- should greatly reduce human error. The algorithm should cover every single revision of VIC.
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2013-08-24 15:21:51 +00:00 |
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saxxonpike
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b5fcb81727
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Commodore64: Save states implemented.
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2013-08-19 03:42:40 +00:00 |
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saxxonpike
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a3b1fb3c36
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Commodore64: Interrupt and timer chip tweaks.
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2013-08-17 10:46:27 +00:00 |
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adelikat
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cff1ff2940
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Removing unused directives from a bunch of files because I was playing around with resharper, but that got boring so not every file
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2013-04-14 20:39:19 +00:00 |
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saxxonpike
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31fba1ec2b
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commodore64: change from uint to int, seems to speed things up a little with no side effects
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2012-12-11 06:27:00 +00:00 |
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saxxonpike
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c64951fce8
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commodore64: implement motherboard configuration, add sprite-sprite and sprite-data collision interrupts to VIC
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2012-12-05 21:07:51 +00:00 |
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saxxonpike
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1eca7805cf
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commodore64: add cartridge mapper 0012 (Zaxxon, Super Zaxxon), fix mapper 0000 to support 4k roms
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2012-11-29 16:33:04 +00:00 |
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saxxonpike
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27217f119d
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commodore64: adjusted BA timing for PAL (it was taking one cycle too many), makes a lot of timing-sensitive games and demos run better
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2012-11-28 21:09:45 +00:00 |
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saxxonpike
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8e55810161
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commodore64: more video function implemented in the new system, 12 pixel delay also applied to border
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2012-11-28 06:21:52 +00:00 |
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saxxonpike
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95d228f413
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commodore64: new core with focus on low-level comm between chips and activity on both phases of the clock
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2012-11-27 05:11:40 +00:00 |