Commit Graph

16 Commits

Author SHA1 Message Date
Brian Armstrong 2c6ecb68bd Merge branch 'master' into brian/mem_callback_addr_value 2019-06-06 02:11:04 -07:00
Brian Armstrong d41bd867b8 flags 2019-06-06 02:04:47 -07:00
James Groom 4e91f88af3
Use nameof in cores 2019-03-28 14:18:58 +11:00
Brian Armstrong a8f293eec8 Call mem callbacks with addr, value 2019-01-24 03:23:21 -08:00
adelikat cd289c474e memorycallbacks with domains - Phase 2 - change api to Call methods and refactor accordingly, everything should behave as it was before the refactor at this point. No cores have yet to be implemented with domains other than the default bus they already had 2017-08-03 18:08:07 -05:00
adelikat 8ad021c6fd Intellivision - implement memory callbacks 2017-04-23 13:28:40 -05:00
adelikat d03577ade6 Intellivision - partially implement IDebuggable - flag/register getting and setting, and TotalExecutedCycles 2017-04-23 12:30:41 -05:00
alyosha-tas 2526f8c7b9 Update CP1610 2017-03-05 18:44:34 -05:00
alyosha-tas a36b7093e3 Intellivision implement System Bus memory domain 2017-02-09 12:53:55 -05:00
adelikat eb1f477f9d Intellivision - turn off logging 2017-02-08 17:26:30 -06:00
J.D. Purcell 206ea9887b Text savestate fixes. 2016-12-14 18:35:03 -05:00
alyosha-tas 33843265f8 Update CP1610 to include Halts from SR2 2016-12-13 16:47:21 -05:00
alyosha-tas ba149320c5 INtellivision fill out save states 2016-12-07 10:55:25 -05:00
alyosha-tas c230609656 Cp1610 trace logger
WIP
2016-11-12 12:58:10 -05:00
adelikat e44493d9fb Intellivision - wire up trace logger to the core. Currently does nothing since the TraceCallback in CP1610 needs to be wired up in the object in the right places 2016-11-11 16:17:35 -06:00
adelikat 7393f132ab Move CPUs from Emulation.Common to Emulation.Cores 2014-01-22 01:14:36 +00:00