Commit Graph

23 Commits

Author SHA1 Message Date
SaxxonPike d39f3e2e61 6502X: pending IRQs are not delayed when !RDY is asserted 2019-07-13 12:31:09 -05:00
SaxxonPike bf2cba0e23 6502X: remove a comment (this is indeed a dummy fetch) 2019-07-13 11:38:03 -05:00
SaxxonPike 9758efe604 6502X: CPU does a read or write regardless if the result is trashed, even during reset and dummy pushes 2019-07-09 19:46:33 -05:00
SaxxonPike 3efea15038 6502X: When !RDY is asserted, still do other operations. Plus, do dummy reads on stack ops 2019-07-09 05:24:47 -05:00
SaxxonPike d48964b642 6502X: According to the datasheet, RDY must be high in order for interrupts to trigger
- this has implications for C64, as it may cause VIC interrupts to fire quite later than they currently do
2019-07-06 00:00:51 -05:00
SaxxonPike cb48104d7a 6502X: Fix ADC with decimal mode enabled. 2019-07-03 23:49:55 -05:00
alyosha-tas 69fe1bdf97 NESHawk: VRAM write timing glitch 2018-12-16 13:10:04 -06:00
Scepheo f3ea6fe025 Use generic interface type on MOS 6052X for talking to the emulator core (#1189)
* Use generic interface type on MOS 6052X for talking to the emulator core
* Change CpuLink constructors to not use expression-bodies, to get the AppVeyor build to pass.
* Add comment explaining why IMOS6502XLink exists.
2018-05-20 23:18:53 +03:00
alyosha-tas 0e0d3e4143 Update Execute.cs 2017-06-17 19:01:04 -04:00
J.D. Purcell b53502eed8 Spaces -> tabs. 2017-04-15 16:37:30 -04:00
alyosha-tas 3ac053c33d Update 6502 reset 2017-03-08 12:19:31 -05:00
alyosha-tas 1c9d814e15 Add files via upload 2016-06-24 15:02:50 -04:00
Tony Konzel d518db2d14 6502: RTS IncPc micro-op should perform a read at PC and discard the result. 2016-06-22 15:09:57 -05:00
alyosha-tas 55feae8bf6 clean up and minor fixes 2016-06-16 11:29:08 -04:00
alyosha-tas b7c8755b14 Fill in some undocumented opcodes
now passes instr_misc/instr_misc (the only test I could find that even concerned itself with these opcodes)
2016-06-15 22:33:15 -04:00
Anthony Konzel aa83c33c58 6502: All non-writes are affected by RDY. 2016-03-09 20:12:49 -06:00
adelikat f5e679fa0d Refactor ITraceable to work on TraceInfo objects that separate Disassembly and Register information. Make Tracelogger two columns. 2016-02-21 17:34:42 -05:00
zeromus 91d070094d 6502 cpu core: make JAM/KIL actually do something like the right thing 2015-12-31 11:43:38 -06:00
Kabuto f7c15bfd0f Fixed indentation and TODOs 2015-09-28 20:53:19 +02:00
Kabuto 1e9564a337 C64 core: tape loading added, lots of bugfixes and improvements 2015-09-28 01:30:58 +02:00
adelikat f546a8080c Move some extension methods from the generic extensions file to NumberExtensions and fix up namespaces 2014-07-03 15:35:50 +00:00
goyuken 4ada3b4973 NES: fix tracelogger for first instruction of NMI or IRQ. also make it obviously indicate that an NMI or IRQ has occurred 2014-02-12 22:01:23 +00:00
adelikat 7393f132ab Move CPUs from Emulation.Common to Emulation.Cores 2014-01-22 01:14:36 +00:00