parent
7e6e9705ae
commit
e7c093eac6
Binary file not shown.
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@ -60,8 +60,8 @@ void DebugMessage(int level, const char *message, ...)
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if(level == M64MSG_ERROR)
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{
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//trigger a vsync just to get out of frame advance
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new_vi();
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//trigger a vsync just to get out of frame advance
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new_vi();
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WaitForSingleObject(rompausesem, INFINITE);
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}
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@ -106,8 +106,8 @@ void dma_pi_read(void)
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{
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for (i=0; i < (pi_register.pi_rd_len_reg & 0xFFFFFF)+1; i++)
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{
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sram[((pi_register.pi_cart_addr_reg-0x08000000)+i)^S8] =
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((unsigned char*)rdram)[(pi_register.pi_dram_addr_reg+i)^S8];
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sram[MASK_ADDR_U8(((pi_register.pi_cart_addr_reg-0x08000000)+i)^S8, sram)] =
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((unsigned char*)rdram)[MASK_ADDR_U8((pi_register.pi_dram_addr_reg+i)^S8, rdram)];
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}
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sram_write_file();
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@ -145,8 +145,8 @@ void dma_pi_write(void)
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for (i=0; i<(int)(pi_register.pi_wr_len_reg & 0xFFFFFF)+1; i++)
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{
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((unsigned char*)rdram)[(pi_register.pi_dram_addr_reg+i)^S8]=
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sram[(((pi_register.pi_cart_addr_reg-0x08000000)&0xFFFF)+i)^S8];
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((unsigned char*)rdram)[MASK_ADDR_U8((pi_register.pi_dram_addr_reg+i)^S8, rdram)]=
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sram[MASK_ADDR_U8((((pi_register.pi_cart_addr_reg-0x08000000)&0xFFFF)+i)^S8, sram)];
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}
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flashram_info.use_flashram = -1;
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@ -204,8 +204,8 @@ void dma_pi_write(void)
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unsigned long rdram_address1 = pi_register.pi_dram_addr_reg+i+0x80000000;
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unsigned long rdram_address2 = pi_register.pi_dram_addr_reg+i+0xa0000000;
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((unsigned char*)rdram)[(pi_register.pi_dram_addr_reg+i)^S8]=
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rom[(((pi_register.pi_cart_addr_reg-0x10000000)&0x3FFFFFF)+i)^S8];
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((unsigned char*)rdram)[MASK_ADDR_U8((pi_register.pi_dram_addr_reg+i)^S8, rdram)]=
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rom[MASK_ADDR_U8((((pi_register.pi_cart_addr_reg-0x10000000)&0x3FFFFFF)+i)^S8, rom)];
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if (!invalid_code[rdram_address1>>12])
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{
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@ -234,8 +234,8 @@ void dma_pi_write(void)
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{
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for (i=0; i<(int)longueur; i++)
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{
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((unsigned char*)rdram)[(pi_register.pi_dram_addr_reg+i)^S8]=
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rom[(((pi_register.pi_cart_addr_reg-0x10000000)&0x3FFFFFF)+i)^S8];
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((unsigned char*)rdram)[MASK_ADDR_U8((pi_register.pi_dram_addr_reg+i)^S8, rdram)]=
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rom[MASK_ADDR_U8((((pi_register.pi_cart_addr_reg-0x10000000)&0x3FFFFFF)+i)^S8, rom)];
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}
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}
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@ -300,7 +300,7 @@ void dma_sp_write(void)
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for(j=0; j<count; j++) {
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for(i=0; i<length; i++) {
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spmem[memaddr^S8] = dram[dramaddr^S8];
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spmem[MASK_ADDR_U8(memaddr^S8, SP_DMEM)] = dram[MASK_ADDR_U8(dramaddr^S8, rdram)];
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memaddr++;
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dramaddr++;
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}
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@ -326,7 +326,7 @@ void dma_sp_read(void)
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for(j=0; j<count; j++) {
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for(i=0; i<length; i++) {
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dram[dramaddr^S8] = spmem[memaddr^S8];
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dram[MASK_ADDR_U8(dramaddr^S8, rdram)] = spmem[MASK_ADDR_U8(memaddr^S8, SP_DMEM)];
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memaddr++;
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dramaddr++;
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}
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@ -345,7 +345,7 @@ void dma_si_write(void)
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for (i=0; i<(64/4); i++)
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{
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PIF_RAM[i] = sl(rdram[si_register.si_dram_addr/4+i]);
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PIF_RAM[i] = sl(rdram[MASK_ADDR_U32(si_register.si_dram_addr/4+i, rdram)]);
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}
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update_pif_write();
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@ -366,7 +366,7 @@ void dma_si_read(void)
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for (i=0; i<(64/4); i++)
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{
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rdram[si_register.si_dram_addr/4+i] = sl(PIF_RAM[i]);
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rdram[MASK_ADDR_U32(si_register.si_dram_addr/4+i, rdram)] = sl(PIF_RAM[i]);
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}
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update_count();
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@ -135,7 +135,7 @@ void flashram_command(unsigned int command)
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unsigned int i;
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for (i=flashram_info.erase_offset; i<(flashram_info.erase_offset+128); i++)
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{
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flashram[i^S8] = 0xff;
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flashram[MASK_ADDR_U8(i^S8, flashram)] = 0xff;
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}
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flashram_write_file();
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}
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@ -145,8 +145,8 @@ void flashram_command(unsigned int command)
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int i;
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for (i=0; i<128; i++)
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{
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flashram[(flashram_info.erase_offset+i)^S8]=
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((unsigned char*)rdram)[(flashram_info.write_pointer+i)^S8];
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flashram[MASK_ADDR_U8((flashram_info.erase_offset+i)^S8, flashram)]=
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((unsigned char*)rdram)[MASK_ADDR_U8((flashram_info.write_pointer+i)^S8, rdram)];
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}
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flashram_write_file();
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}
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@ -180,14 +180,14 @@ void dma_read_flashram(void)
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switch (flashram_info.mode)
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{
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case STATUS_MODE:
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rdram[pi_register.pi_dram_addr_reg/4] = (unsigned int)(flashram_info.status >> 32);
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rdram[pi_register.pi_dram_addr_reg/4+1] = (unsigned int)(flashram_info.status);
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rdram[MASK_ADDR_U32(pi_register.pi_dram_addr_reg/4, rdram)] = (unsigned int)(flashram_info.status >> 32);
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rdram[MASK_ADDR_U32(pi_register.pi_dram_addr_reg/4+1, rdram)] = (unsigned int)(flashram_info.status);
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break;
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case READ_MODE:
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for (i=0; i<(pi_register.pi_wr_len_reg & 0x0FFFFFF)+1; i++)
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{
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((unsigned char*)rdram)[(pi_register.pi_dram_addr_reg+i)^S8]=
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flashram[(((pi_register.pi_cart_addr_reg-0x08000000)&0xFFFF)*2+i)^S8];
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((unsigned char*)rdram)[MASK_ADDR_U8((pi_register.pi_dram_addr_reg+i)^S8, rdram)]=
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flashram[MASK_ADDR_U8((((pi_register.pi_cart_addr_reg-0x08000000)&0xFFFF)*2+i)^S8, rdram)];
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}
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break;
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default:
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@ -26,6 +26,9 @@
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#define TRACECB() if (traceCB) traceCB()
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#define MASK_ADDR_U8(x, m) (x) & (sizeof(m) - 1)
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#define MASK_ADDR_U32(x, m) (x) & (sizeof(m) / 4 - 1)
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int init_memory(int DoByteSwap);
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void free_memory(void);
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#define read_word_in_memory() readmem[address>>16]()
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@ -91,7 +91,7 @@ static void eeprom_write_file(void)
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free(filename);*/
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saveramModified = 1;
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saveramModified = 1;
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}
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/*static char *get_mempack_path(void)
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free(filename);*/
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saveramModified = 1;
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saveramModified = 1;
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}
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//#define DEBUG_PIF
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@ -302,15 +302,17 @@ static unsigned char mempack_crc(unsigned char *data)
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return CRC;
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}
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static void internal_ReadController(int Control, unsigned char *Command)
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static void internal_ReadController(int Control, unsigned char *Command, unsigned int Remaining)
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{
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if (Remaining <= 2) return;
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switch (Command[2])
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{
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case 1:
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#ifdef DEBUG_PIF
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DebugMessage(M64MSG_INFO, "internal_ReadController() Channel %i Command 1 read buttons", Control);
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#endif
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if (Controls[Control].Present)
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if (Controls[Control].Present && Remaining > 6)
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{
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BUTTONS Keys;
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input.getKeys(Control, &Keys);
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#ifdef DEBUG_PIF
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DebugMessage(M64MSG_INFO, "internal_ReadController() Channel %i Command 2 read controller pack (in Input plugin)", Control);
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#endif
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if (Controls[Control].Present)
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if (Controls[Control].Present && Remaining > 37)
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{
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if (Controls[Control].Plugin == PLUGIN_RAW)
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if (input.readController)
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#ifdef DEBUG_PIF
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DebugMessage(M64MSG_INFO, "internal_ReadController() Channel %i Command 3 write controller pack (in Input plugin)", Control);
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#endif
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if (Controls[Control].Present)
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if (Controls[Control].Present && Remaining > 37)
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{
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if (Controls[Control].Plugin == PLUGIN_RAW)
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if (input.readController)
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}
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}
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static void internal_ControllerCommand(int Control, unsigned char *Command)
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static void internal_ControllerCommand(int Control, unsigned char *Command, unsigned int Remaining)
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{
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if (Remaining <= 2) return;
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switch (Command[2])
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{
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case 0x00: // read status
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#ifdef DEBUG_PIF
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DebugMessage(M64MSG_INFO, "internal_ControllerCommand() Channel %i Command %02x check pack present", Control, Command[2]);
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#endif
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if (Controls[Control].Present)
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if (Controls[Control].Present && Remaining > 5)
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{
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Command[3] = 0x05;
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Command[4] = 0x00;
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Command[1] |= 0x80;
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break;
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case 0x02: // read controller pack
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if (Controls[Control].Present)
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if (Controls[Control].Present && Remaining > 0x25)
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{
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switch (Controls[Control].Plugin)
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{
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Command[1] |= 0x80;
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break;
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case 0x03: // write controller pack
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if (Controls[Control].Present)
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if (Controls[Control].Present && Remaining > 0x25)
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{
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switch (Controls[Control].Plugin)
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{
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Controls[channel].RawData)
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input.controllerCommand(channel, &PIF_RAMb[i]);
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else
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internal_ControllerCommand(channel, &PIF_RAMb[i]);
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internal_ControllerCommand(channel, &PIF_RAMb[i], 0x40 - i);
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}
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else if (channel == 4)
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EepromCommand(&PIF_RAMb[i]);
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if (channel < 4)
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{
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if (Controls[channel].Present &&
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Controls[channel].RawData)
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input.readController(channel, &PIF_RAMb[i]);
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Controls[channel].RawData)
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{
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unsigned int remaining = 0x40 - i;
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unsigned int needed = 3;
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if (remaining > 2)
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{
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switch (PIF_RAMb[i + 2])
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{
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case 0x00:
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case 0xFF:
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needed = 6;
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break;
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case 0x01:
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needed = 7;
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break;
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case 0x02:
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case 0x03:
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needed = 38;
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break;
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}
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}
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if (remaining >= needed)
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input.readController(channel, &PIF_RAMb[i]);
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}
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else
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internal_ReadController(channel, &PIF_RAMb[i]);
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internal_ReadController(channel, &PIF_RAMb[i], 0x40 - i);
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}
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i += PIF_RAMb[i] + (PIF_RAMb[(i+1)] & 0x3F) + 1;
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channel++;
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EXPORT void CALL init_saveram(void)
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{
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eeprom_format();
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mempack_format();
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saveramModified = 0;
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eeprom_format();
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mempack_format();
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saveramModified = 0;
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flashram_format();
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flashram_format();
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sram_format();
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sram_format();
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}
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EXPORT void CALL save_saveram(unsigned char * dest)
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{
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memcpy(dest, eeprom, 0x800);
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memcpy(dest + 0x800, mempack, 4 * 0x8000);
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memcpy(dest + (0x800 + 4 * 0x8000), flashram, 0x20000);
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memcpy(dest + (0x800 + 4 * 0x8000 + 0x20000), sram, 0x8000);
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memcpy(dest, eeprom, 0x800);
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memcpy(dest + 0x800, mempack, 4 * 0x8000);
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memcpy(dest + (0x800 + 4 * 0x8000), flashram, 0x20000);
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memcpy(dest + (0x800 + 4 * 0x8000 + 0x20000), sram, 0x8000);
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}
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EXPORT void CALL load_saveram(unsigned char * src)
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{
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memcpy(eeprom, src, 0x800);
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memcpy(mempack, src + 0x800, 4 * 0x8000);
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memcpy(flashram, src + (0x800 + 4 * 0x8000), 0x20000);
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memcpy(sram, src + (0x800 + 4 * 0x8000 + 0x20000), 0x8000);
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memcpy(eeprom, src, 0x800);
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memcpy(mempack, src + 0x800, 4 * 0x8000);
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memcpy(flashram, src + (0x800 + 4 * 0x8000), 0x20000);
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memcpy(sram, src + (0x800 + 4 * 0x8000 + 0x20000), 0x8000);
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}
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@ -127,7 +127,7 @@ void add_interupt_event(int type, unsigned int delay)
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if (get_event(type)) {
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DebugMessage(M64MSG_WARNING, "two events of type 0x%x in interrupt queue", type);
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return;
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return;
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}
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if (q == NULL)
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@ -384,7 +384,7 @@ void gen_interupt(void)
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#ifdef WITH_LIRC
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lircCheckInput();
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#endif
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SDL_PumpEvents();
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//SDL_PumpEvents();
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refresh_stat();
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// {
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//SDL_Delay(10);
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SDL_PumpEvents();
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//SDL_PumpEvents();
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#ifdef WITH_LIRC
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lircCheckInput();
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#endif //WITH_LIRC
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@ -405,7 +405,7 @@ void gen_interupt(void)
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//}
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new_vi();
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WaitForSingleObject(rompausesem, INFINITE);
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WaitForSingleObject(rompausesem, INFINITE);
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if (vi_register.vi_v_sync == 0) vi_register.vi_delay = 500000;
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else vi_register.vi_delay = ((vi_register.vi_v_sync + 1)*1500);
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next_vi += vi_register.vi_delay;
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@ -443,7 +443,7 @@ void gen_interupt(void)
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#ifdef WITH_LIRC
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lircCheckInput();
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#endif //WITH_LIRC
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SDL_PumpEvents();
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//SDL_PumpEvents();
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PIF_RAMb[0x3F] = 0x0;
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remove_interupt_event();
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MI_register.mi_intr_reg |= 0x02;
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