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z80: Bus timing on interrupts

This commit is contained in:
alyosha-tas 2018-06-04 08:57:12 -04:00
parent 1125ccedc3
commit 9f4b6f1ecf
2 changed files with 35 additions and 20 deletions
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48
BizHawk.Emulation.Cores/CPUs/Z80A/Interrupts.cs
View File

@ -34,16 +34,18 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
{ {
cur_instr = new ushort[] cur_instr = new ushort[]
{DEC16, SPl, SPh, {DEC16, SPl, SPh,
TR, ALU, PCl,
WAIT, WAIT,
WR, SPl, SPh, PCh, WR_DEC, SPl, SPh, PCh,
DEC16, SPl, SPh, TR16, PCl, PCh, NMI_V, ZERO,
WAIT, WAIT,
WR, SPl, SPh, PCl, WR, SPl, SPh, ALU,
ASGN, PCl, 0x66, IDLE,
ASGN, PCh, 0,
WAIT, WAIT,
OP_F, OP_F,
OP }; OP };
BUSRQ = new ushort[] { 0, SPl, 0, 0, SPl, 0, 0, PCl, 0, 0, 0 };
} }
// Mode 0 interrupts only take effect if a CALL or RST is on the data bus // Mode 0 interrupts only take effect if a CALL or RST is on the data bus
@ -56,55 +58,61 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
cur_instr = new ushort[] cur_instr = new ushort[]
{IDLE, {IDLE,
WAIT, WAIT,
RD, ALU, PCl, PCh, RD_INC, ALU, PCl, PCh,
INC16, PCl, PCh, IDLE,
WAIT, WAIT,
OP_F, OP_F,
OP }; OP };
BUSRQ = new ushort[] { PCl, 0, 0, PCl, 0, 0, 0 };
} }
// Just jump to $0038 // Just jump to $0038
private void INTERRUPT_1() private void INTERRUPT_1()
{ {
cur_instr = new ushort[] cur_instr = new ushort[]
{DEC16, SPl, SPh, {IDLE,
WAIT, ASGN, ALU, PCl,
WR, SPl, SPh, PCh,
DEC16, SPl, SPh, DEC16, SPl, SPh,
WAIT,
WR, SPl, SPh, PCl,
ASGN, PCl, 0x38,
IDLE, IDLE,
ASGN, PCh, 0, WAIT,
WR_DEC, SPl, SPh, PCh,
TR16, PCl, PCh, IRQ_V, ZERO,
WAIT,
WR, SPl, SPh, ALU,
IDLE, IDLE,
WAIT, WAIT,
OP_F, OP_F,
OP }; OP };
BUSRQ = new ushort[] { 0, 0, 0, SPl, 0, 0, SPl, 0, 0, PCl, 0, 0, 0 };
} }
// Interrupt mode 2 uses the I vector combined with a byte on the data bus // Interrupt mode 2 uses the I vector combined with a byte on the data bus
private void INTERRUPT_2() private void INTERRUPT_2()
{ {
cur_instr = new ushort[] cur_instr = new ushort[]
{IDLE, {FTCH_DB,
WAIT, IDLE,
FTCH_DB,
TR16, Z, W, DB, I,
DEC16, SPl, SPh, DEC16, SPl, SPh,
TR16, Z, W, DB, I,
WAIT, WAIT,
WR, SPl, SPh, PCh, WR_DEC, SPl, SPh, PCh,
DEC16, SPl, SPh, IDLE,
WAIT, WAIT,
WR, SPl, SPh, PCl, WR, SPl, SPh, PCl,
IDLE, IDLE,
WAIT, WAIT,
RD_INC, PCl, Z, W, RD_INC, PCl, Z, W,
IDLE, IDLE,
WAIT,
RD, PCh, Z, W, RD, PCh, Z, W,
IDLE, IDLE,
WAIT, WAIT,
OP_F, OP_F,
OP }; OP };
BUSRQ = new ushort[] { 0, 0, 0, SPl, 0, 0, SPl, 0, 0, Z, 0, 0, Z, 0 ,0 ,PCl, 0, 0, 0 };
} }
private static ushort[] INT_vectors = new ushort[] {0x40, 0x48, 0x50, 0x58, 0x60}; private static ushort[] INT_vectors = new ushort[] {0x40, 0x48, 0x50, 0x58, 0x60};

7
BizHawk.Emulation.Cores/CPUs/Z80A/Registers.cs
View File

@ -40,6 +40,8 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
public ushort H_s = 30; public ushort H_s = 30;
public ushort L_s = 31; public ushort L_s = 31;
public ushort DB = 32; public ushort DB = 32;
public ushort IRQ_V = 34; // IRQ mode 1 vector
public ushort NMI_V = 35; // NMI vector
public ushort[] Regs = new ushort[36]; public ushort[] Regs = new ushort[36];
@ -112,6 +114,11 @@ namespace BizHawk.Emulation.Cores.Components.Z80A
Regs[i] = 0; Regs[i] = 0;
} }
// the IRQ1 vector is 0x38
Regs[IRQ_V] = 0x38;
// The NMI vector is constant 0x66
Regs[NMI_V] = 0x66;
FlagI = false; FlagI = false;
FlagW = false; FlagW = false;
} }