Add files via upload
This commit is contained in:
parent
258688ebdd
commit
946c025cd6
|
@ -12,36 +12,36 @@ namespace BizHawk.Emulation.Cores.Calculators
|
|||
{
|
||||
return new Dictionary<string, RegisterValue>
|
||||
{
|
||||
["A"] = _cpu.RegisterA,
|
||||
["AF"] = _cpu.RegisterAF,
|
||||
["B"] = _cpu.RegisterB,
|
||||
["BC"] = _cpu.RegisterBC,
|
||||
["C"] = _cpu.RegisterC,
|
||||
["D"] = _cpu.RegisterD,
|
||||
["DE"] = _cpu.RegisterDE,
|
||||
["E"] = _cpu.RegisterE,
|
||||
["F"] = _cpu.RegisterF,
|
||||
["H"] = _cpu.RegisterH,
|
||||
["HL"] = _cpu.RegisterHL,
|
||||
["I"] = _cpu.RegisterI,
|
||||
["IX"] = _cpu.RegisterIX,
|
||||
["IY"] = _cpu.RegisterIY,
|
||||
["L"] = _cpu.RegisterL,
|
||||
["PC"] = _cpu.RegisterPC,
|
||||
["R"] = _cpu.RegisterR,
|
||||
["Shadow AF"] = _cpu.RegisterShadowAF,
|
||||
["Shadow BC"] = _cpu.RegisterShadowBC,
|
||||
["Shadow DE"] = _cpu.RegisterShadowDE,
|
||||
["Shadow HL"] = _cpu.RegisterShadowHL,
|
||||
["SP"] = _cpu.RegisterSP,
|
||||
["Flag C"] = _cpu.RegisterF.Bit(0),
|
||||
["Flag N"] = _cpu.RegisterF.Bit(1),
|
||||
["Flag P/V"] = _cpu.RegisterF.Bit(2),
|
||||
["Flag 3rd"] = _cpu.RegisterF.Bit(3),
|
||||
["Flag H"] = _cpu.RegisterF.Bit(4),
|
||||
["Flag 5th"] = _cpu.RegisterF.Bit(5),
|
||||
["Flag Z"] = _cpu.RegisterF.Bit(6),
|
||||
["Flag S"] = _cpu.RegisterF.Bit(7)
|
||||
["A"] = _cpu.Regs[_cpu.A],
|
||||
["AF"] = _cpu.Regs[_cpu.F] + (_cpu.Regs[_cpu.A] << 8),
|
||||
["B"] = _cpu.Regs[_cpu.B],
|
||||
["BC"] = _cpu.Regs[_cpu.C] + (_cpu.Regs[_cpu.B] << 8),
|
||||
["C"] = _cpu.Regs[_cpu.C],
|
||||
["D"] = _cpu.Regs[_cpu.D],
|
||||
["DE"] = _cpu.Regs[_cpu.E] + (_cpu.Regs[_cpu.D] << 8),
|
||||
["E"] = _cpu.Regs[_cpu.E],
|
||||
["F"] = _cpu.Regs[_cpu.F],
|
||||
["H"] = _cpu.Regs[_cpu.H],
|
||||
["HL"] = _cpu.Regs[_cpu.L] + (_cpu.Regs[_cpu.H] << 8),
|
||||
["I"] = _cpu.Regs[_cpu.I],
|
||||
["IX"] = _cpu.Regs[_cpu.Ixl] + (_cpu.Regs[_cpu.Ixh] << 8),
|
||||
["IY"] = _cpu.Regs[_cpu.Iyl] + (_cpu.Regs[_cpu.Iyh] << 8),
|
||||
["L"] = _cpu.Regs[_cpu.L],
|
||||
["PC"] = _cpu.Regs[_cpu.PCl] + (_cpu.Regs[_cpu.PCh] << 8),
|
||||
["R"] = _cpu.Regs[_cpu.R],
|
||||
["Shadow AF"] = _cpu.Regs[_cpu.F_s] + (_cpu.Regs[_cpu.A_s] << 8),
|
||||
["Shadow BC"] = _cpu.Regs[_cpu.C_s] + (_cpu.Regs[_cpu.B_s] << 8),
|
||||
["Shadow DE"] = _cpu.Regs[_cpu.E_s] + (_cpu.Regs[_cpu.D_s] << 8),
|
||||
["Shadow HL"] = _cpu.Regs[_cpu.L_s] + (_cpu.Regs[_cpu.H_s] << 8),
|
||||
["SP"] = _cpu.Regs[_cpu.Iyl] + (_cpu.Regs[_cpu.Iyh] << 8),
|
||||
["Flag C"] = _cpu.FlagC,
|
||||
["Flag N"] = _cpu.FlagN,
|
||||
["Flag P/V"] = _cpu.FlagP,
|
||||
["Flag 3rd"] = _cpu.Flag3,
|
||||
["Flag H"] = _cpu.FlagH,
|
||||
["Flag 5th"] = _cpu.Flag5,
|
||||
["Flag Z"] = _cpu.FlagZ,
|
||||
["Flag S"] = _cpu.FlagS
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -49,73 +49,85 @@ namespace BizHawk.Emulation.Cores.Calculators
|
|||
{
|
||||
switch (register)
|
||||
{
|
||||
default:
|
||||
throw new InvalidOperationException();
|
||||
case "A":
|
||||
_cpu.RegisterA = (byte)value;
|
||||
break;
|
||||
case "AF":
|
||||
_cpu.RegisterAF = (byte)value;
|
||||
break;
|
||||
case "B":
|
||||
_cpu.RegisterB = (byte)value;
|
||||
break;
|
||||
case "BC":
|
||||
_cpu.RegisterBC = (byte)value;
|
||||
break;
|
||||
case "C":
|
||||
_cpu.RegisterC = (byte)value;
|
||||
break;
|
||||
case "D":
|
||||
_cpu.RegisterD = (byte)value;
|
||||
break;
|
||||
case "DE":
|
||||
_cpu.RegisterDE = (byte)value;
|
||||
break;
|
||||
case "E":
|
||||
_cpu.RegisterE = (byte)value;
|
||||
break;
|
||||
case "F":
|
||||
_cpu.RegisterF = (byte)value;
|
||||
break;
|
||||
case "H":
|
||||
_cpu.RegisterH = (byte)value;
|
||||
break;
|
||||
case "HL":
|
||||
_cpu.RegisterHL = (byte)value;
|
||||
break;
|
||||
case "I":
|
||||
_cpu.RegisterI = (byte)value;
|
||||
break;
|
||||
case "IX":
|
||||
_cpu.RegisterIX = (byte)value;
|
||||
break;
|
||||
case "IY":
|
||||
_cpu.RegisterIY = (byte)value;
|
||||
break;
|
||||
case "L":
|
||||
_cpu.RegisterL = (byte)value;
|
||||
break;
|
||||
case "PC":
|
||||
_cpu.RegisterPC = (ushort)value;
|
||||
break;
|
||||
case "R":
|
||||
_cpu.RegisterR = (byte)value;
|
||||
break;
|
||||
case "Shadow AF":
|
||||
_cpu.RegisterShadowAF = (byte)value;
|
||||
break;
|
||||
case "Shadow BC":
|
||||
_cpu.RegisterShadowBC = (byte)value;
|
||||
break;
|
||||
case "Shadow DE":
|
||||
_cpu.RegisterShadowDE = (byte)value;
|
||||
break;
|
||||
case "Shadow HL":
|
||||
_cpu.RegisterShadowHL = (byte)value;
|
||||
break;
|
||||
case "SP":
|
||||
_cpu.RegisterSP = (byte)value;
|
||||
default:
|
||||
throw new InvalidOperationException();
|
||||
case "A":
|
||||
_cpu.Regs[_cpu.A] = (ushort)value;
|
||||
break;
|
||||
case "AF":
|
||||
_cpu.Regs[_cpu.F] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.A] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
case "B":
|
||||
_cpu.Regs[_cpu.B] = (ushort)value;
|
||||
break;
|
||||
case "BC":
|
||||
_cpu.Regs[_cpu.C] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.B] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
case "C":
|
||||
_cpu.Regs[_cpu.C] = (ushort)value;
|
||||
break;
|
||||
case "D":
|
||||
_cpu.Regs[_cpu.D] = (ushort)value;
|
||||
break;
|
||||
case "DE":
|
||||
_cpu.Regs[_cpu.E] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.D] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
case "E":
|
||||
_cpu.Regs[_cpu.E] = (ushort)value;
|
||||
break;
|
||||
case "F":
|
||||
_cpu.Regs[_cpu.F] = (ushort)value;
|
||||
break;
|
||||
case "H":
|
||||
_cpu.Regs[_cpu.H] = (ushort)value;
|
||||
break;
|
||||
case "HL":
|
||||
_cpu.Regs[_cpu.L] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.H] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
case "I":
|
||||
_cpu.Regs[_cpu.I] = (ushort)value;
|
||||
break;
|
||||
case "IX":
|
||||
_cpu.Regs[_cpu.Ixl] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.Ixh] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
case "IY":
|
||||
_cpu.Regs[_cpu.Iyl] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.Iyh] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
case "L":
|
||||
_cpu.Regs[_cpu.L] = (ushort)value;
|
||||
break;
|
||||
case "PC":
|
||||
_cpu.Regs[_cpu.PCl] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.PCh] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
case "R":
|
||||
_cpu.Regs[_cpu.R] = (ushort)value;
|
||||
break;
|
||||
case "Shadow AF":
|
||||
_cpu.Regs[_cpu.F_s] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.A_s] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
case "Shadow BC":
|
||||
_cpu.Regs[_cpu.C_s] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.B_s] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
case "Shadow DE":
|
||||
_cpu.Regs[_cpu.E_s] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.D_s] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
case "Shadow HL":
|
||||
_cpu.Regs[_cpu.L_s] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.H_s] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
case "SP":
|
||||
_cpu.Regs[_cpu.SPl] = (ushort)(value & 0xFF);
|
||||
_cpu.Regs[_cpu.SPh] = (ushort)(value & 0xFF00);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
|
@ -13,11 +13,13 @@ namespace BizHawk.Emulation.Cores.Calculators
|
|||
_controller = controller;
|
||||
_lagged = true;
|
||||
|
||||
_cpu.Debug = _tracer.Enabled;
|
||||
|
||||
if (_cpu.Debug && _cpu.Logger == null) // TODO, lets not do this on each frame. But lets refactor CoreComm/CoreComm first
|
||||
if (_tracer.Enabled)
|
||||
{
|
||||
_cpu.Logger = s => _tracer.Put(s);
|
||||
_cpu.TraceCallback = s => _tracer.Put(s);
|
||||
}
|
||||
else
|
||||
{
|
||||
_cpu.TraceCallback = null;
|
||||
}
|
||||
|
||||
// I eyeballed this speed
|
||||
|
@ -26,8 +28,12 @@ namespace BizHawk.Emulation.Cores.Calculators
|
|||
_onPressed = controller.IsPressed("ON");
|
||||
|
||||
// and this was derived from other emus
|
||||
_cpu.ExecuteCycles(10000);
|
||||
_cpu.Interrupt = true;
|
||||
for (int j = 0; j < 10000; j++)
|
||||
{
|
||||
_cpu.ExecuteOne();
|
||||
}
|
||||
|
||||
_cpu.FlagI = true;
|
||||
}
|
||||
|
||||
Frame++;
|
||||
|
|
|
@ -7,55 +7,52 @@ namespace BizHawk.Emulation.Cores.Calculators
|
|||
{
|
||||
public partial class TI83 : IStatable
|
||||
{
|
||||
private byte[] _stateBuffer;
|
||||
public bool BinarySaveStatesPreferred
|
||||
{
|
||||
get { return true; }
|
||||
}
|
||||
|
||||
public bool BinarySaveStatesPreferred => false;
|
||||
public void SaveStateText(TextWriter writer)
|
||||
{
|
||||
SyncState(new Serializer(writer));
|
||||
}
|
||||
|
||||
public void LoadStateText(TextReader reader)
|
||||
{
|
||||
SyncState(new Serializer(reader));
|
||||
}
|
||||
|
||||
public void SaveStateBinary(BinaryWriter bw)
|
||||
{
|
||||
SyncState(Serializer.CreateBinaryWriter(bw));
|
||||
SyncState(new Serializer(bw));
|
||||
}
|
||||
|
||||
public void LoadStateBinary(BinaryReader br)
|
||||
{
|
||||
SyncState(Serializer.CreateBinaryReader(br));
|
||||
}
|
||||
|
||||
public void SaveStateText(TextWriter tw)
|
||||
{
|
||||
SyncState(Serializer.CreateTextWriter(tw));
|
||||
}
|
||||
|
||||
public void LoadStateText(TextReader tr)
|
||||
{
|
||||
SyncState(Serializer.CreateTextReader(tr));
|
||||
SyncState(new Serializer(br));
|
||||
}
|
||||
|
||||
public byte[] SaveStateBinary()
|
||||
{
|
||||
if (_stateBuffer == null)
|
||||
{
|
||||
var stream = new MemoryStream();
|
||||
var writer = new BinaryWriter(stream);
|
||||
SaveStateBinary(writer);
|
||||
_stateBuffer = stream.ToArray();
|
||||
writer.Close();
|
||||
return _stateBuffer;
|
||||
}
|
||||
else
|
||||
{
|
||||
var stream = new MemoryStream(_stateBuffer);
|
||||
var writer = new BinaryWriter(stream);
|
||||
SaveStateBinary(writer);
|
||||
writer.Close();
|
||||
return _stateBuffer;
|
||||
}
|
||||
MemoryStream ms = new MemoryStream();
|
||||
BinaryWriter bw = new BinaryWriter(ms);
|
||||
SaveStateBinary(bw);
|
||||
bw.Flush();
|
||||
return ms.ToArray();
|
||||
}
|
||||
|
||||
private void SyncState(Serializer ser)
|
||||
{
|
||||
ser.BeginSection("TI83");
|
||||
byte[] core = null;
|
||||
if (ser.IsWriter)
|
||||
{
|
||||
var ms = new MemoryStream();
|
||||
ms.Close();
|
||||
core = ms.ToArray();
|
||||
}
|
||||
_cpu.SyncState(ser);
|
||||
|
||||
ser.BeginSection("TI83");
|
||||
ser.Sync("RAM", ref _ram, false);
|
||||
ser.Sync("romPageLow3Bits", ref _romPageLow3Bits);
|
||||
ser.Sync("romPageHighBit", ref _romPageHighBit);
|
||||
|
|
|
@ -2,7 +2,7 @@ using System;
|
|||
using System.Globalization;
|
||||
|
||||
using BizHawk.Emulation.Common;
|
||||
using BizHawk.Emulation.Cores.Components.Z80;
|
||||
using BizHawk.Emulation.Common.Components.Z80A;
|
||||
|
||||
// http://www.ticalc.org/pub/text/calcinfo/
|
||||
namespace BizHawk.Emulation.Cores.Calculators
|
||||
|
@ -48,7 +48,7 @@ namespace BizHawk.Emulation.Cores.Calculators
|
|||
_tracer = new TraceBuffer { Header = _cpu.TraceHeader };
|
||||
|
||||
ser.Register<ITraceable>(_tracer);
|
||||
ser.Register<IDisassemblable>(new Disassembler());
|
||||
ser.Register<IDisassemblable>(_cpu);
|
||||
}
|
||||
|
||||
private readonly TraceBuffer _tracer;
|
||||
|
@ -151,7 +151,7 @@ namespace BizHawk.Emulation.Cores.Calculators
|
|||
if (LinkActive)
|
||||
{
|
||||
// Prevent rom calls from disturbing link port activity
|
||||
if (LinkActive && _cpu.RegisterPC < 0x4000)
|
||||
if (LinkActive && _cpu.RegPC < 0x4000)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
@ -428,13 +428,13 @@ namespace BizHawk.Emulation.Cores.Calculators
|
|||
|
||||
private void IRQCallback()
|
||||
{
|
||||
// Console.WriteLine("IRQ with vec {0} and cpu.InterruptMode {1}", cpu.RegisterI, cpu.InterruptMode);
|
||||
_cpu.Interrupt = false;
|
||||
//Console.WriteLine("IRQ with vec {0} and cpu.InterruptMode {1}", _cpu.Regs[_cpu.I], _cpu.InterruptMode);
|
||||
_cpu.FlagI = false;
|
||||
}
|
||||
|
||||
private void NMICallback()
|
||||
{
|
||||
Console.WriteLine("NMI");
|
||||
//Console.WriteLine("NMI");
|
||||
_cpu.NonMaskableInterrupt = false;
|
||||
}
|
||||
|
||||
|
@ -447,7 +447,7 @@ namespace BizHawk.Emulation.Cores.Calculators
|
|||
_ram[i] = 0xFF;
|
||||
}
|
||||
|
||||
_cpu.RegisterPC = _startPC;
|
||||
_cpu.RegPC = _startPC;
|
||||
|
||||
_cpu.IFF1 = false;
|
||||
_cpu.IFF2 = false;
|
||||
|
|
Loading…
Reference in New Issue