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ZXHawk: wire up +2a/+3 memory contention model (MREQ)

This commit is contained in:
Asnivor 2018-06-13 07:55:23 +01:00
parent 9a906cd8af
commit 9166b0b931
1 changed files with 11 additions and 1 deletions
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12
BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/CPUMonitor.cs
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@ -30,7 +30,17 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
/// </summary>
public ushort BUSRQ
{
get { return _cpu.BUSRQ[_cpu.bus_pntr]; }
get
{
switch (machineType)
{
case MachineType.ZXSpectrum128Plus2a:
case MachineType.ZXSpectrum128Plus3:
return _cpu.MEMRQ[_cpu.bus_pntr];
default:
return _cpu.BUSRQ[_cpu.mem_pntr];
}
}
}
#endregion