ZXHawk: Start building on new BUSRQ implementation
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Asnivor
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32ae549c70
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7677b75de3
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@ -23,6 +23,16 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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public int instr_pntr => _cpu.instr_pntr;
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public ushort RegPC => _cpu.RegPC;
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public long TotalExecutedCycles => _cpu.TotalExecutedCycles;
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public ushort BUSRQ
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{
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get
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{
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if (_cpu.bus_pntr < _cpu.BUSRQ.Length - 1)
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return _cpu.BUSRQ[_cpu.bus_pntr];
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return 0;
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}
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}
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/// <summary>
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/// Called when the first byte of an instruction is fetched
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@ -39,106 +49,67 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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/// </summary>
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public void Cycle()
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{
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if (portContending)
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{
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RunPortContention();
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}
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/*
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else
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{
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// check for wait state on cycle that has just happened
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// next cycle should be a read/write operation
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if (cur_instr[instr_pntr] == Z80A.WAIT)
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{
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ushort addr = 0;
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bool abort = false;
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// check for upcoming BUSRQ
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if (BUSRQ == 0)
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return;
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// identify the type of operation and get the targetted address
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switch (cur_instr[instr_pntr + 1])
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{
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// op fetch
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case Z80A.OP_F:
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addr = RegPC;
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break;
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// read/writes
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case Z80A.RD:
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case Z80A.RD_INC:
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case Z80A.WR:
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case Z80A.WR_INC:
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addr = (ushort)(_cpu.Regs[cur_instr[instr_pntr + 3]] | _cpu.Regs[cur_instr[instr_pntr + 4]] << 8);
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break;
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default:
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abort = true;
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break;
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}
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if (!abort)
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{
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// is the address in a potentially contended bank?
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if (_machine.IsContended(addr))
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{
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// will the ULA be contending this address on the next cycle?
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var delay = _machine.ULADevice.GetContentionValue((int)_machine.CurrentFrameCycle + 1);
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_cpu.TotalExecutedCycles += delay;
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}
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}
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}
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}
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*/
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return;
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// check for wait state on next cycle
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// the cycle after that should be a read/write operation or op fetch
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if (instr_pntr >= cur_instr.Length - 1)
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{
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// will overflow
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return;
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}
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if (cur_instr[instr_pntr + 1] == Z80A.WAIT)
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{
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// return;
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ushort addr = 0;
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// identify the type of operation and get the targetted address
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var op = cur_instr[instr_pntr + 2];
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switch (op)
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switch (BUSRQ)
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{
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// op fetch
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case Z80A.OP_F:
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addr = (ushort)(RegPC);
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if (_machine.IsContended(addr))
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{
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var delay = _machine.ULADevice.GetContentionValue((int)_machine.CurrentFrameCycle);
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if (delay > 0)
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{
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_cpu.TotalExecutedCycles += delay;
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_machine.ULADevice.RenderScreen((int)_machine.CurrentFrameCycle);
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}
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}
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// PCl
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case 0:
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addr = (ushort)(_cpu.Regs[_cpu.PCl] | _cpu.Regs[_cpu.PCh] << 8);
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break;
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// read/writes
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case Z80A.RD:
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case Z80A.RD_INC:
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case Z80A.WR:
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case Z80A.WR_INC:
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addr = (ushort)(_cpu.Regs[cur_instr[instr_pntr + 4]] | _cpu.Regs[cur_instr[instr_pntr + 5]] << 8);
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if (_machine.IsContended(addr))
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{
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var delay = _machine.ULADevice.GetContentionValue((int)_machine.CurrentFrameCycle);
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if (delay > 0)
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{
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_cpu.TotalExecutedCycles += delay;
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_machine.ULADevice.RenderScreen((int)_machine.CurrentFrameCycle);
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}
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}
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// Z
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case 13:
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addr = (ushort)(_cpu.Regs[_cpu.Z] | _cpu.Regs[_cpu.W] << 8);
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break;
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case Z80A.FTCH_DB:
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// SPl
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case 2:
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addr = (ushort)(_cpu.Regs[_cpu.SPl] | _cpu.Regs[_cpu.SPh] << 8);
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break;
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// L
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case 11:
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addr = (ushort)(_cpu.Regs[_cpu.L] | _cpu.Regs[_cpu.H] << 8);
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break;
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// I
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case 21:
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addr = (ushort)(_cpu.Regs[_cpu.R] | _cpu.Regs[_cpu.I] << 8);
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break;
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// Ixl
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case 15:
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addr = (ushort)(_cpu.Regs[_cpu.Ixl] | _cpu.Regs[_cpu.Ixh] << 8);
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break;
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// Iyl
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case 17:
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addr = (ushort)(_cpu.Regs[_cpu.Iyl] | _cpu.Regs[_cpu.Iyh] << 8);
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break;
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// A
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case 4:
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addr = (ushort)(_cpu.Regs[_cpu.F] | _cpu.Regs[_cpu.A] << 8);
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break;
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// B
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case 6:
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addr = (ushort)(_cpu.Regs[_cpu.C] | _cpu.Regs[_cpu.B] << 8);
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break;
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// D
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case 8:
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addr = (ushort)(_cpu.Regs[_cpu.E] | _cpu.Regs[_cpu.D] << 8);
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break;
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default:
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break;
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}
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if (_machine.IsContended(addr))
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_cpu.TotalExecutedCycles += _machine.ULADevice.GetContentionValue();
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}
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}
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@ -169,10 +169,9 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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// check for interrupt
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ULADevice.CheckForInterrupt(CurrentFrameCycle);
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// run a single CPU instruction
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// run a single CPU instruction
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CPU.ExecuteOne();
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// check contention for next cycle
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CPUMon.Cycle();
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// cycle the tape device
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@ -212,11 +212,13 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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/// </summary>
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public override void ContendMemory(ushort addr)
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{
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/*
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if (IsContended(addr))
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{
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var delay = ULADevice.GetContentionValue((int)CurrentFrameCycle);
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CPU.TotalExecutedCycles += delay;
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}
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*/
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}
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/// <summary>
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@ -400,11 +400,13 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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/// </summary>
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public override void ContendMemory(ushort addr)
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{
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/*
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if (IsContended(addr))
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{
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var delay = ULADevice.GetContentionValue((int)CurrentFrameCycle);
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CPU.TotalExecutedCycles += delay;
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}
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*/
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}
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/// <summary>
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@ -400,11 +400,13 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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/// </summary>
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public override void ContendMemory(ushort addr)
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{
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/*
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if (IsContended(addr))
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{
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var delay = ULADevice.GetContentionValue((int)CurrentFrameCycle);
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CPU.TotalExecutedCycles += delay;
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}
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*/
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}
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/// <summary>
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@ -98,8 +98,10 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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/// <returns></returns>
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public override byte ReadMemory(ushort addr)
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{
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/*
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if (IsContended(addr))
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CPU.TotalExecutedCycles += ULADevice.GetContentionValue((int)CurrentFrameCycle);
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*/
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var data = ReadBus(addr);
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return data;
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@ -113,12 +115,14 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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/// <param name="value"></param>
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public override void WriteMemory(ushort addr, byte value)
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{
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/*
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// apply contention if necessary
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if (IsContended(addr))
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{
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ULADevice.RenderScreen((int)CurrentFrameCycle);
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CPU.TotalExecutedCycles += ULADevice.GetContentionValue((int)CurrentFrameCycle);
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}
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*/
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WriteBus(addr, value);
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}
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@ -122,6 +122,8 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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/// </summary>
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public override void ContendMemory(ushort addr)
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{
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return;
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/*
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if (IsContended(addr))
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{
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var off = 1;
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@ -138,6 +140,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
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}
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CPU.TotalExecutedCycles += delay;
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}
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*/
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}
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/// <summary>
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