diff --git a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/CPUMonitor.cs b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/CPUMonitor.cs
index d098cc94a4..e345c44c4f 100644
--- a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/CPUMonitor.cs
+++ b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/CPUMonitor.cs
@@ -23,6 +23,16 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
public int instr_pntr => _cpu.instr_pntr;
public ushort RegPC => _cpu.RegPC;
public long TotalExecutedCycles => _cpu.TotalExecutedCycles;
+ public ushort BUSRQ
+ {
+ get
+ {
+ if (_cpu.bus_pntr < _cpu.BUSRQ.Length - 1)
+ return _cpu.BUSRQ[_cpu.bus_pntr];
+
+ return 0;
+ }
+ }
///
/// Called when the first byte of an instruction is fetched
@@ -39,106 +49,67 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
///
public void Cycle()
{
-
if (portContending)
{
RunPortContention();
}
- /*
else
{
- // check for wait state on cycle that has just happened
- // next cycle should be a read/write operation
- if (cur_instr[instr_pntr] == Z80A.WAIT)
- {
- ushort addr = 0;
- bool abort = false;
+ // check for upcoming BUSRQ
+ if (BUSRQ == 0)
+ return;
- // identify the type of operation and get the targetted address
- switch (cur_instr[instr_pntr + 1])
- {
- // op fetch
- case Z80A.OP_F:
- addr = RegPC;
- break;
- // read/writes
- case Z80A.RD:
- case Z80A.RD_INC:
- case Z80A.WR:
- case Z80A.WR_INC:
- addr = (ushort)(_cpu.Regs[cur_instr[instr_pntr + 3]] | _cpu.Regs[cur_instr[instr_pntr + 4]] << 8);
- break;
- default:
- abort = true;
- break;
- }
-
- if (!abort)
- {
- // is the address in a potentially contended bank?
- if (_machine.IsContended(addr))
- {
- // will the ULA be contending this address on the next cycle?
- var delay = _machine.ULADevice.GetContentionValue((int)_machine.CurrentFrameCycle + 1);
- _cpu.TotalExecutedCycles += delay;
- }
- }
- }
-
- }
- */
- return;
- // check for wait state on next cycle
- // the cycle after that should be a read/write operation or op fetch
- if (instr_pntr >= cur_instr.Length - 1)
- {
- // will overflow
- return;
- }
-
- if (cur_instr[instr_pntr + 1] == Z80A.WAIT)
- {
- // return;
ushort addr = 0;
- // identify the type of operation and get the targetted address
- var op = cur_instr[instr_pntr + 2];
- switch (op)
+ switch (BUSRQ)
{
- // op fetch
- case Z80A.OP_F:
- addr = (ushort)(RegPC);
- if (_machine.IsContended(addr))
- {
- var delay = _machine.ULADevice.GetContentionValue((int)_machine.CurrentFrameCycle);
- if (delay > 0)
- {
- _cpu.TotalExecutedCycles += delay;
- _machine.ULADevice.RenderScreen((int)_machine.CurrentFrameCycle);
- }
- }
+ // PCl
+ case 0:
+ addr = (ushort)(_cpu.Regs[_cpu.PCl] | _cpu.Regs[_cpu.PCh] << 8);
break;
- // read/writes
- case Z80A.RD:
- case Z80A.RD_INC:
- case Z80A.WR:
- case Z80A.WR_INC:
- addr = (ushort)(_cpu.Regs[cur_instr[instr_pntr + 4]] | _cpu.Regs[cur_instr[instr_pntr + 5]] << 8);
- if (_machine.IsContended(addr))
- {
- var delay = _machine.ULADevice.GetContentionValue((int)_machine.CurrentFrameCycle);
- if (delay > 0)
- {
- _cpu.TotalExecutedCycles += delay;
- _machine.ULADevice.RenderScreen((int)_machine.CurrentFrameCycle);
- }
- }
+ // Z
+ case 13:
+ addr = (ushort)(_cpu.Regs[_cpu.Z] | _cpu.Regs[_cpu.W] << 8);
break;
- case Z80A.FTCH_DB:
+ // SPl
+ case 2:
+ addr = (ushort)(_cpu.Regs[_cpu.SPl] | _cpu.Regs[_cpu.SPh] << 8);
break;
+ // L
+ case 11:
+ addr = (ushort)(_cpu.Regs[_cpu.L] | _cpu.Regs[_cpu.H] << 8);
+ break;
+ // I
+ case 21:
+ addr = (ushort)(_cpu.Regs[_cpu.R] | _cpu.Regs[_cpu.I] << 8);
+ break;
+ // Ixl
+ case 15:
+ addr = (ushort)(_cpu.Regs[_cpu.Ixl] | _cpu.Regs[_cpu.Ixh] << 8);
+ break;
+ // Iyl
+ case 17:
+ addr = (ushort)(_cpu.Regs[_cpu.Iyl] | _cpu.Regs[_cpu.Iyh] << 8);
+ break;
+ // A
+ case 4:
+ addr = (ushort)(_cpu.Regs[_cpu.F] | _cpu.Regs[_cpu.A] << 8);
+ break;
+ // B
+ case 6:
+ addr = (ushort)(_cpu.Regs[_cpu.C] | _cpu.Regs[_cpu.B] << 8);
+ break;
+ // D
+ case 8:
+ addr = (ushort)(_cpu.Regs[_cpu.E] | _cpu.Regs[_cpu.D] << 8);
+ break;
+
default:
break;
}
+
+ if (_machine.IsContended(addr))
+ _cpu.TotalExecutedCycles += _machine.ULADevice.GetContentionValue();
}
}
diff --git a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/SpectrumBase.cs b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/SpectrumBase.cs
index d6bea89b67..a87c006336 100644
--- a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/SpectrumBase.cs
+++ b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/SpectrumBase.cs
@@ -169,10 +169,9 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
// check for interrupt
ULADevice.CheckForInterrupt(CurrentFrameCycle);
- // run a single CPU instruction
-
+ // run a single CPU instruction
CPU.ExecuteOne();
-
+ // check contention for next cycle
CPUMon.Cycle();
// cycle the tape device
diff --git a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128K/ZX128.Memory.cs b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128K/ZX128.Memory.cs
index 3ab198737e..df1d5587da 100644
--- a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128K/ZX128.Memory.cs
+++ b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128K/ZX128.Memory.cs
@@ -212,11 +212,13 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
///
public override void ContendMemory(ushort addr)
{
+ /*
if (IsContended(addr))
{
var delay = ULADevice.GetContentionValue((int)CurrentFrameCycle);
CPU.TotalExecutedCycles += delay;
}
+ */
}
///
diff --git a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus2a/ZX128Plus2a.Memory.cs b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus2a/ZX128Plus2a.Memory.cs
index 26ae8ef939..d4c46af37f 100644
--- a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus2a/ZX128Plus2a.Memory.cs
+++ b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus2a/ZX128Plus2a.Memory.cs
@@ -400,11 +400,13 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
///
public override void ContendMemory(ushort addr)
{
+ /*
if (IsContended(addr))
{
var delay = ULADevice.GetContentionValue((int)CurrentFrameCycle);
CPU.TotalExecutedCycles += delay;
}
+ */
}
///
diff --git a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus3/ZX128Plus3.Memory.cs b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus3/ZX128Plus3.Memory.cs
index 68a3841244..e288b67c86 100644
--- a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus3/ZX128Plus3.Memory.cs
+++ b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum128KPlus3/ZX128Plus3.Memory.cs
@@ -400,11 +400,13 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
///
public override void ContendMemory(ushort addr)
{
+ /*
if (IsContended(addr))
{
var delay = ULADevice.GetContentionValue((int)CurrentFrameCycle);
CPU.TotalExecutedCycles += delay;
}
+ */
}
///
diff --git a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum16K/ZX16.cs b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum16K/ZX16.cs
index 1d9c7edc0b..c17d90fe26 100644
--- a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum16K/ZX16.cs
+++ b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum16K/ZX16.cs
@@ -98,8 +98,10 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
///
public override byte ReadMemory(ushort addr)
{
+ /*
if (IsContended(addr))
CPU.TotalExecutedCycles += ULADevice.GetContentionValue((int)CurrentFrameCycle);
+ */
var data = ReadBus(addr);
return data;
@@ -113,12 +115,14 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
///
public override void WriteMemory(ushort addr, byte value)
{
+ /*
// apply contention if necessary
if (IsContended(addr))
{
ULADevice.RenderScreen((int)CurrentFrameCycle);
CPU.TotalExecutedCycles += ULADevice.GetContentionValue((int)CurrentFrameCycle);
}
+ */
WriteBus(addr, value);
}
diff --git a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum48K/ZX48.Memory.cs b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum48K/ZX48.Memory.cs
index 7dd6f3cd21..2006f35c02 100644
--- a/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum48K/ZX48.Memory.cs
+++ b/BizHawk.Emulation.Cores/Computers/SinclairSpectrum/Machine/ZXSpectrum48K/ZX48.Memory.cs
@@ -122,6 +122,8 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
///
public override void ContendMemory(ushort addr)
{
+ return;
+ /*
if (IsContended(addr))
{
var off = 1;
@@ -138,6 +140,7 @@ namespace BizHawk.Emulation.Cores.Computers.SinclairSpectrum
}
CPU.TotalExecutedCycles += delay;
}
+ */
}
///