nes-pass 10-even_odd_timing and 05-nmi_timing
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44daaa0841
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@ -147,8 +147,6 @@ namespace BizHawk.Emulation.Consoles.Nintendo
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for (int i = 0; i < x; i++)
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{
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ppur.status.cycle++;
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if (ppur.status.cycle == ppur.status.end_cycle)
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ppur.status.cycle = 0;
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//might not actually run a cpu cycle if there are none to be run right now
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nes.RunCpuOne();
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@ -66,7 +66,7 @@ namespace BizHawk.Emulation.Consoles.Nintendo
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{
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public int sl;
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public bool rendering { get { return sl >= 0 && sl < 241; } }
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public int cycle, end_cycle;
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public int cycle;
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}
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//uses the internal counters concept at http://nesdev.icequake.net/PPU%20addressing.txt
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@ -94,7 +94,8 @@ namespace BizHawk.Emulation.Consoles.Nintendo
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ser.Sync("_ht", ref _ht);
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ser.Sync("fh", ref fh);
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ser.Sync("status.cycle", ref status.cycle);
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ser.Sync("status.end_cycle", ref status.end_cycle);
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int junk = 0;
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ser.Sync("status.end_cycle", ref junk);
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ser.Sync("status.sl", ref status.sl);
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}
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@ -151,7 +152,6 @@ namespace BizHawk.Emulation.Consoles.Nintendo
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fh = 0;
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_fv = _v = _h = _vt = _ht = 0;
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status.cycle = 0;
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status.end_cycle = 341;
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status.sl = 241;
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}
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@ -97,11 +97,12 @@ namespace BizHawk.Emulation.Consoles.Nintendo
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//NOTE: Not having this here breaks a Super Donkey Kong game.
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reg_2003 = 0;
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//fceu/fceux had 12 here, but 15 was required to pass blargg's 05-nmi_timing.nes
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const int delay = 15;
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//this was repeatedly finetuned from the fceux days thrugh the old cpu core and into the new one to pass 05-nmi_timing.nes
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//note that there is still some leniency. for instance, 4,2 will pass in addition to 3,3
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const int delay = 6;
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runppu(3);
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bool nmi_destiny = reg_2000.vblank_nmi_gen && Reg2002_vblank_active;
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runppu(delay - 3);
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runppu(3);
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if (nmi_destiny) TriggerNMI();
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if (PAL)
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runppu(70 * (kLineTime) - delay);
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@ -116,6 +117,8 @@ namespace BizHawk.Emulation.Consoles.Nintendo
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int oamslot=0;
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int oamcount=0;
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idleSynch ^= true;
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//render 241 scanlines (including 1 dummy at beginning)
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for (int sl = 0; sl < 241; sl++)
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{
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@ -422,35 +425,24 @@ namespace BizHawk.Emulation.Consoles.Nintendo
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ppuphase = PPUPHASE.BG;
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//I'm unclear of the reason why this particular access to memory is made.
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//The nametable address that is accessed 2 times in a row here, is also the
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//same nametable address that points to the 3rd tile to be rendered on the
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//screen (or basically, the first nametable address that will be accessed when
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//the PPU is fetching background data on the next scanline).
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//(not implemented yet)
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if (sl == 0)
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{
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if (idleSynch && reg_2001.show_bg && !PAL)
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ppur.status.end_cycle = 340;
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else
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ppur.status.end_cycle = 341;
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idleSynch ^= true;
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}
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else
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ppur.status.end_cycle = 341;
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//fetch BG: two tiles for next line
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for (int xt = 0; xt < 2; xt++)
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Read_bgdata(ref bgdata[xt]);
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runppu(kFetchTime * 2);
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//this sequence is tuned to pass 10-even_odd_timing.nes
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runppu(kFetchTime);
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bool evenOddDestiny = reg_2001.show_bg;
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runppu(kFetchTime);
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//After memory access 170, the PPU simply rests for 4 cycles (or the
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//equivelant of half a memory access cycle) before repeating the whole
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//pixel/scanline rendering process. If the scanline being rendered is the very
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//first one on every second frame, then this delay simply doesn't exist.
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if (ppur.status.end_cycle == 341)
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if (sl == 0 && idleSynch && evenOddDestiny && !PAL)
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{ }
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else
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runppu(1);
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ppur.status.cycle = 0;
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} //scanline loop
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