2013-08-09 05:34:38 +00:00
|
|
|
|
using BizHawk.Emulation.Computers.Commodore64.MOS;
|
|
|
|
|
|
|
|
|
|
using System;
|
|
|
|
|
using System.Collections.Generic;
|
|
|
|
|
using System.Linq;
|
|
|
|
|
using System.Text;
|
|
|
|
|
|
|
|
|
|
namespace BizHawk.Emulation.Computers.Commodore64
|
|
|
|
|
{
|
|
|
|
|
public partial class Motherboard
|
|
|
|
|
{
|
2013-08-14 05:05:17 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
bool CassPort_ReadDataOutput()
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
2013-08-13 12:23:32 +00:00
|
|
|
|
return (cpu.PortData & 0x08) != 0;
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
bool CassPort_ReadMotor()
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
2013-08-13 12:23:32 +00:00
|
|
|
|
return (cpu.PortData & 0x20) != 0;
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
bool Cia0_ReadCnt()
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
2013-08-14 05:05:17 +00:00
|
|
|
|
return (userPort.ReadCounter1Buffer() && cia0.ReadCNTBuffer());
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
byte Cia0_ReadPortA()
|
|
|
|
|
{
|
2013-08-13 12:23:32 +00:00
|
|
|
|
WriteInputPort();
|
|
|
|
|
return cia0InputLatchA;
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
byte Cia0_ReadPortB()
|
|
|
|
|
{
|
2013-08-13 12:23:32 +00:00
|
|
|
|
WriteInputPort();
|
|
|
|
|
return cia0InputLatchB;
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
bool Cia0_ReadSP()
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
2013-08-14 05:05:17 +00:00
|
|
|
|
return (userPort.ReadSerial1Buffer() && cia0.ReadSPBuffer());
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
bool Cia1_ReadCnt()
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
2013-08-14 05:05:17 +00:00
|
|
|
|
return (userPort.ReadCounter2Buffer() && cia1.ReadCNTBuffer());
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Cia1_ReadPortA()
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
2013-08-14 05:05:17 +00:00
|
|
|
|
// the low bits are actually the VIC memory address.
|
|
|
|
|
byte result = 0xFF;
|
|
|
|
|
if (serPort.WriteDataIn())
|
|
|
|
|
result &= 0x7F;
|
|
|
|
|
if (serPort.WriteClockIn())
|
|
|
|
|
result &= 0xBF;
|
|
|
|
|
return result;
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
bool Cia1_ReadSP()
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
2013-08-14 05:05:17 +00:00
|
|
|
|
return (userPort.ReadSerial2Buffer() && cia1.ReadSPBuffer());
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-13 12:23:32 +00:00
|
|
|
|
byte Cpu_ReadPort()
|
|
|
|
|
{
|
2013-08-13 19:52:03 +00:00
|
|
|
|
byte data = 0x1F;
|
2013-08-14 05:05:17 +00:00
|
|
|
|
if (!cassPort.ReadSenseBuffer())
|
2013-08-13 19:52:03 +00:00
|
|
|
|
data &= 0xEF;
|
|
|
|
|
return data;
|
2013-08-13 12:23:32 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
bool Glue_ReadIRQ()
|
|
|
|
|
{
|
|
|
|
|
return cia0.ReadIRQBuffer() & vic.ReadIRQBuffer() & cartPort.ReadIRQBuffer();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
byte Pla_ReadBasicRom(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = basicRom.Read(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadCartridgeHi(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = cartPort.ReadHiRom(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadCartridgeLo(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = cartPort.ReadLoRom(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool Pla_ReadCharen()
|
|
|
|
|
{
|
2013-08-13 12:23:32 +00:00
|
|
|
|
return (cpu.PortData & 0x04) != 0;
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadCharRom(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = charRom.Read(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadCia0(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = cia0.Read(addr);
|
|
|
|
|
if (!inputRead && (addr == 0xDC00 || addr == 0xDC01))
|
|
|
|
|
inputRead = true;
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadCia1(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = cia1.Read(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadColorRam(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus &= 0xF0;
|
|
|
|
|
bus |= colorRam.Read(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadExpansionHi(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = cartPort.ReadHiExp(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadExpansionLo(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = cartPort.ReadLoExp(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool Pla_ReadHiRam()
|
|
|
|
|
{
|
2013-08-13 12:23:32 +00:00
|
|
|
|
return (cpu.PortData & 0x02) != 0;
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadKernalRom(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = kernalRom.Read(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool Pla_ReadLoRam()
|
|
|
|
|
{
|
2013-08-13 12:23:32 +00:00
|
|
|
|
return (cpu.PortData & 0x01) != 0;
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadMemory(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = ram.Read(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadSid(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = sid.Read(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Pla_ReadVic(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = vic.Read(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
void Pla_WriteCartridgeHi(int addr, byte val)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = val;
|
|
|
|
|
cartPort.WriteHiRom(addr, val);
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
void Pla_WriteCartridgeLo(int addr, byte val)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = val;
|
|
|
|
|
cartPort.WriteLoRom(addr, val);
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
void Pla_WriteCia0(int addr, byte val)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = val;
|
|
|
|
|
cia0.Write(addr, val);
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
void Pla_WriteCia1(int addr, byte val)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = val;
|
|
|
|
|
cia1.Write(addr, val);
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
void Pla_WriteColorRam(int addr, byte val)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = val;
|
|
|
|
|
colorRam.Write(addr, val);
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
void Pla_WriteExpansionHi(int addr, byte val)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = val;
|
|
|
|
|
cartPort.WriteHiExp(addr, val);
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
void Pla_WriteExpansionLo(int addr, byte val)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = val;
|
|
|
|
|
cartPort.WriteLoExp(addr, val);
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
void Pla_WriteMemory(int addr, byte val)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = val;
|
|
|
|
|
ram.Write(addr, val);
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
void Pla_WriteSid(int addr, byte val)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = val;
|
|
|
|
|
sid.Write(addr, val);
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
void Pla_WriteVic(int addr, byte val)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus = val;
|
|
|
|
|
vic.Write(addr, val);
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
bool SerPort_ReadAtnOut()
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
2013-08-13 12:23:32 +00:00
|
|
|
|
return (cia1.PortBData & 0x08) == 0;
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
bool SerPort_ReadClockOut()
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
2013-08-13 12:23:32 +00:00
|
|
|
|
return (cia1.PortAData & 0x10) == 0;
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
bool SerPort_ReadDataOut()
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
2013-08-13 12:23:32 +00:00
|
|
|
|
return (cia1.PortAData & 0x20) == 0;
|
2013-08-09 05:34:38 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
byte Sid_ReadPotX()
|
|
|
|
|
{
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
byte Sid_ReadPotY()
|
|
|
|
|
{
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Vic_ReadMemory(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
2013-08-13 12:23:32 +00:00
|
|
|
|
switch (cia1.PortAData & 0x3)
|
|
|
|
|
{
|
|
|
|
|
case 0:
|
|
|
|
|
addr |= 0xC000;
|
|
|
|
|
break;
|
|
|
|
|
case 1:
|
|
|
|
|
addr |= 0x8000;
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
addr |= 0x4000;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2013-08-09 05:34:38 +00:00
|
|
|
|
address = addr;
|
|
|
|
|
if ((addr & 0x7000) == 0x1000)
|
|
|
|
|
bus = charRom.Read(addr);
|
|
|
|
|
else
|
|
|
|
|
bus = ram.Read(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
|
2013-08-14 05:05:17 +00:00
|
|
|
|
byte Vic_ReadColorRam(int addr)
|
2013-08-09 05:34:38 +00:00
|
|
|
|
{
|
|
|
|
|
address = addr;
|
|
|
|
|
bus &= 0xF0;
|
|
|
|
|
bus |= colorRam.Read(addr);
|
|
|
|
|
return bus;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|