2012-12-05 21:07:51 +00:00
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using BizHawk.Emulation.Computers.Commodore64.MOS;
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namespace BizHawk.Emulation.Computers.Commodore64
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{
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public partial class Motherboard
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{
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// chips
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public Chip23XX basicRom;
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public Chip23XX charRom;
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public MOS6526 cia0;
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public MOS6526 cia1;
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public Chip2114 colorRam;
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public MOS6510 cpu;
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public Chip23XX kernalRom;
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public MOSPLA pla;
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public Chip4864 ram;
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public Sid sid;
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public Vic vic;
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// ports
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public CartridgePort cartPort;
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public CassettePort cassPort;
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2013-08-13 12:23:32 +00:00
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public IController controller;
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2012-12-05 21:07:51 +00:00
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public SerialPort serPort;
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public UserPort userPort;
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// state
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public ushort address;
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public byte bus;
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public bool inputRead;
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public Motherboard(Region initRegion)
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{
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// note: roms need to be added on their own externally
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cartPort = new CartridgePort();
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cassPort = new CassettePort();
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cia0 = new MOS6526(initRegion);
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2013-08-13 12:23:32 +00:00
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cia1 = new MOS6526(initRegion);
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2012-12-05 21:07:51 +00:00
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colorRam = new Chip2114();
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cpu = new MOS6510();
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pla = new MOSPLA();
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ram = new Chip4864();
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serPort = new SerialPort();
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sid = new MOS6581(44100, initRegion);
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switch (initRegion)
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{
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case Region.NTSC: vic = new MOS6567(); break;
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case Region.PAL: vic = new MOS6569(); break;
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}
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userPort = new UserPort();
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}
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// -----------------------------------------
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2012-12-07 05:24:00 +00:00
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public void Execute()
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2012-12-05 21:07:51 +00:00
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{
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2012-12-07 05:24:00 +00:00
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cia0.ExecutePhase1();
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cia1.ExecutePhase1();
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sid.ExecutePhase1();
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vic.ExecutePhase1();
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cpu.ExecutePhase1();
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2012-12-05 21:07:51 +00:00
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2012-12-07 05:24:00 +00:00
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cia0.ExecutePhase2();
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cia1.ExecutePhase2();
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sid.ExecutePhase2();
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vic.ExecutePhase2();
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cpu.ExecutePhase2();
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2012-12-05 21:07:51 +00:00
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}
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// -----------------------------------------
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public void HardReset()
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{
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address = 0xFFFF;
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bus = 0xFF;
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inputRead = false;
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cpu.HardReset();
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cia0.HardReset();
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cia1.HardReset();
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colorRam.HardReset();
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ram.HardReset();
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serPort.HardReset();
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sid.HardReset();
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vic.HardReset();
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userPort.HardReset();
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// because of how mapping works, the cpu needs to be hard reset twice
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cpu.HardReset();
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}
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public void Init()
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{
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2013-08-13 12:23:32 +00:00
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cassPort.ReadDataOutput = CassPort_DeviceReadLevel;
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cassPort.ReadMotor = CassPort_DeviceReadMotor;
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cia0.ReadFlag = Cia0_ReadFlag;
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2013-08-09 05:34:38 +00:00
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cia0.ReadPortA = Cia0_ReadPortA;
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cia0.ReadPortB = Cia0_ReadPortB;
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2013-08-13 12:23:32 +00:00
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cia1.ReadFlag = Cia1_ReadFlag;
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cia1.ReadPortA = Cia1_ReadPortA;
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2013-08-09 05:34:38 +00:00
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cia1.ReadPortB = Cia1_ReadPortB;
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2012-12-05 21:07:51 +00:00
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cpu.PeekMemory = pla.Peek;
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cpu.PokeMemory = pla.Poke;
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2013-08-13 20:16:41 +00:00
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cpu.ReadAEC = vic.ReadAEC;
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2013-08-09 05:34:38 +00:00
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cpu.ReadIRQ = Cpu_ReadIRQ;
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2013-08-13 20:16:41 +00:00
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cpu.ReadNMI = cia1.ReadIRQ;
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2013-08-13 12:23:32 +00:00
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cpu.ReadPort = Cpu_ReadPort;
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2013-08-13 20:16:41 +00:00
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cpu.ReadRDY = vic.ReadBA;
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2012-12-05 21:07:51 +00:00
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cpu.ReadMemory = pla.Read;
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cpu.WriteMemory = pla.Write;
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pla.PeekBasicRom = basicRom.Peek;
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pla.PeekCartridgeHi = cartPort.PeekHiRom;
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pla.PeekCartridgeLo = cartPort.PeekLoRom;
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pla.PeekCharRom = charRom.Peek;
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pla.PeekCia0 = cia0.Peek;
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pla.PeekCia1 = cia1.Peek;
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pla.PeekColorRam = colorRam.Peek;
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pla.PeekExpansionHi = cartPort.PeekHiExp;
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pla.PeekExpansionLo = cartPort.PeekLoExp;
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pla.PeekKernalRom = kernalRom.Peek;
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pla.PeekMemory = ram.Peek;
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pla.PeekSid = sid.Peek;
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pla.PeekVic = vic.Peek;
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pla.PokeCartridgeHi = cartPort.PokeHiRom;
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pla.PokeCartridgeLo = cartPort.PokeLoRom;
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pla.PokeCia0 = cia0.Poke;
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pla.PokeCia1 = cia1.Poke;
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pla.PokeColorRam = colorRam.Poke;
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pla.PokeExpansionHi = cartPort.PokeHiExp;
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pla.PokeExpansionLo = cartPort.PokeLoExp;
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pla.PokeMemory = ram.Poke;
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pla.PokeSid = sid.Poke;
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pla.PokeVic = vic.Poke;
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2013-08-13 20:16:41 +00:00
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pla.ReadAEC = vic.ReadAEC;
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pla.ReadBA = vic.ReadBA;
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2013-08-09 05:34:38 +00:00
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pla.ReadBasicRom = Pla_ReadBasicRom;
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pla.ReadCartridgeHi = Pla_ReadCartridgeHi;
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pla.ReadCartridgeLo = Pla_ReadCartridgeLo;
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pla.ReadCharen = Pla_ReadCharen;
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pla.ReadCharRom = Pla_ReadCharRom;
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pla.ReadCia0 = Pla_ReadCia0;
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pla.ReadCia1 = Pla_ReadCia1;
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pla.ReadColorRam = Pla_ReadColorRam;
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pla.ReadExpansionHi = Pla_ReadExpansionHi;
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pla.ReadExpansionLo = Pla_ReadExpansionLo;
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2013-08-13 20:16:41 +00:00
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pla.ReadExRom = cartPort.ReadExRom;
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pla.ReadGame = cartPort.ReadGame;
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2013-08-09 05:34:38 +00:00
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pla.ReadHiRam = Pla_ReadHiRam;
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pla.ReadKernalRom = Pla_ReadKernalRom;
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pla.ReadLoRam = Pla_ReadLoRam;
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pla.ReadMemory = Pla_ReadMemory;
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pla.ReadSid = Pla_ReadSid;
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pla.ReadVic = Pla_ReadVic;
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pla.WriteCartridgeHi = Pla_WriteCartridgeHi;
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pla.WriteCartridgeLo = Pla_WriteCartridgeLo;
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pla.WriteCia0 = Pla_WriteCia0;
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pla.WriteCia1 = Pla_WriteCia1;
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pla.WriteColorRam = Pla_WriteColorRam;
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pla.WriteExpansionHi = Pla_WriteExpansionHi;
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pla.WriteExpansionLo = Pla_WriteExpansionLo;
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pla.WriteMemory = Pla_WriteMemory;
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pla.WriteSid = Pla_WriteSid;
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pla.WriteVic = Pla_WriteVic;
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2012-12-05 21:07:51 +00:00
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2012-12-07 05:24:00 +00:00
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// note: c64 serport lines are inverted
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2013-08-09 05:34:38 +00:00
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serPort.DeviceReadAtn = SerPort_DeviceReadAtn;
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serPort.DeviceReadClock = SerPort_DeviceReadClock;
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serPort.DeviceReadData = SerPort_DeviceReadData;
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serPort.DeviceReadReset = SerPort_DeviceReadReset;
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serPort.DeviceWriteAtn = SerPort_DeviceWriteAtn;
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serPort.DeviceWriteClock = SerPort_DeviceWriteClock;
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serPort.DeviceWriteData = SerPort_DeviceWriteData;
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serPort.DeviceWriteSrq = SerPort_DeviceWriteSrq;
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sid.ReadPotX = Sid_ReadPotX;
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sid.ReadPotY = Sid_ReadPotY;
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vic.ReadMemory = Vic_ReadMemory;
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vic.ReadColorRam = Vic_ReadColorRam;
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2012-12-05 21:07:51 +00:00
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}
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public void SyncState(Serializer ser)
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{
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}
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}
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}
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