forked from ShuriZma/suyu
shader: Properly blacklist and scale image loads
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parent
c7a1cbad44
commit
fc9bb3c3fe
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@ -84,10 +84,8 @@ void PatchImageQueryDimensions(IR::Block& block, IR::Inst& inst) {
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}
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}
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void PatchImageFetch(IR::Block& block, IR::Inst& inst) {
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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void ScaleIntegerCoord(IR::IREmitter& ir, IR::Inst& inst, const IR::U1& is_scaled) {
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const auto info{inst.Flags<IR::TextureInstInfo>()};
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const IR::U1 is_scaled{ir.IsTextureScaled(ir.Imm32(info.descriptor_index))};
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const IR::Value coord{inst.Arg(1)};
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switch (info.type) {
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case TextureType::Color1D:
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@ -121,6 +119,21 @@ void PatchImageFetch(IR::Block& block, IR::Inst& inst) {
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}
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}
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void PatchImageFetch(IR::Block& block, IR::Inst& inst) {
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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const auto info{inst.Flags<IR::TextureInstInfo>()};
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const IR::U1 is_scaled{ir.IsTextureScaled(ir.Imm32(info.descriptor_index))};
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ScaleIntegerCoord(ir, inst, is_scaled);
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}
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void PatchImageRead(IR::Block& block, IR::Inst& inst) {
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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const auto info{inst.Flags<IR::TextureInstInfo>()};
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// TODO: Scale conditionally
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const IR::U1 is_scaled{IR::Value{true}};
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ScaleIntegerCoord(ir, inst, is_scaled);
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}
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void Visit(const IR::Program& program, IR::Block& block, IR::Inst& inst) {
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const bool is_fragment_shader{program.stage == Stage::Fragment};
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switch (inst.GetOpcode()) {
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@ -144,6 +157,9 @@ void Visit(const IR::Program& program, IR::Block& block, IR::Inst& inst) {
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case IR::Opcode::ImageFetch:
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PatchImageFetch(block, inst);
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break;
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case IR::Opcode::ImageRead:
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PatchImageRead(block, inst);
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break;
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default:
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break;
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}
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@ -139,7 +139,7 @@ void ComputePipeline::Configure() {
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}
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}
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for (const auto& desc : info.image_descriptors) {
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add_image(desc, true);
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add_image(desc, desc.is_written);
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}
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texture_cache.FillComputeImageViews(std::span(views.data(), views.size()));
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@ -362,7 +362,7 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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}
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if constexpr (Spec::has_images) {
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for (const auto& desc : info.image_descriptors) {
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add_image(desc, true);
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add_image(desc, desc.is_written);
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}
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}
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}};
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@ -159,7 +159,7 @@ void ComputePipeline::Configure(Tegra::Engines::KeplerCompute& kepler_compute,
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}
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}
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for (const auto& desc : info.image_descriptors) {
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add_image(desc, true);
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add_image(desc, desc.is_written);
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}
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texture_cache.FillComputeImageViews(std::span(views.data(), views.size()));
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@ -322,20 +322,24 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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}
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return TexturePair(gpu_memory.Read<u32>(addr), via_header_index);
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}};
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const auto add_image{[&](const auto& desc) {
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const auto add_image{[&](const auto& desc, bool blacklist) LAMBDA_FORCEINLINE {
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for (u32 index = 0; index < desc.count; ++index) {
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const auto handle{read_handle(desc, index)};
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views[view_index++] = {handle.first};
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views[view_index++] = {
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.index = handle.first,
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.blacklist = blacklist,
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.id = {},
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};
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}
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}};
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if constexpr (Spec::has_texture_buffers) {
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for (const auto& desc : info.texture_buffer_descriptors) {
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add_image(desc);
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add_image(desc, false);
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}
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}
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if constexpr (Spec::has_image_buffers) {
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for (const auto& desc : info.image_buffer_descriptors) {
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add_image(desc);
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add_image(desc, false);
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}
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}
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for (const auto& desc : info.texture_descriptors) {
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@ -349,7 +353,7 @@ void GraphicsPipeline::ConfigureImpl(bool is_indexed) {
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}
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if constexpr (Spec::has_images) {
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for (const auto& desc : info.image_descriptors) {
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add_image(desc);
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add_image(desc, desc.is_written);
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}
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}
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}};
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