forked from ShuriZma/suyu
Merge pull request #3344 from ReinUsesLisp/vk-botw
vk_shader_decompiler: Disable default values on unwritten render targets
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dfd998216c
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@ -325,9 +325,6 @@ VKPipelineCache::DecompileShaders(const GraphicsPipelineCacheKey& key) {
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specialization.tessellation.primitive = fixed_state.tessellation.primitive;
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specialization.tessellation.primitive = fixed_state.tessellation.primitive;
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specialization.tessellation.spacing = fixed_state.tessellation.spacing;
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specialization.tessellation.spacing = fixed_state.tessellation.spacing;
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specialization.tessellation.clockwise = fixed_state.tessellation.clockwise;
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specialization.tessellation.clockwise = fixed_state.tessellation.clockwise;
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for (const auto& rt : key.renderpass_params.color_attachments) {
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specialization.enabled_rendertargets.set(rt.index);
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}
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SPIRVProgram program;
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SPIRVProgram program;
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std::vector<vk::DescriptorSetLayoutBinding> bindings;
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std::vector<vk::DescriptorSetLayoutBinding> bindings;
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@ -542,11 +542,10 @@ private:
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return;
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return;
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}
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}
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for (u32 rt = 0; rt < static_cast<u32>(frag_colors.size()); ++rt) {
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for (u32 rt = 0; rt < static_cast<u32>(std::size(frag_colors)); ++rt) {
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if (!specialization.enabled_rendertargets[rt]) {
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if (!IsRenderTargetEnabled(rt)) {
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continue;
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continue;
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}
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}
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const Id id = AddGlobalVariable(OpVariable(t_out_float4, spv::StorageClass::Output));
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const Id id = AddGlobalVariable(OpVariable(t_out_float4, spv::StorageClass::Output));
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Name(id, fmt::format("frag_color{}", rt));
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Name(id, fmt::format("frag_color{}", rt));
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Decorate(id, spv::Decoration::Location, rt);
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Decorate(id, spv::Decoration::Location, rt);
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@ -852,6 +851,15 @@ private:
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return binding;
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return binding;
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}
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}
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bool IsRenderTargetEnabled(u32 rt) const {
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for (u32 component = 0; component < 4; ++component) {
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if (header.ps.IsColorComponentOutputEnabled(rt, component)) {
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return true;
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}
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}
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return false;
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}
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bool IsInputAttributeArray() const {
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bool IsInputAttributeArray() const {
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return stage == ShaderType::TesselationControl || stage == ShaderType::TesselationEval ||
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return stage == ShaderType::TesselationControl || stage == ShaderType::TesselationEval ||
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stage == ShaderType::Geometry;
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stage == ShaderType::Geometry;
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@ -1889,19 +1897,14 @@ private:
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// rendertargets/components are skipped in the register assignment.
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// rendertargets/components are skipped in the register assignment.
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u32 current_reg = 0;
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u32 current_reg = 0;
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for (u32 rt = 0; rt < Maxwell::NumRenderTargets; ++rt) {
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for (u32 rt = 0; rt < Maxwell::NumRenderTargets; ++rt) {
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if (!specialization.enabled_rendertargets[rt]) {
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// Skip rendertargets that are not enabled
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continue;
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}
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// TODO(Subv): Figure out how dual-source blending is configured in the Switch.
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// TODO(Subv): Figure out how dual-source blending is configured in the Switch.
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for (u32 component = 0; component < 4; ++component) {
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for (u32 component = 0; component < 4; ++component) {
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const Id pointer = AccessElement(t_out_float, frag_colors.at(rt), component);
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if (!header.ps.IsColorComponentOutputEnabled(rt, component)) {
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if (header.ps.IsColorComponentOutputEnabled(rt, component)) {
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continue;
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OpStore(pointer, SafeGetRegister(current_reg));
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++current_reg;
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} else {
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OpStore(pointer, component == 3 ? v_float_one : v_float_zero);
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}
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}
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const Id pointer = AccessElement(t_out_float, frag_colors[rt], component);
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OpStore(pointer, SafeGetRegister(current_reg));
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++current_reg;
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}
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}
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}
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}
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if (header.ps.omap.depth) {
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if (header.ps.omap.depth) {
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@ -102,9 +102,6 @@ struct Specialization final {
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Maxwell::TessellationSpacing spacing{};
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Maxwell::TessellationSpacing spacing{};
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bool clockwise{};
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bool clockwise{};
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} tessellation;
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} tessellation;
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// Fragment specific
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std::bitset<8> enabled_rendertargets;
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};
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};
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// Old gcc versions don't consider this trivially copyable.
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// Old gcc versions don't consider this trivially copyable.
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// static_assert(std::is_trivially_copyable_v<Specialization>);
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// static_assert(std::is_trivially_copyable_v<Specialization>);
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