hipnosuer
/
Zuma
forked from ShuriZma/suyu
1
0
Fork 0
Code Pull Requests Activity

Merge pull request #355 from lioncash/simp 

armemu: Simplify some instructions.
This commit is contained in:
bunnei 2014-12-28 22:20:49 -05:00
parent 5763d40319 6ce2a38ec4
commit df728cb4c2
1 changed files with 148 additions and 231 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

215
src/core/arm/interpreter/armemu.cpp
View File

@ -6266,29 +6266,13 @@ L_stm_s_takeabort:
} }
printf("Unhandled v6 insn: pkh/sxtab/selsxtb\n"); printf("Unhandled v6 insn: pkh/sxtab/selsxtb\n");
break; break;
case 0x6a: {
ARMword Rm;
int ror = -1;
switch (BITS(4, 11)) { case 0x6a: // SSAT, SSAT16, SXTB, and SXTAB
case 0x07:
ror = 0;
break;
case 0x47:
ror = 8;
break;
case 0x87:
ror = 16;
break;
case 0xc7:
ror = 24;
break;
case 0x01:
case 0xf3:
//ichfly
//SSAT16
{ {
const u8 op2 = BITS(5, 7);
// SSAT16
if (op2 == 0x01) {
const u8 rd_idx = BITS(12, 15); const u8 rd_idx = BITS(12, 15);
const u8 rn_idx = BITS(0, 3); const u8 rn_idx = BITS(0, 3);
const u8 num_bits = BITS(16, 19) + 1; const u8 num_bits = BITS(16, 19) + 1;
@ -6316,77 +6300,58 @@ L_stm_s_takeabort:
state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi & 0xFFFF) << 16); state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi & 0xFFFF) << 16);
return 1; return 1;
} }
else if (op2 == 0x03) {
const u8 rotation = BITS(10, 11) * 8;
u32 rm = ((state->Reg[BITS(0, 3)] >> rotation) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotation)) & 0xFF) & 0xFF);
if (rm & 0x80)
rm |= 0xffffff00;
default: // SXTB, otherwise SXTAB
break;
}
if (ror == -1) {
if (BITS(4, 6) == 0x7) {
printf("Unhandled v6 insn: ssat\n");
return 0;
}
break;
}
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF);
if (Rm & 0x80)
Rm |= 0xffffff00;
if (BITS(16, 19) == 0xf) if (BITS(16, 19) == 0xf)
/* SXTB */ state->Reg[BITS(12, 15)] = rm;
state->Reg[BITS(12, 15)] = Rm;
else else
/* SXTAB */ state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm;
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
return 1; return 1;
} }
case 0x6b: else {
printf("Unimplemented op: SSAT");
}
}
break;
case 0x6b: // REV, REV16, SXTH, and SXTAH
{ {
ARMword Rm; const u8 op2 = BITS(5, 7);
int ror = -1;
switch (BITS(4, 11)) { // REV
case 0x07: if (op2 == 0x01) {
ror = 0;
break;
case 0x47:
ror = 8;
break;
case 0x87:
ror = 16;
break;
case 0xc7:
ror = 24;
break;
case 0xf3: // REV
DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24); DEST = ((RHS & 0xFF) << 24) | ((RHS & 0xFF00)) << 8 | ((RHS & 0xFF0000) >> 8) | ((RHS & 0xFF000000) >> 24);
return 1; return 1;
case 0xfb: // REV16 }
// REV16
else if (op2 == 0x05) {
DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8); DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00)) >> 8 | ((RHS & 0xFF0000) << 8) | ((RHS & 0xFF000000) >> 8);
return 1; return 1;
default:
break;
} }
else if (op2 == 0x03) {
const u8 rotate = BITS(10, 11) * 8;
if (ror == -1) u32 rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFFFF) & 0xFFFF);
break; if (rm & 0x8000)
rm |= 0xffff0000;
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF); // SXTH, otherwise SXTAH
if (Rm & 0x8000) if (BITS(16, 19) == 15)
Rm |= 0xffff0000; state->Reg[BITS(12, 15)] = rm;
if (BITS(16, 19) == 0xf)
/* SXTH */
state->Reg[BITS(12, 15)] = Rm;
else else
/* SXTAH */ state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm;
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
return 1; return 1;
} }
}
break;
case 0x6c: // UXTB16 and UXTAB16 case 0x6c: // UXTB16 and UXTAB16
{ {
const u8 rm_idx = BITS(0, 3); const u8 rm_idx = BITS(0, 3);
@ -6414,29 +6379,12 @@ L_stm_s_takeabort:
return 1; return 1;
} }
break; break;
case 0x6e: { case 0x6e: // USAT, USAT16, UXTB, and UXTAB
ARMword Rm;
int ror = -1;
switch (BITS(4, 11)) {
case 0x07:
ror = 0;
break;
case 0x47:
ror = 8;
break;
case 0x87:
ror = 16;
break;
case 0xc7:
ror = 24;
break;
case 0x01:
case 0xf3:
//ichfly
//USAT16
{ {
const u8 op2 = BITS(5, 7);
// USAT16
if (op2 == 0x01) {
const u8 rd_idx = BITS(12, 15); const u8 rd_idx = BITS(12, 15);
const u8 rn_idx = BITS(0, 3); const u8 rn_idx = BITS(0, 3);
const u8 num_bits = BITS(16, 19); const u8 num_bits = BITS(16, 19);
@ -6463,84 +6411,53 @@ L_stm_s_takeabort:
state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF); state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF);
return 1; return 1;
} }
else if (op2 == 0x03) {
default: const u8 rotate = BITS(10, 11) * 8;
break; const u32 rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFF) & 0xFF);
}
if (ror == -1) {
if (BITS(4, 6) == 0x7) {
printf("Unhandled v6 insn: usat\n");
return 0;
}
break;
}
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFF) & 0xFF);
if (BITS(16, 19) == 0xf) if (BITS(16, 19) == 0xf)
/* UXTB */ /* UXTB */
state->Reg[BITS(12, 15)] = Rm; state->Reg[BITS(12, 15)] = rm;
else else
/* UXTAB */ /* UXTAB */
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm; state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm;
return 1; return 1;
} }
else {
case 0x6f: { printf("Unimplemented op: USAT");
ARMword Rm; }
int ror = -1; }
switch (BITS(4, 11)) {
case 0x07:
ror = 0;
break;
case 0x47:
ror = 8;
break;
case 0x87:
ror = 16;
break;
case 0xc7:
ror = 24;
break; break;
case 0xfb: // REVSH case 0x6f: // UXTH, UXTAH, and REVSH.
{ {
const u8 op2 = BITS(5, 7);
// REVSH
if (op2 == 0x05) {
DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00) >> 8); DEST = ((RHS & 0xFF) << 8) | ((RHS & 0xFF00) >> 8);
if (DEST & 0x8000) if (DEST & 0x8000)
DEST |= 0xffff0000; DEST |= 0xffff0000;
return 1; return 1;
} }
default: // UXTH and UXTAH
break; else if (op2 == 0x03) {
} const u8 rotate = BITS(10, 11) * 8;
const ARMword rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFFFF) & 0xFFFF);
if (ror == -1) // UXTH
break;
Rm = ((state->Reg[BITS(0, 3)] >> ror) & 0xFFFF) | (((state->Reg[BITS(0, 3)] << (32 - ror)) & 0xFFFF) & 0xFFFF);
/* UXT */
/* state->Reg[BITS (12, 15)] = Rm; */
/* dyf add */
if (BITS(16, 19) == 0xf) { if (BITS(16, 19) == 0xf) {
state->Reg[BITS(12, 15)] = Rm; state->Reg[BITS(12, 15)] = rm;
} }
// UXTAH
else { else {
/* UXTAH */ state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + rm;
/* state->Reg[BITS (12, 15)] = state->Reg [BITS (16, 19)] + Rm; */
// printf("rd is %x rn is %x rm is %x rotate is %x\n", state->Reg[BITS (12, 15)], state->Reg[BITS (16, 19)]
// , Rm, BITS(10, 11));
// printf("icounter is %lld\n", state->NumInstrs);
state->Reg[BITS(12, 15)] = state->Reg[BITS(16, 19)] + Rm;
// printf("rd is %x\n", state->Reg[BITS (12, 15)]);
// exit(-1);
} }
return 1; return 1;
} }
}
case 0x70: case 0x70:
// ichfly // ichfly
// SMUAD, SMUSD, SMLAD, and SMLSD // SMUAD, SMUSD, SMLAD, and SMLSD